54F676LM

54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register December 1994 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode (M) input is HIGH information present on the parallel data (P0 – P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal When M is LOW data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations Features Y Y Y Y 16-bit parallel-to-serial conversion 16-bit serial-in serial-out Chip select control Slim 24 lead 300 mil package Commercial 74F676PC 74F676SPC Military Package Number N24A N24C Package Description 24-Lead (0 600 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 600 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F676DM (Note 2) 54F676SDM (Note 2) 74F676SC (Note 1) 54F676FM (Note 2) 54F676LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24A J24F M24B W24C E28A Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9588 – 3 TL F 9588 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9588 RRD-B30M105 Printed in U S A Logic Symbols IEEE IEC TL F 9588 – 1 Unit Loading Fan Out 54F 74F Pin Names P0 – P15 CS CP M SI SO Description Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output UL HIGH LOW 10 10 10 10 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA TL F 9588 – 4 Functional Description The 16-bit shift register operates in one of three modes as indicated in the Shift Register Operations Table HOLD a HIGH signal on the Chip Select (CS) input prevents clocking and data is stored in the sixteen registers Shift Serial Load data present on the SI pin shifts into the register on the falling edge of CP Data enters the Q0 position and shifts toward Q15 on successive clocks finally appearing on the SO pin Parallel Load data present on P0 – P15 are entered into the register on the falling edge of CP The SO output represents the Q15 register output To prevent false clocking CP must be LOW during a LOWto-HIGH transition of CS Shift Register Operations Table Control Input CS H L L M X L H CP X K K Hold Shift Serial Load Parallel Load Operating Mode H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial K e HIGH-to-LOW Transition Block Diagram TL F 9588 – 5 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 0V 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b 150 VOL IIH IBVI ICEX VID IOD IIL IOS ICC V mA mA mA V mA mA mA mA Min Max Max Max 00 00 Max Max Max 72 3 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL Maximum Clock Frequency Propagation Delay CP to SO 100 45 50 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 110 90 90 11 0 12 5 Max 54F TA VCC e Mil CL e 50 pF Min 45 45 50 17 0 14 5 Max 74F TA VCC e Com CL e 50 pF Min 90 45 50 12 0 13 5 Max MHz ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(L) th(H) tw(H) tw(L) Setup Time HIGH or LOW SI to CP Hold Time HIGH or LOW SI to CP Setup Time HIGH or LOW Pn to CP Hold Time HIGH or LOW Pn to CP Setup Time HIGH or LOW M to CP Hold Time HIGH or LOW M to CP Setup Time LOW CS to CP Hold Time HIGH CS to CP CP Pulse Width HIGH or LOW 40 40 40 40 30 30 40 40 80 80 20 20 10 0 10 0 40 60 Max 54F TA VCC e Mil Min 40 40 40 40 30 30 40 40 80 80 20 20 12 0 10 0 50 90 Max 74F TA VCC e Com Min 40 40 40 40 30 30 40 40 80 80 20 20 10 0 ns 10 0 40 60 ns Max Units ns ns ns 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code Plastic DIP Pe SP e Slim Plastic DIP De Ceramic DIP SD e Slim Ceramic DIP Fe Flatpak Le Leadless Chip Carrier (LCC) Se Small Outline SOIC JEDEC 676 S C X Special Variations QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 5 6 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 7 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0 300 Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 24-Lead (0 300 Wide) Molded Small Outline Package JEDEC NS Package Number M24B 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0 600 Wide) Molded Dual-In-Line Package (P) NS Package Number N24A 24-Lead (0 300 Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register Physical Dimensions inches (millimeters) (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications