54LS113DMQB

54LS113 Dual JK Edge-Triggered Flip-Flop June 1989 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed Input data is transferred to the outputs on the falling edge of the clock pulse Connection Diagram Dual-In-Line Package Logic Symbol TL F 10205 – 2 TL F 10205 – 1 VCC e Pin 14 GND e Pin 7 Order Number 54LS113DMQB 54LS113FMQB or 54LS113LMQB See NS Package Number E20A J14A or W14B Truth Table Inputs tn J L L H H K L H L H Output tn a 1 Q Qn L H Qn Pin Names J1 J2 K1 K2 CP1 CP2 SD1 SD2 Q1 Q2 Q1 Q2 Description Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Set Inputs (Active LOW) Outputs tn e Bit Time before Clock Pulse tn a 1 e Bit Time after Clock Pulse H e HIGH Voltage Level L e LOW Voltage Level Asynchronous Input Low input to SD sets Q to HIGH level Set is independent of clock C1995 National Semiconductor Corporation TL F 10205 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C 54LS b 65 C to a 150 C Storage Temperature Range Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA ts (H) ts (L) th (H) th (L) tw (H) tw (L) tw (L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time Jn or Kn to CPn Hold Time Jn or Kn to CPn CPn Pulse Width SDn Pulse Width LOW b 55 54LS113 Nom 5 Max 55 Units V V 07 b0 4 45 2 V mA mA C ns ns ns ns 4 125 20 20 0 0 20 15 15 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Max Input Voltage High Level Input Current Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V JK SD CP IIH VCC e Max VI e 2 7V JK SD CP IIL IOS ICC Low Level Input Current Short Circuit Output Current Supply Current VCC e Max VI e 0 5V VCC e Max (Note 2) VCC e Max (Note 3) JK CP SD b 30 b 60 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 04 01 03 04 20 60 80 b 400 b 800 b 100 V mA mA mA mA mA 8 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 ICC is measured with all outputs open and all inputs grounded 2 Switching Characteristics VCC e a 5 0V Symbol Parameter TA e a 25 C (See Section 1 for test waveforms and output load) 54LS113 CL e 15 pF Min Max MHz 16 24 16 24 ns ns Units fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay SDn to Qn or Qn 30 Logic Diagram (one half shown) TL F 10205 – 3 3 4 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS113LMQB NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS113DMQB NS Package Number J14A 5 54LS113 Dual JK Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number 54LS113FMQB NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications