54LS256FMQB

54LS256 DM74LS256 Dual 4-Bit Addressable Latch June 1989 54LS256 DM74LS256 Dual 4-Bit Addressable Latch General Description The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 – Q3) When the Enable (E) is HIGH and the Clear input (CL) is LOW all outputs (Q0–Q3) are LOW Dual 4-channel demultiplexing occurs when the CL and E are both LOW When CL is HIGH and E is LOW the selected output (Q0 – Q3) determined by the Address inputs follows D When the E goes HIGH the contents of the latch are stored When operating in the addressable latch mode (E e LOW CL e HIGH) changing more than one bit of the Address (A0 A1) could impose a transient wrong address Therefore this should be done only while in the memory mode (E e CL e HIGH) Features Y Y Y Y Y Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Active low common clear Connection Diagram Dual-In-Line Package Logic Symbol TL F 9823–1 Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Number J16A N16E or W16A Pin Names A0 A1 Da Db E CL Q0a – Q3a Q0b – Q3b Description TL F 9823 – 2 VCC e Pin 16 GND e Pin 8 Common Address Inputs Data Inputs Common Enable Input (Active LOW) Conditional Clear Input (Active LOW) Side A Latch Outputs Side B Latch Outputs C1995 National Semiconductor Corporation TL F 9823 RRD-B30M115 Printed in U S A Truth Table Inputs CL L L L L L H H H H H E H L L L L H L L L L A0 X L H L H X L H L H A1 X L L H H X L L H H Q0 L D L L L Qtb1 D Qtb1 Qtb1 Qtb1 Outputs Q1 L L D L L Qt b 1 Qtb1 D Qt b 1 Qt b 1 Q2 L L L D L Qtb1 Qtb1 Qt b 1 D Qtb1 Q3 L L L L D Qt b 1 Qt b 1 Qt b 1 Qt b 1 D Clear Demultiplex Mode Memory Addressable Latch t b 1 e Bit time before address change or rising edge of E H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Mode Selection E L H L H CL H H L L Mode Addressable Latch Memory Active HIGH 4-Channel Demultiplexers Clear Logic Diagram TL F 9823 – 3 2 Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA ts (H) th (H) ts (L) th (L) ts (H) ts (L) tw (L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH Dn to E Hold Time HIGH Dn to E Setup Time LOW Dn to E Hold Time LOW Dn to E Setup Time HIGH or LOW An to E E Pulse Width LOW b 55 54LS256 Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS256 Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA C ns ns ns ns ns ns 4 125 0 20 0 15 0 0 17 8 70 20 0 15 0 0 17 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VCC e Min IOL e Max VIH e Min IOL e 4 mA VCC e Min II IIH IIL IOS ICC Input Current Input Voltage Max VCC e Max VI e 10V VCC e Max VI e 2 7V VCC e Max VI e 0 4V VCC e Max (Note 2) VCC e Max 54LS DM74 54LS DM74 DM74 Inputs E Inputs E Low Level Input Current Inputs E Short Circuit Output Current Supply Current 54LS DM74 b 20 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 27 34 04 0 35 0 25 05 04 01 02 20 40 b0 4 b0 8 b 100 b 100 V mA High Level Input Current mA mA mA mA 25 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second 3 Switching Characteristics VCC e a 5 0V TA e a 25 C (See Section 1 for waveforms and load configurations) Symbol Parameter RL e 2 kX CL e 15 pF Max tPLH tPHL tPLH tPHL tPLH tPHL tPLH Propagation Delay E to Qn Propagation Delay Dn to Qn Propagation Delay An to Qn Propagation Delay CL to Qn 27 24 30 20 30 29 18 ns ns ns ns Units 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS256DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS256N NS Package Number N16E 5 54LS256 DM74LS256 Dual 4-Bit Addressable Latch Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS256FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National 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