5962-95833

DS90C031 LVDS Quad CMOS Differential Line Driver June 1998 DS90C031 LVDS Quad CMOS Differential Line Driver General Description The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90C031 accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE ® function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 11 mW typical. The DS90C031 and companion line receiver (DS90C032) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. Features n n n n n n n n n > 155.5 Mbps (77.7 MHz) switching rates ± 350 mV differential signaling Ultra low power dissipation 400 ps maximum differential skew (5V, 25˚C) 3.5 ns maximum propagation delay Industrial operating temperature range Military operating temperature range option Available in surface mount packaging (SOIC) and (LCC) Pin compatible with DS26C31, MB571 (PECL) and 41LG (PECL) n Compatible with IEEE 1596.3 SCI LVDS standard n Conforms to ANSI/TIA/EIA-644 LVDS standard n Available to Standard Microcircuit Drawing (SMD) 5962-95833 Connection Diagrams Dual-In-Line LCC Package DS011946-1 Order Number DS90C031TM See NS Package Number M16A DS011946-33 Order Number DS90C031E-QML See NS Package Number E20A For Complete Military Specifications, refer to appropriate SMD or MDS. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS011946 www.national.com Functional Diagram DS011946-2 Truth Table DRIVER Enables EN L All other combinations of ENABLE inputs EN* H Input DIN X L H Z L H Outputs DOUT+ DOUT− Z H L www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +6V −0.3V to (VCC + 0.3V) Input Voltage (DIN) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) Output Voltage (DOUT+, DOUT−) Short Circuit Duration Continuous (DOUT+, DOUT−) Maximum Package Power Dissipation @ +25˚C M Package 1068 mW E Package 1900 mW Derate M Package 8.5 mW/˚C above +25˚C Derate E Package 12.8 mW/˚C above +25˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature Range Soldering (4 sec.) +260˚C Maximum Junction Temperature (DS90C031T) Maximum Junction Temperature (DS90C031E) ESD Rating (Note 7) (HBM, 1.5 kΩ, 100 pF) (EIAJ, 0 Ω, 200 pF) +150˚C +175˚C ≥ 3,500V ≥ 250V Recommended Operating Conditions Min +4.5 Supply Voltage (VCC) Operating Free Air Temperature (TA) DS90C031T −40 DS90C031E −55 Typ +5.0 +25 +25 Max +5.5 +85 +125 Units V ˚C ˚C Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol VOD1 ∆VOD1 Parameter Differential Output Voltage Change in Magnitude of VOD1 for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Input Current Input Clamp Voltage Output Short Circuit Current Output TRI-STATE Current No Load Supply Current Drivers Enabled Loaded Supply Current Drivers Enabled No Load Supply Current Drivers Disabled VIN = VCC, GND, 2.5V or 0.4V ICL = −18 mA VOUT = 0V (Note 8) EN = 0.8V and EN* = 2.0V, VOUT = 0V or VCC DIN = VCC or GND DIN = 2.5V or 0.4V RL = 100Ω All Channels VIN = VCC or GND (all inputs) DIN = VCC or GND EN = GND, EN* = VCC DS90C031T DS90C031E DS90C031T DS90C031E DS90C031T DOUT−, DOUT+ VCC DIN, EN, EN* RL = 100Ω 0.90 2.0 GND −10 −1.5 −10 Conditions RL = 100Ω (Figure 1) Pin DOUT−, DOUT+ Min 250 Typ 345 4 Max 450 35 Units mV |mV| VOS ∆VOS VOH VOL VIH VIL II VCL IOS IOZ ICC ICCL 1.125 1.25 5 1.41 1.07 1.375 25 1.60 VCC 0.8 V |mV| V V V V µA V mA µA mA mA mA mA mA mA ±1 −0.8 −3.5 +10 −5.0 +10 3.0 6.5 21.0 25.0 4.0 10.0 ±1 1.7 4.0 15.4 15.4 2.2 2.2 ICCZ Switching Characteristics VCC = +5.0V, TA = +25˚C DS90C031T. (Notes 3, 4, 6, 9) Symbol tPHLD tPLHD tSKD tSK1 Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew |tPHLD – tPLHD| Channel-to-Channel Skew (Note 4) Conditions RL = 100Ω, CL = 5 pF (Figure 2 and Figure 3) Min 1.0 1.0 0 0 Typ 2.0 2.1 80 300 Max 3.0 3.0 400 600 Units ns ns ps ps 3 www.national.com Switching Characteristics Symbol tTLH tTHL tPHZ tPLZ tPZH tPZL Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Parameter (Continued) VCC = +5.0V, TA = +25˚C DS90C031T. (Notes 3, 4, 6, 9) Conditions Min Typ 0.35 0.35 RL = 100Ω, CL = 5 pF (Figure 4 and Figure 5) 2.5 2.5 2.5 2.5 Max 1.5 1.5 10 10 10 10 Units ns ns ns ns ns ns Switching Characteristics VCC = +5.0V ± 10%, TA = −40˚C to +85˚C DS90C031T. (Notes 3, 4, 5, 6, 9) Symbol tPHLD tPLHD tSKD tSK1 tSK2 tTLH tTHL tPHZ tPLZ tPZH tPZL Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew |tPHLD – tPLHD| Channel-to-Channel Skew (Note 4) Chip to Chip Skew (Note 5) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low RL = 100Ω, CL = 5 pF (Figure 4 and Figure 5) 0.35 0.35 2.5 2.5 2.5 2.5 Conditions RL = 100Ω, CL = 5 pF (Figure 2 and Figure 3) Min 0.5 0.5 0 0 Typ 2.0 2.1 80 0.3 Max 3.5 3.5 900 1.0 3.0 2.0 2.0 15 15 15 15 Units ns ns ps ns ns ns ns ns ns ns ns Switching Characteristics VCC = +5.0V ± 10%, TA = −55˚C to +125˚C DS90C031E. (Notes 3, 4, 5, 6, 9, 10) Symbol tPHLD tPLHD tSKD tSK1 tSK2 tPHZ tPLZ tPZH tPZL Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew |tPHLD – tPLHD| Channel-to-Channel Skew (Note 4) Chip to Chip Skew (Note 5) Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low RL = 100Ω, CL = 5 pF (Figure 4 and Figure 5) 2.5 2.5 2.5 2.5 Conditions RL = 100Ω, CL = 20 pF (Figure 3) CL Connected between each Output and GND Min 0.5 0.5 0 0 Typ 2.0 2.1 0.08 0.3 Max 5.0 5.0 3.0 3.0 4.5 20 20 20 20 Units ns ns ns ns ns ns ns ns ns Parameter Measurement Information DS011946-3 FIGURE 1. Driver VOD and VOS Test Circuit www.national.com 4 Parameter Measurement Information (Continued) DS011946-4 FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit DS011946-5 FIGURE 3. Driver Propagation Delay and Transition Time Waveforms DS011946-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit 5 www.national.com Parameter Measurement Information (Continued) DS011946-7 FIGURE 5. Driver TRI-STATE Delay Waveform Typical Application DS011946-8 FIGURE 6. Point-to-Point Application Applications Information LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90C031 differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The typical output current is mere 3.4 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termi- nation be employed to terminate the signal and to complete the loop as shown in Figure 6. AC or unterminated configurations are not allowed. The 3.4 mA loop current will develop a differential voltage of 340 mV across the 100Ω termination resistor which the receiver detects with a 240 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340 mV – 100 mV = 240 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown inFigure 7. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 680 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. www.national.com 6 Applications Information (Continued) The footprint of the DS90C031 is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver. DS011946-9 FIGURE 7. Driver Output Levels Pin Descriptions Pin No. (SOIC) 1, 7, 9, 15 2, 6, 10, 14 3, 5, 11, 13 4 12 DIN DOUT+ DOUT− EN EN* Driver input pin, TTL/CMOS compatible Non-inverting driver output pin, LVDS levels Inverting driver output pin, LVDS levels Active high enable pin, OR-ed with EN* Active low enable pin, OR-ed with EN Name Description Pin No. (SOIC) 16 8 Name VCC GND Description Power supply pin, +5V ± 10% Ground pin Ordering Information Operating Temperature −40˚C to +85˚C −55˚C to +125˚C DS90C031E-QML 5962-95833 Package Type/ Number SOP/M16A LCC/E20A (NSID) (SMD) DS90C031TM DS90C031E-QML Order Number Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and ∆VOD1. Note 3: All typicals are given for: VCC = +5.0V, TA = +25˚C. Note 4: Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. Note 5: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 6: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns. Note 7: ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥ 3,500V EIAJ (0Ω, 200 pF) ≥ 250V Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 9: CL includes probe and jig capacitance. Note 10: Guaranteed by characterization data (DS90C031E). 7 www.national.com Typical Performance Characteristics Power Supply Current vs Power Supply Voltage Power Supply Current vs Temperature DS011946-10 DS011946-11 Power Supply Current vs Power Supply Voltage Power Supply Current vs Temperature DS011946-12 DS011946-13 Output TRI-STATE Current vs Power Supply Voltage Output Short Circuit Current vs Power Supply Voltage DS011946-14 DS011946-15 www.national.com 8 Typical Performance Characteristics Differential Output Voltage vs Power Supply Voltage (Continued) Differential Output Voltage vs Ambient Temperature DS011946-16 DS011946-17 Output Voltage High vs Power Supply Voltage Output Voltage High vs Ambient Temperature DS011946-18 DS011946-19 Output Voltage Low vs Power Supply Voltage Output Voltage Low vs Ambient Temperature DS011946-20 DS011946-21 9 www.national.com Typical Performance Characteristics Offset Voltage vs Power Supply Voltage (Continued) Offset Voltage vs Ambient Temperature DS011946-22 DS011946-23 Power Supply Current vs Frequency Power Supply Current vs Frequency DS011946-24 DS011946-25 Differential Output Voltage vs Load Resistor Differential Propagation Delay vs Power Supply Voltage DS011946-26 DS011946-27 www.national.com 10 Typical Performance Characteristics Differential Propagation Delay vs Ambient Temperature (Continued) Differential Skew vs Power Supply Voltage DS011946-29 DS011946-28 Differential Skew vs Ambient Temperature Differential Transition Time vs Power Supply Voltage DS011946-30 DS011946-31 Differential Transition Time vs Ambient Temperature DS011946-32 11 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier, Type C Order Number DS90C031E-QML NS Package Number E20A 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90C031TM NS Package Number M16A 13 www.national.com DS90C031 LVDS Quad CMOS Differential Line Driver LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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