74F402PC

54F 74F402 Serial Data Polynomial Generator Checker January 1995 54F 74F402 Serial Data Polynomial Generator Checker General Description The ’F402 expandable Serial Data Polynomial generator checker is an expandable version of the ’F401 It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems A 4-bit control input selects one-of-six generator polynomials The list of polynomials includes CRC-16 CRCCCITT and Ethernet as well as three other standard polynomials (56th order 48th order 32nd order) Individual clear and preset inputs are provided for floppy disk and other applications The Error output indicates whether or not a transmission error has occurred The CWG Control input inhibits feedback during check word transmission The ’F402 is compatible with FAST devices and with all TTL families Features Y Y Y Y Y Y Y Y Guaranteed 30 MHz data rate Six selectable polynomials Other polynomials available Separate preset and clear controls Expandable Automatic right justification Error output open collector Typical applications Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems Commercial 74F402PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F402DM (Note 1) 54F402FM (Note 1) 54F402LM (Note 1) J16A W16A E20A Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbol Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9535 – 1 TL F 9535 – 2 TL F 9535–4 TRI-STATE is a registered trademark of National Semiconductor Corporation Ethernet is a registered trademark of Xerox Corporation C1995 National Semiconductor Corporation TL F 9535 RRD-B30M105 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 1 0 0 67 1 0 0 67 285(100) 13 3(6 7) 1 0 0 67 26 7(13 3) 285(100) 13 3(6 7) 1 0 0 67 1 0 0 67 1 0 0 67 1 0 0 67 1 0 0 67 Input IIH IIL Output IOH IOL 20 mA b0 4 mA 20 mA b0 4 mA b 5 7 mA( b 2 mA) 8 mA (4 mA) 20 mA b0 4 mA 16 mA (8 mA) b 5 7 mA( b 2 mA) 8 mA (4 mA) 20 mA b0 4 mA 20 mA b0 4 mA 20 mA b0 4 mA 20 mA b0 4 mA 20 mA b0 4 mA S0 – S3 CWG D CW D ER RO CP SEI RFB MR P Open Collector Polynomial Select Inputs Check Word Generate Input Serial Data Check Word Data Input Error Output Register Output Clock Pulse Serial Expansion Input Register Feedback Master Reset Preset Functional Description The ’F402 Serial Data Polynomial Generator Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic For encoding the data stream (message polynomial) is divided by a selected polynomial This division results in a remainder (or residue) which is appended to the message as check bits For error checking the bit stream containing both data and check bits is divided by the same selected polynomial If there are no detectable errors this division results in a zero remainder Although it is possible to choose many generating polynomials of a given degree standards exist that specify a small number of useful polynomials The ’F402 implements the polynomials listed in Table I by applying the appropriate logic levels to the select pins S0 S1 S2 and S3 The ’F402 consists of a 16-bit register a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram The polynomial control code presented at inputs S0 S1 S2 and S3 is decoded by the ROM selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs To generate the check bits the data stream is entered via the Data Inputs (D) using the LOW-to-HIGH transition of the Clock Input (CP) This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB) and controls the XOR gates The Check Word Generate (CWG) must be held HIGH while the data is being entered After the last data bit is entered the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed) To check an incoming message for errors both the data and check bits are entered through the D Input with the CWG Input held HIGH The Error Output becomes valid after the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP with the exception of the Ethernet polynomial (see Applications paragraph) If no detectable errors have occurred during the data transmission the resultant internal register bits are all LOW and the Error Output (ER) is HIGH If a detectable error has occurred ER is LOW ER remains valid until the next LOW-to-HIGH transition of CP or until the device has been preset or reset A HIGH on the Master Reset Input (MR) asynchronously clears the entire register A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of 1 The Ethernet residue selection in which the registers containing the non-zero residue are cleared 2 The 56th order polynomial in which the 8 least significant register bits of the least significant device are cleared and 3 Register S e 0 in which all bits are cleared 2 TABLE I Hex 0 C D E F 7 B 3 2 4 8 5 9 1 6 A S3 L H H H H L H L L L H L H L L H Select Code S2 S1 L H H H H H L L L H L H L L H L L L L H H H H H H L L L L L H H S0 L L H L H H H H L L L H H H L L 0 X32 a X26 a X23 a X22 a X16 a X12 a X11 a X10 a X8 a X7 a X5 a X4 a X2 a X a 1 X32 a X31 a X27 a X26 a X25 a X19 a X16 a X15 a X13 a X12 a X11 a X9 a X7 a X6 a X5 a X4 a X2 a X a 1 X16 a X15 a X2 a 1 X16 a X12 a X5 a 1 X56 a X55 a X49 a X45 a X41 a X39 a X38 a X37 a X36 a X31 a X22 a X19 a X17 a X16 a X15 a X14 a X12 a X11 a X9 a X5 a X a 1 X48 a X36 a X35 a X23 a X21 a X15 a X13 a X8 a X2 a 1 X32 a X23 a X21 a X11 a X2 a 1 56th Order Polynomial Remarks Se0 Ethernet Polynomial Ethernet Residue CRC-16 CRC-CCITT 48th Order 32nd Order Block Diagram TL F 9535 – 5 3 TABLE II Select Code 0 C D E F 7 B 3 2 4 8 5 9 1 6 A P3 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 P2 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 P1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 P0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 C2 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 C1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 C0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Polynomial Se0 Ethernet Polynomial Ethernet Residue CRC-16 CRC-CCITT 56th Order 48th Order 32nd Order Applications In addition to polynomial selection there are four other capabilities provided for in the ’F402 ROM The first is set or clear selectability The sixteen internal registers have the capability to be either set or cleared when P is brought LOW This set or clear capability is done in four groups of 4 (see Table II P0 – P3) The second ROM capability (C0) is in determining the polarity of the check word As is the case with the Ethernet polynomial the check word can be inverted when it is appended to the data stream or as is the case with the other polynomials the residue is appended with no inversion Thirdly the ROM contains a bit (C1) which is used to select the RFB input instead of the SEI input to be fed into the LSB This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomial or a residue If the latter then it inhibits the RFB input As mentioned previously upon a successful data transmission the CRC register has a zero residue There is an exception to this however with respect to the Ethernet polynomial This polynomial upon a successful data transmission has a non-zero residue in the CRC register (C7 04 DD 7B)16 In order to provide a no-error indication two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one additional time after the last check bit has been entered will result in zeroing the CRC register In this manner a no-error indication is achieved With the present mix of polynomials the largest is 56th order requiring four devices while the smallest is 16th order requiring just one device In order to accommodate multiplexing between high order polynomials (X 16th order) and lower order polynomials a location of all zeros is provided This allows the user to choose a lower order polynomial even if the system is configured for a higher order one The ’F402 expandable CRC generator checker contains 6 popular CRC polynomials 2-16th Order 2-32nd Order 148th Order and 1-56th Order The application diagram shows the ’F402 connected for a 56th Order polynomial Also shown are the input patterns for other polynomials When the ’F402 is used with a gated clock disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled Preset and Master Reset are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and 56th Order select code 8 LSB are exceptions to this) To generate a CRC the pattern for the selected polynomial is applied to the S inputs the register is preset or cleared as required clock is enabled CWG is set HIGH data is applied to D input output data is on D CW When the last data bit has been entered CWG is set LOW and the register is clocked for n bits (where n is the order of the polynomial) The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D CW after the residue has been shifted out) To check a CRC the pattern for the selected polynomial is applied to the S inputs the register is preset or cleared as required clock is enabled CWG is set HIGH the data stream including the CRC is applied to D input When the last bit of the CRC has been entered the ER output is checked HIGH e error free data LOW e corrupt data The clock may now be stopped if desired To implement polynomials of lower order than 56th select the number of packages required for the order of polynomial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain) 4 Applications (Continued) TL F 9535 – 6 5 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75 b0 4 b 20 b 130 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b2 mA (RO D CW) IOH e b5 7 mA (RO D CW) IOH e b5 7 mA (RO D CW) IOL IOL IOL IOL e e e e 24 24 27 04 04 05 05 20 0 50 100 70 250 50 VOL V Min 4 mA (D CW RO) 8 mA (ER) 16 mA (ER) 8 mA (D CW RO) IIH IBVI ICEX VID IOD IIL IOS IOHC ICC Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current mA mA mA V mA mA mA mA mA Max Max Max 00 00 Max Max Min Max VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 0V (D CW RO) VOUT e VCC (ER) Output Short-Circuit Current Open Collector Output OFF Leakage Test Power Supply Current 250 110 165 6 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPLH tPHL tPHL tPLH tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to D CW Propagation Delay CP to RO Propagation Delay CP to ER Propagation Delay P to D CW Propagation Delay P to RO Propagation Delay P to ER Propagation Delay MR to D CW Propagation Delay MR to RO Propagation Delay MR to ER Propagation Delay D to D CW Propagation Delay CWG to D CW Propagation Delay Sn to D CW 30 85 10 5 80 80 15 5 85 11 0 11 5 95 10 0 10 5 11 0 90 16 5 60 75 65 70 11 5 95 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 45 15 0 18 0 13 5 14 0 26 0 14 5 18 5 19 5 16 0 17 0 18 0 19 0 15 5 28 0 10 5 12 0 11 0 12 0 19 5 16 0 19 0 23 0 17 0 18 0 33 0 18 5 23 5 24 5 20 5 21 5 23 0 24 0 19 5 35 5 13 5 16 0 14 0 15 5 24 5 20 0 Max 54F TA VCC e Mil CL e 50 pF Min 30 75 95 70 70 14 0 75 10 0 10 5 85 90 95 10 0 80 14 5 50 65 55 60 90 85 26 5 26 5 26 0 22 5 38 5 23 5 31 0 32 0 31 5 26 0 29 0 28 5 23 5 39 0 19 5 20 0 21 5 21 5 29 0 25 0 Max 74F TA VCC e Com CL e 50 pF Min 30 75 95 70 70 14 0 75 10 0 10 5 85 90 95 10 0 80 14 5 50 65 55 60 10 5 85 21 0 25 0 19 0 20 0 35 0 20 5 25 5 26 5 22 5 23 5 25 5 26 0 21 5 37 5 15 0 18 0 15 5 17 5 26 5 22 0 Max MHz ns ns ns ns ns ns ns ns ns ns ns ns Units 7 AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) trec trec Setup Time HIGH or LOW SEI to CP Hold Time HIGH or LOW SEI to CP Setup Time HIGH or LOW RFB to CP Hold Time HIGH or LOW RFB to CP Setup Time HIGH or LOW S1 to CP Hold Time HIGH or LOW S1 to CP Setup Time HIGH or LOW D to CP Hold Time HIGH or LOW D to CP Setup Time HIGH or LOW CWG to CP Hold Time HIGH or LOW CWG to CP Clock Pulse Width HIGH or LOW MR Pulse Width HIGH P Pulse Width LOW Recovery Time MR to CP Recovery Time P to CP 45 45 0 0 11 0 11 0 0 0 13 5 13 0 0 0 90 90 0 0 70 55 0 0 40 40 40 40 30 50 Max 54F TA VCC e Mil Min 60 60 10 10 14 0 14 0 0 0 16 0 15 5 0 0 11 5 11 5 0 0 90 80 0 0 70 50 70 50 40 65 Max 74F TA VCC e Com Min 50 50 0 0 12 5 12 5 0 0 15 0 14 5 0 0 10 0 10 0 0 0 80 65 0 0 45 45 45 45 35 ns 60 ns ns ns Max Units ns ns ns ns ns 8 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) 402 P C Special Variations QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 9 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 10 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 300 Wide) Molded Plastic Dual-In-Line Package (P) NS Package Number N16E 11 54F 74F402 Serial Data Polynomial Generator Checker Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications