54F 74F563 Octal D-Type Latch with TRI-STATE Outputs
May 1995
54F 74F563 Octal D-Type Latch with TRI-STATE Outputs
General Description
The ’F563 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs This device is functionally identical to the ’F573 but has inverted outputs
Features
Y Y Y
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F573
Commercial 74F563PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F563DM (Note 2) 74F563SC (Note 1) 74F563SJ (Note 1) 54F563FM (Note 2) 54F563LM (Note 2)
J20A M20B M20D W20A E20A
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9562 – 3
TL F 9562 – 5
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 3 mA 24 mA (20 mA)
D0 – D7 LE OE O0 – O7
Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9562 RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9562 – 2 TL F 9562–1
Functional Description
The ’F563 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Inputs OE H H H H L L L LE X H H L H H L D X L H X L H X
Function Table Internal Q X H L NC H L NC Output O Z Z Z Z H L NC High Z High Z High Z Latched Transparent Transparent Latched Function
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance NC e No Change
Logic Diagram
TL F 9562 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin
b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150
Recommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V
C C C C
b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75
b0 6
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V Min
IIN e b18 mA IOH IOH IOH IOH IOH IOH
e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA
25 24 25 24 27 27 05 05 20 0 50 100 70 250 50
V
Min
VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCL ICCZ
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
V mA mA mA V mA mA mA mA mA mA mA mA
Min Max Max Max 00 00 Max Max Max Max 0 0V Max Max
IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V VO e LOW VO e HIGH Z
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current 40 40 3
b 60
50
b 50 b 150
500 61 61
AC Electrical Characteristics
74F Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 35 25 45 30 20 30 15 15 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 85 65 95 70 75 85 55 55 54F TA VCC e Mil CL e 50 pF Min 30 20 40 25 20 25 15 15 Max 10 5 75 11 0 75 95 10 0 70 55 74F TA VCC e Com CL e 50 pF Min 30 20 40 25 20 15 15 15 Max 95 70 10 5 70 90 95 65 55 ns ns Units
ns
AC Operating Requirements
74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) tw(H) Setup Time HIGH or LOW Dn to LE Hold Time HIGH or LOW Dn to LE LE Pulse Width HIGH 20 20 30 30 40 Max 54F TA VCC e Mil Min 20 20 30 30 40 Max 74F TA VCC e Com Min 20 20 30 30 40 Max ns ns ns Units
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 563 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C)
4
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A
20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0 300 Wide) Molded Small Outline Package EIAJ NS Package Number M20D
20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A
7
54F 74F563 Octal D-Type Latch with TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F) NS Package Number W20A
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