74F632VC

DP8406 (54F 74F632) 32-Bit Parallel Error Detection and Correction Circuit May 1991 DP8406 (54F 74F632) 32-Bit Parallel Error Detection and Correction Circuit General Description The DP8406 device is a 32-bit parallel error detection and correction circuit (EDAC) in a 52-pin or 68-pin package The EDAC uses a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDAC to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and corrected Single-bit errors in the 7-bit check word are flagged and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location Dual-bit errors are flagged but not corrected These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word two errors in the 7-bit check word or one error in each word) The gross-error condition of all LOWs or all HIGHs from memory will be detected Otherwise errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect Read-modify-write (byte-control) operations can be performed by using output latch enable LEDBO and the individual OEB0 through OEB3 byte control pins Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the Data Bit and Check Bit input latches These will determine if the failure occurred in memory or in the EDAC Features Y Y Y Y Y Y Y Detects and corrects single-bit errors Detects and flags dual-bit errors Built-in diagnostic capability Fast write and read cycle processing times Byte-write capability Guaranteed 4000V minimum ESD protection Fully pin and function compatible with SN74ALS632A thru SN74ALS635 series TI’s Simplified Functional Block TL F 9579 – 9 Device DP8406 DP8406 Package 52-Pin 68-Pin Byte-Write yes yes Output TRI-STATE TRI-STATE FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9579 RRD-B30M105 Printed in U S A Logic Symbol TL F 9579 – 1 Unit Loading Fan Out 54F 74F Pin Names CB0 – CB6 DB0 – DB31 OEB0 – OEB3 LEDBO OECB S0 S1 ERR MERR Description Check Word Bit Input or TRI-STATE Output Data Word Bit Input or TRI-STATE Output Output Enable Data Bits Output Latch Enable Data Bit Output Enable Check Bit Select Pins Single Error Flag Multiple Error Flag UL HIGH LOW 3 5 1 083 150 40 (33 3) 3 5 1 083 150 40 (33 3) 10 10 10 10 10 10 10 10 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 70 mA b650 mA b 3 mA 24 mA (20 mA) 70 mA b650 mA b 3 mA 24 mA (20 mA) 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA b 1 mA 20 mA Connection Diagrams Pin Assignment for LCC and PCC 52-Pin Pin Assignment for LCC and PCC 68-Pin TL F 9579–3 Order Number DP8406QV (74F632QC) See NS Package Number V52A NC No internal connection TL F 9579 – 8 Order Number DP8406V (74F632VC) See NS Package Number V68A 2 Connection Diagram (Continued) Pin Assignment for Side Brazed DIP Functional Description MEMORY WRITE CYCLE DETAILS During a memory write cycle the check bits (CB0 through CB6) are generated internally in the EDAC by seven 16-input parity generators using the 32-bit data word as defined in Table II These seven check bits are stored in memory along with the original 32-bit data word This 32-bit word will later be used in the memory read cycle for error detection and correction ERROR DETECTION AND CORRECTION DETAILS During a memory read cycle the 7-bit check word is retrieved along with the actual data In order to be able to determine whether the data from memory is acceptable to use as presented to the bus the error flags must be tested to determine if they are at the HIGH level The first case in Table III represents the normal no-error conditions The EDAC presents HIGHs on both flags The next two cases of single-bit errors give a HIGH on MERR and a LOW on ERR which is the signal for a correctable error and the EDAC should be sent through the correction cycle The last three cases of double-bit errors will cause the EDAC to signal LOWs on both ERR and MERR which is the interrupt indication for the CPU Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied to internal parity generators checkers If the parity of all seven groupings of data and check bits is correct it is assumed that no error has occurred and both error flags will be HIGH TL F 9579 – 2 Order Number DP8406D (74F632DC) See NS Package Number D52A TABLE I Write Control Function Memory Cycle Write EDAC Function Generate Check Word Control S1 S0 L L DB Control OEBn H DB Output Latch LEDBO X CB Control OECB L Error Flags ERR MERR H H Data I O Check I O Output Check Bit Input See Table II for details of check bit generation 3 Functional Description (Continued) TABLE II Parity Algorithm 32-Bit Data Word Check Word Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CB0 CB1 CB2 CB3 CB4 CB5 CB6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X XX XXXXXXXX X X X X X X X X X XX XXXX X X XXX XXXXXX X X X XX X XXX X XX The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit TABLE III Error Function Total Number of Errors 32-Bit Data Word 0 1 0 1 2 0 H e HIGH Voltage Level L e LOW Voltage Level Error Flags ERR H L L L L L MERR H H H L L L Data Correction Not Applicable Correction Correction Interrupt Interrupt Interrupt 7-Bit Check Word 0 0 1 1 0 2 If the parity of one or more of the check groups is incorrect an error has occurred and the proper error flag or flags will be set LOW Any single error in the 32-bit data word will change the state of either three or five bits of the 7-bit check word Any single error in the 7-bit check word changes the state of only that one bit In either case the single error flag (ERR) will be set LOW while the dual error flag (MERR) will remain HIGH Any 2-bit error will change the state of an even number of check bits The 2-bit error is not correctable since the parity tree can only identify single-bit errors Both error flags are set LOW when any 2-bit error is detected Three or more simultaneous bit errors can cause the EDAC to believe that no error a correctable error or an uncorrectable error has occurred and will produce erroneous results in all three cases It should be noted that the gross-error conditions of all LOWs and all HIGHs will be detected As the corrected word is made available on the data I O port (DB0 through DB31) the check word I O port (CB0 through CB6) presents a 7-bit syndrome error code This syndrome error code can be used to locate the bad memory chip See Table V for syndrome decoding READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS The ’F632 device is capable of byte-write operations The 39-bit word from memory must first be latched into the Data Bit and Check Bit input latches This is easily accomplished by switching from the read and flag mode (S1 e H S0 e L) to the latch input mode (S1 e H S0 e H) The EDAC will then make any corrections if necessary to the data word and place it at the input of the output data latch This data word must then be latched into the output data latch by taking LEDBO from a LOW to a HIGH 4 Byte control can now be employed on the data word through the OEB0 through OEB3 controls OEB0 controls DB0 –DB7 (byte 0) OEB1 controls DB8 –DB15 (byte 1) OEB2 controls DB16 –DB23 (byte 2) and OEB3 controls DB24 –DB31 (byte 3) Placing a HIGH on the byte control will disable the output and the user can modify the byte If a LOW is placed on the byte control then the original byte is allowed to pass onto the data bus unchanged If the original data word is altered through byte control a new check word must be generated before it is written back into memory This is easily accomplished by taking controls S1 and S0 LOW Table VI lists the read-modify-write functions DIAGNOSTIC OPERATIONS The ’F632 is capable of diagnostics that allow the user to determine whether the EDAC or the memory is failing The diagnostic function tables will help the user to see the possibilities for diagnostic control In the diagnostic mode (S1 e L S0 e H) the check word is latched into the input latch while the data input latch remains transparent This lets the user apply various data words against a fixed known check word If the user applies a diagnostic data word with an error in any bit location the ERR flag should be LOW If a diagnostic data word with two errors in any bit location is applied the MERR flag should be LOW After the check word is latched into the input latch it can be verified by taking OECB LOW This outputs the latched check word The diagnostic data word can be latched into the output data latch and verified By changing from the diagnostic mode (S1 e L S0 e H) to the correction mode (S1 e H S0 e H) the user can verify that the EDAC will correct the diagnostic data word Also the syndrome bits can be produced to verify that the EDAC pinpoints the error location Table VII lists the diagnostic functions Functional Description (Continued) TABLE IV Read Flag and Correct Function Memory Cycle Read Read EDAC Function Read Flag Control S1 S0 H H L H Data I O Input Latched Input Data Output Corrected Data Word DB Control OEBn H H DB Output Latch LEDBO X L Check I O Input Latched Input Check Word Output Syndrome Bits (Note 2) CB Control OECB H H Error Flags ERR MERR Enabled (Note 1) Enabled (Note 1) Latch Input Data Check Bits Output Corrected Data Syndrome Bits Read H H L X L Enabled (Note 1) Note 1 See Table III for error description Note 2 See Table V for error location TABLE V Syndrome Decoding Syndrome Bits 6 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 5 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 4 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H 3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H 2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H 1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H 0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H unc 2-Bit 2-Bit unc 2-Bit unc unc 2-Bit (Note 2) 2-Bit unc DB31 2-Bit unc 2-Bit 2-Bit DB30 2-Bit unc DB29 2-Bit DB28 2-Bit 2-Bit DB27 DB26 2-Bit 2-Bit DB25 2-Bit DB24 unc 2-Bit Error 6 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 5 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Syndrome Bits 4 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H 3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H 2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H 1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H 0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H 2-Bit unc DB7 2-Bit DB6 2-Bit 2-Bit DB5 DB4 2-Bit 2-Bit DB3 2-Bit DB2 unc 2-Bit DB0 2-Bit 2-Bit unc 2-Bit DB1 unc 2-Bit 2-Bit unc unc 2-Bit unc 2-bit 2-bit CB6 Error CBX e Error in check bit X DBY e Error in data bit Y 2-Bit e Double-bit error unc e Uncorrectable multi-bit error Note 2-bit and unc condition will cause both ERR and MERR to be LOW Note 1 Syndrome bits for all LOWs MERR and ERR LOW for all LOWs only ERR LOW for DB30 error Note 2 Syndrome bits for all HIGHs 5 Functional Description (Continued) TABLE V Syndrome Decoding (Continued) Syndrome Bits 6 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H 5 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 4 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H 3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H 2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H 1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H 0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H 2-Bit unc unc 2-Bit unc 2-Bit 2-Bit unc unc 2-Bit 2-Bit DB15 2-Bit unc DB14 2-Bit unc 2-Bit 2-Bit DB13 2-Bit DB12 DB11 2-Bit 2-Bit DB10 DB9 2-Bit DB8 2-Bit 2-Bit CB5 Error 6 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H 5 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Syndrome Bits 4 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H 3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H 2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H 1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H 0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H unc 2-Bit 2-Bit DB23 2-Bit DB22 DB21 2-Bit 2-Bit DB20 DB19 2-Bit DB18 2-Bit 2-Bit CB4 2-Bit DB16 unc 2-Bit DB17 2-Bit 2-Bit CB3 unc (Note 1) 2-Bit 2-Bit CB2 2-Bit CB1 CB0 None Error CBX e Error in check bit X DBY e Error in data bit Y 2-Bit e Double-bit error unc e Uncorrectable multi-bit error Note 2-bit and unc condition will cause both ERR and MERR to be LOW Note 1 Syndrome bits for all LOWs MERR and ERR LOW for all LOWs only ERR LOW for DB30 error Note 2 Syndrome bits for all HIGHs 6 Functional Description (Continued) TABLE VI Read-Modify-Write Function Memory Cycle Read Read EDAC Function Read Flag Control S1 S0 H H L H BYTEn Input Latched Input Data Latched Output Data Word Input Modified BYTE0 Output Unchanged BYTE0 OEBn H H DB Output Latch LEDBO X L Check I O Input Latched Input Check Word High Z H H Output Syndrome Bits CB Control OECB H H H L Enabled Error Flags ERR MERR Enabled Enabled Latch Input Data Check Bits Latch Corrected Data Word into Output Latch Read H H Modify Write Modify Appropriate Byte or Bytes Generate New Check Word H H L Output Check Word L H H L L OEB0 controls DB0 –DB7 (BYTE0) OEB1 controls DB8 –DB15 (BYTE1) OEB2 controls DB16 –DB23 (BYTE2) OEB3 controls DB24 –DB31 (BYTE3) TABLE VII Diagnostic Function EDAC Function Read Flag Control S1 S0 H L Data I O Input Correct Data Word Input Diagnostic Data Word DB Byte Control OEBn H DB Output Latch LEDBO X Check I O Input Correct Check Bits Latched Input Check Bits Output Latched Check Bits High Z Latch Diagnostic Data Word into Input Latch Latched Input Diagnostic Data Word Output Diagnostic Data Word Output Corrected Diagnostic Data Word Output Syndrome Bits High Z Output Syndrome Bits High Z Output Corrected Diagnostic Data Word Output Syndrome Bits Output Syndrome Bits High Z CB Control OECB H Error Flags ERR MERR H Latch Input Check Word while Data Input Latch Remains Transparent Latch Diagnostic Data Word into Output Latch L H H L H Enabled L H Input Diagnostic Data Word H H L Enabled H L H L H L H H H H H Enabled Output Diagnostic Data Word Syndrome Bits H H L H Enabled H H L L Enabled Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag In this case the diagnostic data word will contain errors in two bit locations 7 Block Diagram TL F 9579 – 4 Timing Waveforms Read Flag and Correct Mode TL F 9579 – 5 8 Timing Waveforms (Continued) Read Correct and Modify Mode TL F 9579 – 6 Diagnostic Mode TL F 9579 – 7 9 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V b 0 5V to VCC b 0 5V to a 5 5V DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75 b0 6 54F 74F Typ Max Units V 08 V V VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 b1 2 Min IIN e b18 mA IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA (ERR MERR DBn CBn) b 3 mA (DBn CBn) b 1 mA (ERR MERR DBn CBn) b 3 mA (DBn CBn) b 1 mA (ERR MERR DBn CBn) b 3 mA (DBn CBn) 25 24 25 24 27 27 05 05 05 20 0 50 100 70 10 05 250 50 V Min VOL Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current V Min IOL e 20 mA (ERR MERR DBn CBn) IOL e 20 mA (ERR MERR) IOL e 24 mA (DBn CBn) VIN e 2 7V (S0 S1 OEBn OECB LEDBO) VIN e 7 0V (S0 S1 OEBn OECB LEDBO) VIN e 5 5V (CBn DBn) VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (S0 S1 OEBn OECB LEDBO) VI O e 2 7V (CBn DBn) VI O e 0 5V (CBn DBn) VI O e 2 7V (CBn DBn) VI O e 0 5V (CBn DBn) VOUT e 0V VOUT e 5 25V (CBn DBn) TA e 0 C –25 C TA e 25 C –70 C IIH IBVI IBVIT ICEX VID IOD IIL IIH a IOZH IIL a IOZL IOZH IOZL IOS IZZ ICC ICC mA mA mA mA V mA mA mA mA mA mA mA mA mA mA Max Max Max Max 00 00 Max Max Max Max Max Max 0 0V Max Max Output Leakage Current Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current b 60 70 b 650 70 b 650 b 150 500 340 325 10 AC Electrical Characteristics 74F Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay DB or CB to ERR Propagation Delay DB to ERR Propagation Delay DB or CB to MERR Propagation Delay DB to MERR Propagation Delay S0 and S1 LOW to DB Propagation Delay S1 to CB Propagation Delay S0 or S1 to ERR or MERR Propagation Delay DB to CB Propagation Delay LEDBO to DB Output Enable Time OEBn to DB Output Disable Time OEBn to DB Output Enable Time OECB to CB Output Disable Time OECB to CB 40 40 40 40 50 50 50 50 40 40 40 40 20 40 40 20 20 10 10 10 10 10 10 10 10 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 14 0 10 5 21 0 14 0 17 0 16 0 23 0 19 0 12 0 12 0 10 5 90 11 5 16 0 18 0 11 0 11 0 60 60 50 40 60 60 50 40 Max 27 0 18 0 27 0 18 0 27 0 27 0 27 0 27 0 16 0 16 0 14 0 14 0 13 0 23 0 23 0 13 0 13 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 54F TA VCC e Mil CL e 50 pF Min Max 74F TA VCC e Com CL e 50 pF Min 40 40 40 40 50 50 50 50 40 40 40 40 20 40 40 20 20 10 10 10 10 10 10 10 10 Max 31 0 20 0 31 0 20 0 31 0 31 0 31 0 31 0 20 0 20 0 15 0 15 0 14 0 25 0 25 0 14 0 14 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 ns ns ns ns ns ns ns ns ns ns ns ns ns Units 11 AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts ts(H) ts(H) ts(H) ts ts Setup Time HIGH or LOW DB CB before S0 HIGH (S1 HIGH) Setup Time HIGH S0 HIGH before LEDBO HIGH Setup Time HIGH LEDBO HIGH before S0 or S1 LOW Setup Time HIGH LEDBO HIGH before S1 HIGH Setup Time HIGH or LOW Diagnostic DB before S1 HIGH Setup Time HIGH or LOW Diagnostic CB before S1 LOW or S0 HIGH Setup Time HIGH or LOW Diagnostic DB before LEDBO HIGH (S1 LOW S0 HIGH) Hold Time LOW S0 LOW after S1 HIGH Hold Time HIGH or LOW DB and CB Hold after S0 HIGH Hold Time HIGH or LOW DB Hold after S1 HIGH Hold Time HIGH or LOW CB Hold after S1 LOW or S0 HIGH Hold Time HIGH or LOW Diagnostic DB after LEDBO HIGH (S1 LOW S0 HIGH) LEDBO Pulse Width Correction Time 30 12 0 0 0 0 30 Max 54F TA VCC e Mil Min Max 74F TA VCC e Com Min 30 14 0 0 0 0 30 Max ns ns ns ns ns ns Units ts 80 80 80 80 50 0 80 25 0 80 80 80 80 50 0 80 28 0 ns ns ns ns ns ns ns ns th(L) th th th th tw(L) tcorr Note These parameters are guaranteed by characterization or other tests performed Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial FAST 54F e Military FAST Device Type Package Code D e Ceramic DIP Q e 52-Lead Plastic Chip Carrier (PCC) V e 68-Lead Plastic Chip Carrier (PCC) Order DP8406QV DP8406V or DP8406D 632 D C QR Special Variations QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 12 Physical Dimensions inches (millimeters) 52-Lead Side-Brazed Ceramic Dual-In-Line Package (D) NS Package Number D52A 52-Lead Plastic Chip Carrier (Q) NS Package Number V52A 13 DP8406 (54F 74F632) 32-Bit Parallel Error Detection and Correction Circuit Physical Dimensions inches (millimeters) (Continued) 68-Lead Plastic Chip Carrier (V) NS Package Number V68A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications