74FTC534SCX

74FCT534 Octal D Flip-Flop with TRI-STATE Outputs April 1993 74FCT534 Octal D Flip-Flop with TRI-STATE Outputs General Description The ’FCT534 is a high-speed low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold performance FACT FCT features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance The ’FCT534 is the same as the ’FCT374 except that the outputs are inverted Features Y Y Y Y Y Y Y Y Y ICC and IOZ reduced to 40 0 mA and g 2 5 mA respectively NSC 54 74FCT534 is pin and functionally equivalent to IDT 54 74FCT534 Edge-triggered D-type inputs Buffered positive edge-triggered clock Input clamp diodes to limit bus reflections TTL CMOS input and output level compatible IOL e 48 mA CMOS power levels ESD immunity t 4 kV typ Logic Symbols Connection Diagram Pin Assignment for DIP and SOIC IEEE IEC TL F 10665–1 TL F 10665 – 2 TL F 10665 – 3 Pin Names D0 – D7 CP OE O0 – O7 Description Data Inputs Clock Pulse Input TRI-STATE Output Enable Input Complementary TRI-STATE Outputs TRI-STATE is a registered trademark of National Semiconductor Corporation FACTTM and GTOTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 10665 RRD-B30M105 Printed in U S A Functional Description The ’FCT534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complementary outputs The buffered clock and buffered Output Enable are common to all flip-flops The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition With the Output Enable (OE) LOW the contents of the eight flip-flops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops Logic Diagram TL F 10665 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays Function Table Inputs CP L L L X OE L L L H D H L X X Output O L H O0 Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition Z e High Impedance O0 e Value stored from previous clock cycle 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Terminal Voltage with Respect to GND (VTERM) 74FCT Temperature Under Bias (TBIAS) 74FCT Storage Temperature (TSTG) 74FCT DC Output Current (IOUT) Recommended Operating Conditions Supply Voltage (VCC) 74FCT Input Voltage Output Voltage Operating Temperature (TA) 74FCT Junction Temperature (TJ) PDIP 4 75V to 5 25V 0V to VCC 0V to VCC b 0 C to a 70 C b 0 5V to a 7 0V b 55 C to a 125 C b 55 C to a 125 C 140 C 120 mA Note All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from b 40 C to a 125 C Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur Exposure to absolute maximum rating conditions for extended periods may affect reliability The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables DC Characteristics for ’FCTA Family Devices Typical values are at VCC e 5 0V 25 C ambient and maximum loading For test conditions shown as Max use the value specified for the appropriate device type Com VCC e 5 0V g 5% TA e 0 C to a 70 C VHC e VCC b 0 2V Symbol VIH VIL IIH IIL IOZ Parameter Min Minimum High Level Input Voltage Maximum Low Level Input Voltage Input High Current Input Low Current Maximum TRI-STATE Current 20 08 50 50 b5 0 b5 0 74FCTA Typ Max Units Conditions V V mA mA VCC e Max VCC e Max VCC e Max mA VI e VCC VI e 2 7V (Note 2) VI e 0 5V (Note 2) VI e GND VO VO VO VO e e e e 25 25 b2 5 b2 5 b0 7 b 60 b 120 b1 2 VCC 2 7V (Note 2) 0 5V (Note 2) GND VIK IOS VOH Clamp Diode Voltage Short Circuit Current Minimum High Level Output Voltage V mA V VCC e Min IN e b18 mA VCC e Max (Note 1) VO e GND VCC e 3V VIN e 0 2V or VHC IOH e b32 mA VCC e Min VIN e VIH or VIL IOH e b300 mA IOH e b15 mA 28 VHC 24 30 VCC 43 GND GND 03 02 02 05 V VOL Maximum Low Level Output Voltage VCC e 3V VIN e 0 2V or VHC IOL e 300 mA VCC e Min VIN e VIH or VIL IOL e 300 mA IOL e 48 mA 3 DC Characteristics for ’FCT Family Devices (Continued) Typical values are at VCC e 5 0V 25 C ambient and maximum loading For test conditions shown as Max use the value specified for the appropriate device type Com VCC e 5 0V g 5% TA e 0 C to a 70 C VHC e VCC b 0 2V Symbol ICC Parameter Min Maximum Quiescent Supply Current Quiescent Supply Current TTL Inputs HIGH Dynamic Power Supply Current (Note 4) 74FCT Typ 10 Max 40 0 mA VCC e Max VIN t VHC VIN s 0 2V fI e 0 VCC e Max VIN e 3 4V (Note 3) VCC e Max Outputs Open OE e GND One Input Toggling 50% Duty Cycle VCC e Max Outputs Open fCP e 10 MHz OE e GND fI e 5 MHz One Bit Toggling 50% Duty Cycle mA (Note 5) VCC e Max Outputs Open OE e GND fCP e 10 MHz fI e 2 5 MHz Eight Bits Toggling 50% Duty Cycle mV VIN t VHC VIN s 0 2V VIN t VHC VIN s 0 2V Units Conditions DICC ICCD 05 20 mA 0 15 0 25 mA MHz IC Total Power Supply Current (Note 6) 15 40 VIN t VHC VIN s 0 2V 18 60 VIN e 3 4V VIN e GND 30 78 50 VH Input Hysteresis on Clock Only 16 8 VIN e 3 4V VIN e GND 200 Note 1 Maximum test duration not to exceed one second not more than one output shorted at one time Note 2 This parameter guaranteed but not tested Note 3 Per TTL driven input (VIN e 3 4V) all other inputs at VCC or GND Note 4 This parameter is not directly testable but is derived for use in Total Power Supply calculations Note 5 Values for these conditions are examples of the ICC formula These limits are guaranteed but not tested Note 6 IC e IQUIESCENT a IINPUTS a IDYNAMIC IC e ICC a DICC DHNT a ICCD (fCP 2 a fI NI) ICC e Quiescent Current DICC e Power Supply Current for a TTL High Input (VIN e 3 4V) DH e Duty Cycle for TTL inputs High NT e Number of Inputs at DH ICCD e Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP e Clock Frequency for Register Devices (Zero for Non-Register Devices) fI e Input Frequency NI e Numbers of Inputs at fI All currents are in milliamps and all frequencies are in megahertz 4 AC Electrical Characteristics 74FCT Symbol Parameter TA e a 25 C VCC e 5 0V Typ tPLH tPHL tPZH tPZL tPHZ tPLZ ts th tw Propagation Delay CP to On Output Enable Time Output Disable Time Set Up Time High or Low Dn to CP Hold Time High or Low Dn to CP CP Pulse Width High or Low 65 90 60 10 05 40 74FCT TA VCC e Com CL e 50 pF Min (Note 1) 15 15 15 20 15 70 Max 10 0 12 5 80 ns ns ns ns ns ns Units Note 1 Minimum limits guaranteed but not tested on propagation delays Capacitance TA e a 25 C Symbol CIN COUT Parameter fI e 1 0 MHz Typ 6 8 Max 10 12 Units pF pF Conditions VIN e 0V VOUT e 0V Input Capacitance Output Capacitance Note This parameter is measured at characterization but not tested COUT for 74FCT only Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74FCT Temperature Range Family 74FCT e Commercial TTL-Compatible Device Type Package Code P e Plastic DIP S e Small Outline (SOIC) 534 P C QR Special Variations X e Devices shipped in 13 reels QR e Commercial grade device with burn-in Temperature Range C e Commercial (0 C to a 70 C) 5 6 Physical Dimensions inches (millimeters) 20-Lead Small Outline Integrated Circuit (S) NS Package Number M20B 7 74FCT534 Octal D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications