74LS168

54LS168 Synchronous Bi-Directional BCD Decade Counter June 1989 54LS168 Synchronous Bi-Directional BCD Decade Counter General Description The 54LS168 is a fully synchronous 4-state up down counter featuring a preset capability for programmable operation carry lookahead for easy cascading and a U D input to control the direction of counting It counts in the BCD (8421) sequence and all state changes whether in counting or parallel loading are initiated by the LOW-to-HIGH transition of the clock Connection Diagram Dual-In-Line Package Logic Symbol TL F 10207 – 1 TL F 10207 – 2 Order Number 54LS168DMQB 54LS168FMQB or 54LS168LMQB See NS Package Number E20A J16A or W16A VCC e Pin 16 GND e Pin 8 Pin Names CEP CET CP P0–P3 PE UD Q0–Q3 TC Description Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output (Active LOW) C1995 National Semiconductor Corporation TL F 10207 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C 54LS b 65 C to a 150 C Storage Temperature Range Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Pn CEP or CET to CP Hold Time HIGH or LOW Pn CEP or CET to CP Setup Time HIGH or LOW PE to CP Hold Time HIGH or LOW PE to CP Setup Time HIGH or LOW U D to CP Hold Time HIGH or LOW U D to CP CP Pulse Width HIGH or LOW b 55 54LS168 Nom 5 Max 55 Units V V 07 b0 4 45 2 V mA mA C ns ns ns ns ns ns ns 4 125 15 15 5 5 20 20 0 0 25 25 0 0 20 20 2 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 10 0V VCC e Max VI e 2 7V Inputs CET IIL Low Level Input Current VCC e Max VI e 0 5V Data CP PE U D CEP CET IOS ICC Short Circuit Output Current Supply Current VCC e Max (Note 2) VCC e Max (Note 3) b0 5 b 30 b 60 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 04 01 20 40 b 400 b 400 b 800 b 100 V mA mA High Level Input Current mA mA mA 34 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 ICC is measured with all outputs open and all inputs grounded Switching Characteristics VCC e a 5 0V TA e a 25 C (See Section 1 for test waveforms and output load) 54LS168 Symbol Parameter Min fMax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U D to TC 25 20 20 30 30 15 20 25 25 CL e 15 pF Max MHz ns ns ns ns Units 3 Functional Description The ’LS168 uses edge-triggered D-type flip-flops and has no constraints on changing the control or data input signals in either state of the Clock The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter The parallel load operation takes precedence over the other operations as indicated in the Mode Select Table When PE is LOW the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the Clock In order for counting to occur both CEP and CET must be LOW and PE must be HIGH The U D input then determines the direction of counting The Terminal Count (TC) output is normally HIGH and goes LOW provided that CET is LOW when a counter reaches zero in the COUNT DOWN mode or reaches 9 in the COUNT UP mode The TC output state is not a function of the Count Enable Parallel (CEP) input level The TC output of the ’LS168 decade counter can also be LOW in the illegal states 11 13 and 15 which can occur when power is turned on or via parallel loading If an illegal state occurs the ’LS168 will return to the legitimate sequence within two counts Since the TC signal is derived by decoding the flipflop states there exists the possibility of decoding spikes on TC For this reason the use of TC as a clock signal is not recommended (see logic equation below) 1 Count Enable e CEP  CET  PE 2 Up TC e Q0  Q3  (U D)  CET 3 Down TC e Q0  Q1  Q2  Q3  (U D)  CET TL F 10207 – 3 ’LS168 Mode Select Table PE L H H H H CEP X L L H X CET X L L X H UD X H L X X Action on Rising Clock Edge Load (Pn x Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram Logic Diagram TL F 10207 – 4 4 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS168LMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS168DMQB NS Package Number J16A 5 54LS168 Synchronous Bi-Directional BCD Decade Counter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS168FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National 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