74LS373

DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops May 1992 DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components They are particularly attractive for implementing buffer registers I O ports bidirectional bus drivers and working registers (Continued) Features Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages ’LS373 Order Number DM54LS373J DM54LS373W DM74LS373N or DM74LS373WM See NS Package Number J20A M20B N20A or W20A TL F 6431 – 1 ’LS374 Order Number DM54LS374J DM54LS374W DM74LS374WM or DM74LS374N See NS Package Number J20A M20B N20A or W20A TL F 6431 – 2 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 6431 RRD-B30M105 Printed in U S A General Description (Continued) The eight latches of the DM54 74LS373 are transparent Dtype latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs When the enable is taken low the output will be latched at the level of the data that was set up The eight flip-flops of the DM54 74LS374 are edge-triggered D-type flip flops On the positive transition of the clock the Q outputs will be set to the logic states that were set up at the D inputs A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state In the high-impedance state the outputs neither load nor drive the bus lines significantly The output control does not affect the internal operation of the latches or flip-flops That is the old data can be retained or new data can be entered even while the outputs are off Function Tables DM54 74LS373 Output Control L L L H Enable G H H L X D H L X X Output H L Q0 Z Output Control L L L H DM54 74LS374 Clock D H L X X Output H L Q0 Z u u L X H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care e Transition from low-to-high level Z e High Impedance State Q0 e The level of the output before steady-state input conditions were established u Logic Diagrams DM54 74LS373 Transparent Latches DM54 74LS374 Positive-Edge-Triggered Flip-Flops TL F 6431–3 TL F 6431 – 4 2 Absolute Maximum Ratings (See Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage Storage Temperature Range 7V 7V Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation b 65 C to a 150 C Operating Free Air Temperature Range b 55 C to a 125 C DM54LS DM74LS 0 C to a 70 C Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL tW tSU tH TA Parameter Min Supply Voltage High Level Input Votage Low Level Input Voltage High Level Output Current Low Level Output Current Pulse Width (Note 2) Enable High Enable Low 2) 2) 15 15 5v 20v b 55 DM54LS373 Nom 5 Max 55 07 b1 DM74LS373 Min 4 75 2 08 b2 6 Units Max 5 25 V V V mA mA ns ns ns 70 C Nom 5 45 2 12 15 15 5v 20v 125 0 24 Data Setup Time (Notes 1 Data Hold Time (Notes 1 Free Air Operating Temperature Note 1 The symbol ( v) indicates the falling edge of the clock pulse is used for reference Note 2 TA e 25 C and VCC e 5V ’LS373 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 12 mA VCC e Min II IIH IIL IOZH Input Current Input Voltage Max VCC e Max VI e 7V VCC e Max VI e 2 7V VCC e Max VI e 0 4V VCC e Max VO e 2 7V VIH e Min VIL e Max VCC e Max VO e 0 4V VIH e Min VIL e Max VCC e Max (Note 2) VCC e Max OC e 4 5V Dn Enable e GND 3 DM54 DM74 b 20 b 50 Min Typ (Note 1) Max b1 5 Units V V DM54 DM74 DM54 DM74 DM74 24 24 34 31 0 25 0 35 04 05 04 01 20 b0 4 VOL Low Level Output Voltage V mA mA mA mA High Level Input Current Low Level Input Current Off-State Output Current with High Level Output Voltage Applied Off-State Output Current with Low Level Output Voltage Applied Short Circuit Output Current Supply Current 20 IOZL b 20 b 100 b 225 mA mA mA IOS ICC 24 40 ‘LS373 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) Data to Q Data to Q Enable to Q Enable to Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q RL e 667X CL e 45 pF Min Max 18 CL e 150 pF Min Max 26 ns Units Symbol Parameter tPLH Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Output Enable Time to High Level Output Output Enable Time to Low Level Output Output Disable Time from High Level Output (Note 3) Output Disable Time from Low Level Output (Note 3) tPHL 18 27 ns tPLH 30 38 ns tPHL 30 36 ns tPZH 28 36 ns tPZL 36 50 ns tPHZ 20 ns tPLZ 25 ns Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 CL e 5 pF Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL tW tSU tH TA Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Pulse Width (Note 4) Data Setup Time (Notes 1 Data Hold Time (Notes 1 Clock High Clock Low 4) 4) 15 15 20u 1u b 55 DM54LS374 Nom 5 Max 55 Min 4 75 2 07 b1 DM74LS374 Nom 5 Max 5 25 Units V V 08 b2 6 45 2 V mA mA ns ns ns 12 15 15 20u 1u 125 0 24 Free Air Operating Temperature 70 C Note 1 The symbol ( ) indicates the rising edge of the clock pulse is used for reference Note 4 TA e 25 C and VCC e 5V u 4 ’LS374 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 12 mA VCC e Min II IIH IIL IOZH Input Current Input Voltage Max VCC e Max VI e 7V VCC e Max VI e 2 7V VCC e Max VI e 0 4V VCC e Max VO e 2 7V VIH e Min VIL e Max DM54 DM74 24 24 34 31 V Min Typ (Note 1) Max b1 5 Units V VOL Low Level Output Voltage DM54 DM74 0 25 0 35 04 05 V DM74 0 25 04 01 20 b0 4 mA mA mA High Level Input Current Low Level Input Current Off-State Output Current with High Level Output Voltage Applied Off-State Output Current with Low Level Output Voltage Applied Short Circuit Output Current Supply Current 20 mA IOZL VCC e Max VO e 0 4V VIH e Min VIL e Max b 20 mA IOS ICC VCC e Max (Note 2) VCC e Max Dn e GND OC e 4 5V DM54 DM74 b 50 b 50 b 225 b 225 mA mA 27 45 ’LS374 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) RL e 667X Symbol Parameter CL e 45 pF Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Output Enable Time to High Level Output Output Enable Time to Low Level Output Output Disable Time from High Level Output (Note 3) Output Disable Time from Low Level Output (Note 3) 35 28 28 28 28 20 25 Max CL e 150 pF Min 20 32 38 44 44 Max MHz ns ns ns ns ns ns Units Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 CL e 5 pF 5 Physical Dimensions inches (millimeters) 20-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS373J or DM54LS374J NS Package Number J20A 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS373WM or DM74LS374WM NS Package Number M20B 20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS373N and DM74LS374N NS Package Number N20A 7 DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flat Package (W) Order Number DM54LS373W or DM54LS374W NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose 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