9328

9328 DM9328 Dual 8-Bit Shift Register June 1989 9328 DM9328 Dual 8-Bit Shift Register General Description The ’9328 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers The multifunctional capability of this device is provided by several features 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources 2) the clock of each register may be provided separately or together 3) both the true and complementary outputs are provided from each 8-bit register and both registers may be master cleared from a common input Connection Diagram Dual-In-Line Package Logic Symbol TL F 9793 – 1 Order Number 9328DMQB 9328FMQB or DM9328N See NS Package Number J16A N16E or W16A TL F 9793 – 2 VCC e Pin 16 GND e Pin 8 Pin Names S D0 D1 CP Description Data Select Input Data Inputs Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) Master Reset Input (Active LOW) Last Stage Output Complementary Output MR Q7 Q7 C1995 National Semiconductor Corporation TL F 9793 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C Military Commercial 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA ts (H) ts (L) th (H) th (L) tw (H) tw (L) tw (L) tw (L) trec Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Clock Pulse Width HIGH or LOW MR Pulse Width with CP HIGH MR Pulse Width with CP LOW Recovery Time MR to CP b 55 Military Nom 5 Max 55 Min 4 75 2 08 b0 4 Commercial Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA C ns ns ns ns ns ns 16 125 0 20 20 0 0 25 25 30 40 33 16 70 20 20 0 0 25 25 30 40 33 Electrical Characteristics Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Max Input Voltage Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VCC e Min IOL e Max VIH e Min VCC e Max VI e 5 5V VCC e Max VI e 2 4V MR Dn Inputs CP Inputs S Inputs CP (COM) Inputs IIL Low Level Input Current VCC e Max VI e 0 4V MR Dn Inputs CP Inputs S Inputs CP (COM) Input 24 34 02 04 1 40 60 80 120 b1 6 b2 4 b3 2 b4 8 Min Typ (Note 1) Max b1 5 Units V V V mA High Level Input Current mA mA 2 Electrical Characteristics Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) (Continued) Symbol IOS ICC Parameter Short Circuit Output Current Supply Current Conditions VCC e Max (Note 2) VCC e Max MIL COMM Min b 20 b 20 Typ (Note 1) Max b 70 b 70 Units mA mA 77 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time Switching Characteristics VCC e a 5 0V TA e a 25 C (See Section 1 for waveforms and load configurations) Symbol Parameter Min fmax tPLH tPHL tPHL Maximum Shift Right Frequency Propagation Delay CP to Q7 or Q7 Propagation Delay MR to Q7 20 20 35 50 CL e 15 pF RL e 400X Max MHz ns ns Units Functional Description The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7) The clocking of each register is controlled by the OR function of the separate and the common clock input Each register is composed of eight clocked RS master slave flip-flops and a number of gates The clock OR gate drives the eight clock inputs of the flip-flops in parallel When the two clock inputs (the separate and the common) to the OR gate are LOW the slave latches are steady but data can enter the master latches via the R and S input During the first LOW-to-HIGH transition of either or both simultaneously of the two clock inputs the data inputs (R and S) are inhibited so that a later change in input data will not affect the master then the now trapped information in the master is transferred to the slave When the transfer is complete both the master and the slave are steady as long as either or both clock inputs remain HIGH During the HIGH-to-LOW transition of the last remaining HIGH clock input the transfer path from master to slave is inhibited first leaving the slave steady in its present state The data inputs (R and S) are enabled so that new data can enter the master Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal Each 8-bit shift register has a 2-input multiplexer in front of the serial data input The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression Serial data in SD e SD0 a SD1 An asynchronous master reset is provided which when activated by a LOW logic level will clear all 16 stages independently of any other input signal Shift Select Table INPUTS S L L H H D0 L H X X D1 X X L H OUTPUT Q7 (tn a 8) L H L H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial n a 8 e indicates state after eight clock pulse 3 Logic Diagram TL F 9793 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 9328DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM9328N NS Package Number N16E 5 9328 DM9328 Dual 8-Bit Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 9328FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support 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