ADC0809

ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer November 1995 ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer General Description The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE ® outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet. (See AN-247 for more information.) Features n Easy interface to all microprocessors n Operates ratiometrically or with 5 VDC or analog span adjusted voltage reference n No zero or full-scale adjust required n 8-channel multiplexer with address logic n 0V to 5V input range with single 5V power supply n Outputs meet TTL voltage level specifications n Standard hermetic or molded 28-pin DIP package n 28-pin molded chip carrier package n ADC0808 equivalent to MM74C949 n ADC0809 equivalent to MM74C949-1 Key Specifications n n n n n Resolution: 8 Bits Total Unadjusted Error: ± 1⁄2 LSB and ± 1 LSB Single Supply: 5 VDC Low Power: 15 mW Conversion Time: 100 µs TRI-STATE ® is a registered trademark of National Semiconductor Corp. © 1997 National Semiconductor Corporation DS005672 www.national.com Block Diagram DS005672-1 See Ordering Information www.national.com 2 Absolute Maximum Ratings 2) (Notes 1, If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) (Note 3) 6.5V Voltage at Any Pin −0.3V to (VCC+0.3V) Except Control Inputs Voltage at Control Inputs −0.3V to +15V (START, OE, CLOCK, ALE, ADD A, ADD B, ADD C) Storage Temperature Range −65˚C to +150˚C 875 mW Package Dissipation at TA = 25˚C Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) ESD Susceptibility (Note 8) 300˚C 215˚C 220˚C 400V (Notes 1, 2) TMIN≤TA≤TMAX −55˚C≤TA≤+125˚C −40˚C≤TA≤+85˚C −40˚C ≤ TA ≤ +85˚C 4.5 VDC to 6.0 VDC Operating Conditions Temperature Range (Note 1) ADC0808CJ ADC0808CCJ, ADC0808CCN, ADC0809CCN ADC0808CCV, ADC0809CCV Range of VCC (Note 1) Electrical Characteristics Converter Specifications: VCC = 5 VDC = VREF+, VREF(−) = GND, TMIN≤TA≤TMAX and fCLK = 640 kHz unless otherwise stated. Symbol Parameter ADC0808 Total Unadjusted Error (Note 5) ADC0809 Total Unadjusted Error (Note 5) Input Resistance Analog Input Voltage Range VREF(+) Voltage, Top of Ladder Voltage, Center of Ladder 0˚C to 70˚C TMIN to TMAX From Ref(+) to Ref(−) (Note 4) V(+) or V(−) Measured at Ref(+) VCC/2-0.1 Measured at Ref(−) fc = 640 kHz, (Note 6) −0.1 −2 1.0 GND−0.10 VCC VCC/2 0 2.5 VCC+0.10 VCC+0.1 VCC/2+0.1 25˚C TMIN to TMAX Conditions Min Typ Max Units LSB LSB LSB LSB kΩ VDC V V ± 1⁄2 ± 3⁄4 ±1 ± 11⁄4 VREF(−) IIN Voltage, Bottom of Ladder Comparator Input Current V 2 µA ± 0.5 Electrical Characteristics Digital Levels and DC Specifications: ADC0808CJ 4.5V≤VCC≤5.5V, −55˚C≤TA≤+125˚C unless otherwise noted ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless otherwise noted Symbol ANALOG MULTIPLEXER IOFF(+) OFF Channel Leakage Current VCC = 5V, VIN = 5V, TA = 25˚C IOFF(−) OFF Channel Leakage Current TMIN to TMAX VCC = 5V, VIN = 0, TA = 25˚C TMIN to TMAX CONTROL INPUTS VIN(1) VIN(0) IIN(1) IIN(0) ICC Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current (The Control Inputs) Logical “0” Input Current (The Control Inputs) Supply Current fCLK = 640 kHz 0.3 3.0 mA VIN = 0 −1.0 µA VIN = 15V VCC−1.5 1.5 1.0 V V µA −200 −1.0 −10 10 200 1.0 nA µA nA µA Parameter Conditions Min Typ Max Units 3 www.national.com Electrical Characteristics (Continued) Digital Levels and DC Specifications: ADC0808CJ 4.5V≤VCC≤5.5V, −55˚C≤TA≤+125˚C unless otherwise noted ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless otherwise noted Symbol VOUT(1) VOUT(0) VOUT(0) IOUT Parameter Logical “1” Output Voltage Logical “0” Output Voltage Logical “0” Output Voltage EOC TRI-STATE Output Current Conditions IO = −360 µA IO = 1.6 mA IO = 1.2 mA VO = 5V VO = 0 −3 Min VCC−0.4 0.45 0.45 3 Typ Max Units V V V µA µA DATA OUTPUTS AND EOC (INTERRUPT) Electrical Characteristics Timing Specifications VCC = VREF(+) = 5V, VREF(−) = GND, tr = tf = 20 ns and TA = 25˚C unless otherwise noted. Symbol tWS tWALE ts tH tD tH1, tH0 t1H, t0H tc fc tEOC CIN COUT Parameter Minimum Start Pulse Width Minimum ALE Pulse Width Minimum Address Set-Up Time Minimum Address Hold Time Analog MUX Delay Time From ALE OE Control to Q Logic State OE Control to Hi-Z Conversion Time Clock Frequency EOC Delay Time Input Capacitance TRI-STATE Output Capacitance Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless othewise specified. Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC. Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900 VDC over temperature variations, initial tolerance and loading. Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 2. None of these A/Ds requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be adjusted to achieve this. See Figure 13. Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little temperature dependence (Figure *NO TGT: fig NS0592*). See paragraph 4.0. Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC. Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Conditions (Figure 5) (Figure 5) (Figure 5) (Figure 5) RS = 0Ω (Figure 5) CL = 50 pF, RL = 10k (Figure 8) CL = 10 pF, RL = 10k (Figure 8) fc = 640 kHz, (Figure 5) (Note 7) (Figure 5) At Control Inputs At TRI-STATE Outputs MIn Typ 100 100 25 25 1 125 125 Max 200 200 50 50 2.5 250 250 116 1280 8+2 µS Units ns ns ns ns µS ns ns µS kHz Clock Periods pF pF 90 10 0 100 640 10 10 15 15 www.national.com 4 Functional Description Multiplexer. The device contains an 8-channel single-ended analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal. TABLE 1. SELECTED ANALOG CHANNEL IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 ADDRESS LINE C L L L L H H H H B L L H H L L H H A L H L H L H L H The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +1⁄2 LSB and succeeding output transitions occur every 1 LSB later up to full-scale. The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit converter. In the ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network. The A/D converter’s successive approximation register (SAR) is reset on the positive edge of the start conversion (SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion. The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements. The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed throught a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors. CONVERTER CHARACTERISTICS The Converter The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter’s digital outputs are positive true. The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally, the 256R network does not cause load variations on the reference voltage. Figure 4 shows a typical error curve for the ADC0808 as measured using the procedures outlined in AN-179. 5 www.national.com Functional Description (Continued) DS005672-2 FIGURE 1. Resistor Ladder and Switch Tree DS005672-13 DS005672-14 FIGURE 2. 3-Bit A/D Transfer Curve FIGURE 3. 3-Bit A/D Absolute Accuracy Curve DS005672-15 FIGURE 4. Typical Error Curve www.national.com 6 Connection Diagrams Dual-In-Line Package Molded Chip Carrier Package DS005672-11 Order Number ADC0808CCN, ADC0809CCN, ADC0808CCJ or ADC0808CJ See NS Package J28A or N28A DS005672-12 Order Number ADC0808CCV or ADC0809CCV See NS Package V28A Timing Diagram DS005672-4 FIGURE 5. 7 www.national.com Typical Performance Characteristics DS005672-16 DS005672-17 FIGURE 6. Comparator IIN vs VIN (VCC = VREF = 5V) FIGURE 7. Multiplexer RON vs VIN (VCC = VREF = 5V) TRI-STATE Test Circuits and Timing Diagrams t1H, tH1 t1H, CL = 10 pF tH1, CL = 50 pF DS005672-18 DS005672-19 DS005672-20 t0H, tH0 t0H, CL = 10 pF tH0, CL = 50 pF DS005672-23 DS005672-22 DS005672-21 FIGURE 8. Applications Information OPERATION 1.0 RATIOMETRIC CONVERSION The ADC0808, ADC0809 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to the ADC0808 is expressed by the equation VZ = Zero voltage DX = Data point being measured DMAX = Maximum data limit DMIN = Minimum data limit A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source of error and cost for many applications. A major advantage of the ADC0808, ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly across the supply and their outputs connected directly into the multiplexer inputs, (Figure 9). Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc., are (1) VIN = Input voltage into the ADC0808 Vfs = Full-scale voltage www.national.com 8 Applications Information (Continued) suitable for measuring proportional relationships; however, many types of measurements must be referred to an absolute standard such as voltage or current. This means a system reference must be used which relates the full-scale voltage to the standard volt. For example, if VCC = VREF = 5.12V, then the full-scale range is divided into 256 standard steps. The smallest standard step is 1 LSB which is then 20 mV. 2.0 RESISTOR LADDER LIMITATIONS The voltages from the resistor ladder are compared to the selected into 8 times in a conversion. These voltages are coupled to the comparator via an analog switch tree which is referenced to the supply. The voltages at the top, center and bottom of the ladder must be controlled to maintain proper operation. The top of the ladder, Ref(+), should not be more positive than the supply, and the bottom of the ladder, Ref(−), should not be more negative than ground. The center of the ladder voltage must also be near the center of the supply because the analog switch tree changes from N-channel switches to P-channel switches. These limitations are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems. Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must be trimmed to match the reference voltage. For instance, if a 5.12V is used, the supply should be adjusted to the same voltage within 0.1V. DS005672-7 FIGURE 9. Ratiometric Conversion System The ADC0808 needs less than a milliamp of supply current so developing the supply from the reference is readily accomplished. In Figure 11 a ground referenced system is shown which generates the supply from the reference. The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the desired bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current as seen in Figure 12. The LM301 is overcompensated to insure stability when loaded by the 10 µF output capacitor. The top and bottom ladder voltages cannot exceed VCC and ground, respectively, but they can be symmetrically less than VCC and greater than ground. The center of the ladder voltage should always be near the center of the supply. The sensitivity of the converter can be increased, (i.e., size of the LSB steps decreased) by using a symmetrical reference system. In Figure 13, a 2.5V reference is symmetrically centered about VCC/2 since the same current flows in identical resistors. This system with a 2.5V reference allows the LSB bit to be half the size of a 5V reference system. 9 www.national.com Applications Information (Continued) DS005672-24 FIGURE 10. Ground Referenced Conversion System Using Trimmed Supply DS005672-25 FIGURE 11. Ground Referenced Conversion System with Reference Generating VCC Supply www.national.com 10 Applications Information (Continued) DS005672-26 FIGURE 12. Typical Reference and Supply Circuit DS005672-27 RA = RB *Ratiometric transducers FIGURE 13. Symmetrically Centered Reference 3.0 CONVERTER EQUATIONS The transition between adjacent codes N and N+1 is given by: (4) where: VIN = Voltage at comparator input VREF(+) = Voltage at Ref(+) VREF(−) = Voltage at Ref(−) VTUE = Total unadjusted error voltage (typically VREF(+)÷512) (2) The center of an output code N is given by: (3) The output code N for an arbitrary input are the integers within the range: 11 www.national.com Applications Information 4.0 ANALOG COMPARATOR INPUTS (Continued) The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances. These are connected alternately to the output of the resistor ladder/ switch tree network and to the comparator input as part of the operation of the chopper stabilized comparator. The average value of the comparator input current varies directly with clock frequency and with VIN as shown in Figure 6. If no filter capacitors are used at the analog inputs and the signal source impedances are low, the comparator input current should not introduce converter errors, as the transient created by the capacitance discharge will die out before the comparator output is strobed. If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average out the dynamic comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted conventionally. Typical Application DS005672-10 *Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor MICROPROCESSOR INTERFACE TABLE PROCESSOR 8080 8085 Z-80 SC/MP 6800 RD RD NRDS VMA • φ2 • R/W READ MEMR WRITE MEMW WR WR NWDS VMA • φ • R/W INTERRUPT (COMMENT) INTR (Thru RST Circuit) INTR (Thru RST Circuit) INT (Thru RST Circuit, Mode 0) SA (Thru Sense A) IRQA or IRQB (Thru PIA) Ordering Information TEMPERATURE RANGE Error −40˚C to +85˚C ADC0808CCN ADC0809CCN N28A Molded DIP ADC0808CCV ADC0809CCV V28A Molded Chip Carrier J28A Ceramic DIP J28A Ceramic DIP ADC0808CCJ −55˚C to +125˚C ADC0808CJ ± 1⁄2 LSB Unadjusted ± 1 LSB Unadjusted Package Outline www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number ADC0808CCJ or ADC0808CJ NS Package Number J28A Molded Dual-In-Line Package (N) Order Number ADC0808CCN or ADC0809CCN NS Package Number N28B 13 www.national.com ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Chip Carrier (V) Order Number ADC0808CCV or ADC0809CCV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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