ADC0811CCV

ADC0811 8-Bit Serial I O A D Converter With 11-Channel Multiplexer December 1994 ADC0811 8-Bit Serial I O A D Converter With 11-Channel Multiplexer General Description The ADC0811 is an 8-Bit successive approximation A D converter with simultaneous serial I O The serial input controls an analog multiplexer which selects from 11 input channels or an internal half scale test voltage An input sample-and-hold is implemented by a capacitive reference ladder and sampled data comparator This allows the input signal to vary during the conversion cycle Separate serial I O and conversion clock inputs are provided to facilitate the interface to various microprocessors Y Y Y Y Y Y Ratiometric or absolute voltage referencing No zero or full-scale adjust required Internally addressable test voltage 0V to 5V input range with single 5V power supply TTL MOS input output compatible 0 3 standard width 20-pin dip or 20-pin molded chip carrier Key Specifications Y Y Y Y Y Features Y Y Y Separate asynchronous converter clock and serial data I O clock 11-Channel multiplexer with 4-Bit serial address logic Built-in sample and hold function Resolution Total unadjusted error Single supply Low Power Conversion Time g 8-Bits LSB and g 1LSB 5VDC 15 mW 32 mS Connection Diagrams Dual-In-Line Package Functional Diagram Top View TL H 5587–1 Molded Chip Carrier (PCC) Package TL H 5587 – 3 Top View TL H 5587–2 Order Number ADC0811J N V See NS Packages J20A N20A V20A Use Ordering Information C1995 National Semiconductor Corporation TL H 5587 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Lead Temp (Soldering 10 seconds) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) ESD Susceptibility (Note 11) 260 C 300 C 215 C 220 C 2000V 2) 4 5 VDC to 6 0 VDC TMINsTAsTMAX 0 CsTAs70 C b 40 C s TA s 85 C b 40 C s TA s 85 C If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) 6 5V Voltage b 0 3V to VCC a 0 3V Inputs and Outputs g 5mA Input Current Per Pin (Note 3) g 20mA Total Package Input Current (Note 3) b 65 C to a 150 C Storage Temperature Package Dissipation at TA e 25 C 875 mW Operating Ratings (Notes 1 Supply Voltage (VCC) Temperature Range ADC0811BCN ADC0811CCN ADC0811BCV ADC0811CCJ ADC0811CCV Electrical Characteristics The following specifications apply for VCC e 4 75V to 5 25V VREF e a 4 6V to (VCC a 0 1V) w2 CLK e 2 097 MHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C ADC0811CCJ Parameter Conditions Typical (Note 6) Tested Limit (Note 7) ADC0811BCN ADC0811BCV ADC0811CCN ADC0811CCV Design Typical Limit (Note 6) (Note 8) Tested Limit (Note 7) Design Limit (Note 8) Units CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total VREF e 5 00 VDC Unadjusted Error (Note 4) ADC0811BCN ADC0811BCV ADC0811CCN ADC0811CCV ADC0811CCJ Minimum Reference Input Resistance Maximum Reference Input Resistance Maximum Analog Input Range Minimum Analog Input Range On Channel Leakage Current ADC0811BCJ CCJ BCN CCN BCV CCV ADC0811CJ BJ ADC0811BCJ CCJ BCN CCN BCV CCV ADC0811BJ CJ Off Channel Leakage Current ADC0811BCJ CCJ BCN CCN BCV CCV ADC0811CJ BJ ADC0811BCJ CCJ BCN CCN BCV CCV ADC0811BJ CJ Minimum VTEST Internal Test Voltage Maximum VTEST Internal Test Voltage On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) VREF e VCC CH 11 Selected VREF e VCC CH 11 Selected (Note 5) 8 8 11 VCC a 0 05 GNDb0 05 1000 1000 b 1000 b 1000 b 1000 b 1000 b 400 b 400 b 1000 g g1 g1 g g1 LSB LSB LSB kX kX V V nA nA nA nA 5 8 8 11 5 11 VCC a 0 05 VCC a 0 05 GNDb0 05 GNDb0 05 400 1000 1000 nA nA 1000 1000 125 130 400 1000 nA nA 125 130 125 130 (Note 10) Counts (Note 10) Counts 2 Electrical Characteristics The following specifications apply for VCC e 4 75V to 5 25V VREF e a 4 6V to (VCC a 0 1V) w2 CLK e 2 097 MHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C (Continued) ADC0811CCJ Parameter Conditions Typical (Note 6) Tested Limit (Note 7) 20 08 0 005 b 0 005 ADC0811BCN ADC0811BCV ADC0811CCN ADC0811CCV Design Limit (Note 8) Typical (Note 6) Tested Limit (Note 7) 20 08 0 005 b 0 005 Design Limit (Note 8) 20 08 25 b2 5 Units DIGITAL AND DC CHARACTERISTICS VIN(1) Logical ‘‘1’’ Input Voltage (Min) VIN(0) Logical ‘‘0’’ Input Voltage (Max) IIN(1) Logical ‘‘1’’ Input Current (Max) IIN(0) Logical ‘‘0’’ Input Current (Max) VOUT(1) Logical ‘‘1’’ Output Voltage (Min) VOUT(0) Logical ‘‘0’’ Output Voltage (Max) IOUT TRI-STATE Output Current (Max) ISOURCE Output Source Current (Min) ISINK Output Sink Current (Min) ICC Supply Current (Max) IREF (Max) AC CHARACTERISTICS Parameter w CLK w Clock Frequency SCLK Serial Data Clock Frequency TC Conversion Process Time MIN MAX MIN MAX Not Including MUX Addressing and MAX Analog Input Sampling Times MIN MAX MIN Conditions Tested Typical Limit (Note 6) (Note 7) Design Limit (Note 8) 10 21 50 525 48 64 1 3 4 w2CLK a 0 MIN MAX tHDI Minimum DI Hold Time from SCLK Rising Edge tHDO Minimum DO Hold Time from SCLK Falling Edge RL e CL e k pF tset-up a 8 SCLK t CS(min) a 48 w2CLK 0 10 1 2 SCLK sec ns sec sec ns ns w cycles w cycles KHz Units VCC e 5 25V VCC e 4 75V VIN e 5 0V VIN e 0V VCC e 4 75V IOUT eb360 mA IOUT eb10 mA VCC e 5 25V IOUT e 1 6 mA VOUT e 0V VOUT e 5V VOUT e 0V VOUT e VCC CS e 1 VREF Open VREF e 5V b 0 01 V V mA mA 25 b2 5 25 25 24 45 04 b3 b 0 01 24 45 04 b3 24 45 04 b3 V V V mA mA mA mA mA mA 0 01 b 12 3 b6 5 0 01 b 14 3 b6 5 3 b6 5 18 1 07 80 25 1 16 1 07 80 25 1 80 25 1 MHz tACC Access Time Delay From CS Falling Edge to DO Data Valid tSET UP Minimum Set up Time of CS Falling Edge to SCLK Rising Edge tHCS CS Hold Time After the Falling Edge of SCLK t CS Total CS Low Time 3 Electrical Characteristics The following specifications apply for VCC e 4 75V to 5 25V VREF e a 4 6V to (VCC a 0 1V) w2 CLK e 2 097 MHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C (Continued) Parameter AC CHARACTERISTICS (Continued) tSDI Minimum DI Set-up Time to SCLK Rising Edge tDDO Maximum Delay From SCLK Falling Edge to DO Data Valid tTRI Maximum DO Hold Time (CS Rising edge to DO TRI-STATE) tCA Analog Sampling Time tRDO Maximum DO Rise Time tFDO Maximum DO Fall Time CIN Maximum Input Capacitance RL e 30k CL e 100 pF RL e 3k CL e 100 pF After Address Is Latched CS e Low RL e 30 kX CL e 100 pf RL e 30 kX CL e 100 pf All Others ‘‘TRI-STATE’’ to ‘‘HIGH’’ State ‘‘LOW’’ to ‘‘HIGH’’ State ‘‘TRI-STATE’’ to ‘‘LOW’’ State ‘‘HIGH’’ to ‘‘LOW’’ State 75 150 75 150 11 5 150 300 150 300 200 180 400 400 400 ns ns Conditions Typical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units 90 150 150 ns 4 SCLK a 1 ms 150 300 150 300 55 15 sec ns ns Analog Inputs ANO–AN10 and VREF pF Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to ground Note 3 Under over voltage conditions (VIN k 0V and VIN l VCC) the maximum input current at any one pin is g 5 mA If the voltage at more than one pin exceeds VCC a 3V the total package current must be limited to 20 mA For example the maximum number of pins that can be over driven at the maximum current level of g 5 mA is four Note 4 Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors Note 5 Two on-chip diodes are tied to each analog input which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading Note 6 Typicals are at 25 C and represent most likely parametric norm Note 7 Guaranteed and 100% production tested under worst case condition Note 8 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels Note 9 Channel leakage current is measured after the channel selection Note 10 1 count e VREF 256 Note 11 Human body model 100 pF discharged through a 1 5 kX resistor Test Circuits Leakage Current D0 Except ‘‘TRI-STATE’’ TL H 5587 – 6 TL H 5587–17 4 Test Circuits (Continued) tTRI ‘‘TRI-STATE’’ TL H 5587 – 22 Typical Performance Characteristics Unadjusted Offset Error vs VREF Voltage Linearity Error vs VREF Voltage Output Current vs Temperature Linearity vs Temperature Linearity vs w2 Clock Frequency Power Supply Current vs Temperature Power Supply Current vs w2 Clock Frequency Resistive Ladder Reference Current vs Temperature TL H 5587 – 16 5 Timing Diagrams D0 ‘‘TRI-STATE’’ Rise Fall Times D0 Low to High State D0 High to Low State TL H 5587 – 14 TL H 5587 – 15 TL H 5587–13 Timing with a continuous SCLK TL H 5587 – 11 Strobing CS High and Low will abort the present conversion and initiate a new serial I O exchange Timing with a gated SCLK and CS Continuously Low TL H 5587 – 9 Using CS To TRI-STATE D0 TL H 5587 – 10 Note Strobing CS Low during this time interval will abort the conversion in process 6 Timing Diagrams (Continued) CS High During Conversion TL H 5587 – 4 CS Low During Conversion TL H 5587 – 5 Note DO and DI lines share the 8-bit I O shift register(see Functional Block Diagram) Since the MUX address bits are shifted in on SCLK rising edges while SCLK falling edges shift out conversion data on DO the eighth falling edge of SCLK will shift out the MSB MUX address bit (A7) on DO Thus if addressing channels CH8–CH10 a high DO will occur momentarily (one w2 clock period) until the 8-bit I O shift register is cleared by the internal EOC signal Channel Addressing Table TABLE I ADC 0811 Channel Addressing MUX ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ANALOG CHANNEL SELECTED CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 VTEST LOGIC TEST MODE Analog channel inputs CH0 thru CH3 are logic outputs 7 8 TL H 5587 – 8 Functional Block Diagram Functional Description 1 0 DIGITAL INTERFACE The ADC0811 uses five input output pins to implement the serial interface Taking chip select (CS) low enables the I O data lines (DO and DI) and the serial clock input (SCLK) The result of the last conversion is transmitted by the A D on the DO line while simultaneously the DI line receives the address data that selects the mux channel for the next conversion The mux address is shifted in on the rising edge of SCLK and the conversion data is shifted out on the falling edge It takes eight SCLK cycles to complete the serial I O A second clock (w2) controls the SAR during the conversion process and must be continuously enabled 1 1 CONTINUOUS SCLK With a continuous SCLK input CS must be used to synchronize the serial data exchange (see Figure 1 ) The ADC0811 recognizes a valid CS one to three w2 clock periods after the actual falling edge of CS This is implemented to ensure noise immunity of the CS signal Any spikes on CS less than one w2 clock period will be ignored CS must remain low during the complete I O exchange which takes eight SCLK cycles Although CS is not immediately acknowledged for the purpose of starting a new conversion the falling edge of CS immediately enables DO to output the MSB (D7) of the previous conversion The first SCLK rising edge will be acknowledged after a setup time (tset-up) has elapsed from the falling edge of CS This and the following seven SCLK rising edges will shift in the channel address for the analog multiplexer Since there are 12 channels only four address bits are utilized The first four SCLK cycles clock in the mux address during the next four SCLK cycles the analog input is selected and sampled During this mux address sample cycle data from the last conversion is also clocked out on DO Since D7 was clocked out on the falling edge of CS only data bits D6 – D0 remain to be received The following seven falling edges of SCLK shift out this data on DO The 8th SCLK falling edge initiates the beginning of the A D’s actual conversion process which takes between 48 to 64 w2 cycles (TC) During this time CS can go high to TRI-STATE DO and disable the SCLK input or it can remain low If CS is held low a new I O exchange will not start until the conversion sequence has been completed however once the conversion ends serial I O will immediately begin Since there is an ambiguity in the conversion time (TC) synchronizing the data exchange is impossible Therefore CS should go high before the 48th w2 clock has elasped and return low after the 64th w2 to synchronize serial communication A conversion or I O operation can be aborted at any time by strobing CS If CS is high or low less than one w2 clock it will be ignored by the A D If the CS is strobed high or low between 1 to 3 w2 clocks the A D may or may not respond Therefore CS must be strobed high or low greater than 3 w2 clocks to ensure recognition If a conversion or I O exchange is aborted while in process the consequent data output will be erroneous until a complete conversion sequence has been implemented 1 2 DISCONTINUOUS SCLK Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its 8th falling edge (see Figure 2 ) SCLK must remain low for TL H 5587 – 18 FIGURE 1 TL H 5587 – 19 FIGURE 2 9 Functional Description (Continued) at least 64 w2 clocks to insure that the A D has completed its conversion If SCLK is enabled sooner synchronizing to the data output on DO is not possible since an end of conversion signal from the A D is not available and the actual conversion time is not known With CS low during the conversion time (64 w2 max) DO will go low after the eighth falling edge of SCLK and remain low until the conversion is completed Once the conversion is through DO will transmit the MSB The rest of the data will be shifted out once SCLK is enabled as discussed previously If CS goes high during the conversion sequence DO is tristated and the result is not affected so long as CS remains high until the end of the conversion 1 2 MULTIPLEXER ADDRESSING The four bit mux address is shifted MSB first into DI Input data corresponds to the channel selected as shown in table 1 Care should be taken not to send an address greater than or equal to twelve (11XX) as this puts the A D in a digital testing mode In this mode the analog inputs CH0 thru CH3 become digital outputs for our use in production testing 2 0 ANALOG INPUT 2 1 THE INPUT SAMPLE AND HOLD The ADC0811’s sample hold capacitor is implemented in its capacitive ladder structure After the channel address is received the ladder is switched to sample the proper analog input This sampling mode is maintained for 1 msec after the eighth SCLK falling edge The hold mode is initiated with the start of the conversion process An acquisition window of 4tSCLK a 1 msec is therefore available to allow the ladder capacitance to settle to the analog input voltage Any change in the analog voltage before or after the acquisition window will not effect the A D conversion result In the most simple case the ladder’s acquisition time is determined by the Ron (3K) of the multiplexer switches and the total ladder capacitance (90pf) These values yield an acquisition time of about 2 msec for a full scale reading Therefore the analog input must be stable for at least 2 msec before and 1 msec after the eighth SCLK falling edge to ensure a proper conversion External input source resistance and capacitance will lengthen the acquisition time and should be accounted for Other conventional sample and hold error specifications are included in the error and timing specs of the A D The hold step and gain error sample hold specs are taken into account in the ADC0811’s total unadjusted error while the hold settling time is included in the A D’s max conversion time of 64 w2 clock periods The hold droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the reading of data However once the data is read it is lost and another conversion is started Typical Applications ADC0811-INS8048 INTERFACE TL H 5587 – 21 10 ADC0811 FUNCTIONAL CIRCUIT TL H 5587 – 20 Ordering Information Temperature Range Total Unadjusted Error g 0 C to 70 C LSB ADC0811BCN ADC0811CCN N20A b 40 C to a 85 C ADC0811BCV ADC0811CCJ ADC0811CCV J20A V20A g 1 LSB Package Outline 11 12 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number ADC0811CCJ NS Package J20A Molded Dual-In-Line Package (N) Order Number ADC0811BCN CCN NS Package N20A 13 ADC0811 8-Bit Serial I O A D Converter With 11-Channel Multiplexer Physical Dimensions inches (millimeters) (Continued) Molded Chip Carrier (V) Order Number ADC0811BCV CCV NS Package V20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 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