ADC08D1000

ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter December 2005 ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter General Description The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-andhold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40˚C ≤ TA ≤ +85˚C) temperature range. Features n n n n n n n n n Internal Sample-and-Hold Single +1.9V ± 0.1V Operation Choice of SDR or DDR output clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications n n n n n n Resolution Max Conversion Rate Bit Error Rate ENOB @ 500 MHz Input DNL Power Consumption — Operating — Power Down Mode 8 Bits 1 GSPS (min) 10-18 (typ) 7.4 Bits (typ) ± 0.15 LSB (typ) 1.6 W (typ) 3.5 mW (typ) Applications n n n n n Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Block Diagram 20097453 © 2005 National Semiconductor Corporation DS200974 www.national.com ADC08D1000 Ordering Information Industrial Temperature Range (-40˚C < TA < +85˚C) ADC08D1000CIYB ADC08D1000EVAL NS Package 128-Pin Exposed Pad LQFP Evaluation Board Pin Configuration 20097401 * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com 2 ADC08D1000 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data.See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See Section 1.1.5.2). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See Section 1.5 for detailed description. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.4.2 for an overview of self-calibration and Section 2.4.2.2 for a description of on-command calibration. Full Scale Range Select and Extended Control Enable. In non-extended control mode, a logic low on this pin sets the full-scale differential input range to 650 mVP-P. A logic high on this pin sets the full-scale differential input range to 870 mVP-P. See Section 1.1.4. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See Section 1.2 for information on the extended control mode. Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See Section 1.1.1). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See Section 1.1.5.1. 3 OutV / SCLK 4 OutEdge / DDR / SDATA 15 DCLK_RST 26 29 PD PDQ 30 CAL 14 FSR/ECE 127 CalDly / DES / SCS 3 www.national.com ADC08D1000 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit (Continued) Description 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.3 for an overview of the clock inputs. 11 10 . 22 23 VINI+ VINI− . VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when the FSR pin is high. 7 VCMO Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100µA. See Section 2.2. Bandgap output voltage capable of 100 µA source/sink. Calibration Running indication. This pin is at a logic high when calibration is running. 31 126 VBG CalRun 32 REXT External bias resistor connection. Nominal value is 3.3k-Ohms ( ± 0.1%) to ground. See Section 1.1.1. 34 35 Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See Section 2.6.2. www.national.com 4 ADC08D1000 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 105 106 107 111 112 113 114 115 116 117 118 122 123 124 125 / / / / / / / / / / / / / / / / 57 56 55 54 50 49 48 47 46 45 44 43 39 38 37 36 Symbol DI7− DI7+ DI6− DI6+ DI5− DI5+ DI4− DI4+ DI3− DI3+ DI2− DI2+ DI1− DI1+ DI0− DI0+ DId7− DId7+ DId6− DId6+ DId5− DId5+ DId4− DId4+ DId3− DId3+ DId2− DId2+ DId1− DId1+ DId0− DId0+ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / DQ7− DQ7+ DQ6− DQ6+ DQ5− DQ5+ DQ4− DQ4+ DQ3− DQ3+ DQ2− DQ2+ DQ1− DQ1+ DQ0− DQ0+ DQd7− DQd7+ DQd6− DQd6+ DQd5− DQd5+ DQd4− DQd4+ DQd3− DQd3+ DQd2− DQd2+ DQd1− DQd1+ DQd0− DQd0+ Equivalent Circuit (Continued) Description I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. 79 80 OR+ OR- Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ± 325 mV or ± 435 mV as defined by the FSR pin). 82 81 DCLK+ DCLK- Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. DCLK outputs are not active during a calibration cycle. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 VA Analog power supply pins. Bypass these pins to ground. 5 www.national.com ADC08D1000 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. 40, 51 ,62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27, 41 42, 53, 64, 74, 87, 97, 108, 119 52, 63, 98, 109, 120 Symbol Equivalent Circuit (Continued) Description Output Driver power supply pins. Bypass these pins to DR GND. VDR GND Ground return for VA. DR GND Ground return for VDR. NC No Connection. Make no connection to these pins. www.national.com 6 ADC08D1000 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Voltage on Any Input Pin Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA ≤ 85˚C ESD Susceptibility (Note 4) Human Body Model Machine Model Soldering Temperature, Infrared, 10 seconds, (Note 5), (Applies to standard plated package only) Storage Temperature 2.2V −0.15V to (VA +0.15V) 0V to 100 mV Operating Ratings (Notes 1, 2) Ambient Temperature Range Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude −40˚C ≤ TA ≤ +85˚C +1.8V to +2.0V +1.8V to VA VCMO ± 50mV 200mV to VA 0V 0V to VA 0.4VP-P to 2.0VP-P ± 25 mA ± 50 mA 2.0 W 2500V 250V Package Thermal Resistance Package θJA θJC(Top of Package) θJ-PAD (Thermal Pad) 235˚C −65˚C to +150˚C 128-Lead Exposed Pad LQFP 25˚C / W 10˚C / W 2.8˚C / W Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ± 0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity (Best fit) Differential Non-Linearity Resolution with No Missing Codes VOFF VOFF_ADJ PFSE NFSE FS_ADJ FPBW B.E.R. Offset Error Input Offset Adjustment Range Positive Full-Scale Error (Note 9) Negative Full-Scale Error (Note 9) Full-Scale Adjustment Range Full Power Bandwidth Bit Error Rate Gain Flatness d.c. to 500 MHz d.c. to 1 GHz fIN = 100 MHz, VIN = FSR − 0.5 dB ENOB Effective Number of Bits fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB Extended Control Mode Normal Mode (non DES) Extended Control Mode -0.45 DC Coupled, 1MHz Sine Wave Overanged DC Coupled, 1MHz Sine Wave Overanged ± 0.3 ± 0.15 ± 0.9 ± 0.6 8 −1.5 0.5 LSB (max) LSB (max) Bits LSB (min) LSB (max) mV ± 45 −0.6 −1.31 ± 25 ± 25 ± 15 mV (max) mV (max) %FS GHz Error/Sample dBFS dBFS Bits ± 20 1.7 10 -18 NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS ± 0.5 ± 1.0 7.5 7.4 7.4 7.0 7.0 Bits (min) Bits (min) 7 www.national.com ADC08D1000 Converter Electrical Characteristics (Continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ± 0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) 47 46.3 46.3 48 47.1 47.1 -55 -55 -55 −60 −60 −60 −65 −65 −65 55 55 55 -50 255 0 47.5 47.5 -47.5 -47.5 44.0 44.0 43.9 43.9 Limits (Note 8) Units (Limits) dB dB (min) dB (min) dB dB (min) dB (min) dB dB (max) dB (max) dB dB dB dB dB dB dB dB (min) dB (min) dB NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB SNR Signal-to-Noise Ratio fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB THD Total Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB 2nd Harm Second Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB 3rd Harm Third Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB SFDR Spurious-Free dynamic Range fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) FPBW (DES) ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR fIN1 = 321 MHz, VIN = FSR − 7 dB fIN2 = 326 MHz, VIN = FSR − 7 dB (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS Full Power Bandwidth Effective Number of Bits Signal to Noise Plus Distortion Ratio Signal to Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious Free Dynamic Range Dual Edge Sampling Mode fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB 900 7.3 7.3 46 46 46.4 46.4 -58 -58 -64 -64 -69 -69 57 57 47 47 570 730 790 950 6.8 6.8 42.5 42.5 43 43 -49 -49 MHz Bits (min) Bits (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB dB dB dB dB (min) dB (min) mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) ANALOG INPUT AND REFERENCE CHARACTERISTICS Full Scale Analog Differential Input Range FSR pin 14 Low FSR pin 14 High 650 870 VIN www.national.com 8 ADC08D1000 Converter Electrical Characteristics (Continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ± 0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) VCMO − 50 VCMO + 50 Units (Limits) mV (min) mV (max) pF pF pF pF 94 106 0.95 1.45 Ω (min) Ω (max) V (min) V (max) V V ppm/˚C 80 IBG = ± 100 µA TA = −40˚C to +85˚C, IBG = ± 100 µA 1.26 28 80 1.20 1.33 pF V (min) V (max) ppm/˚C pF ANALOG INPUT AND REFERENCE CHARACTERISTICS VCMI Analog Input Common Mode Voltage Analog Input Capacitance, Normal operation (Notes 10, 11) Analog Input Capacitance, DES Mode (Notes 10, 11) RIN Differential Input Resistance Differential Each input pin to ground Differential Each input pin to ground VCMO 0.02 1.6 0.08 2.2 100 CIN ANALOG OUTPUT CHARACTERISTICS VCMO VCMO_LVL TC VCMO CLOAD VCMO VBG TC VBG CLOAD VBG Common Mode Output Voltage VCMO input threshold to set DC Coupling mode Common Mode Output Voltage Temperature Coefficient Maximum VCMO load Capacitance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference load Capacitance 192 µA vs. 12 µA, TJ = 25˚C 192 µA vs. 12 µA, TJ = 85˚C VA = 1.8V VA = 2.0V TA = −40˚C to +85˚C 1.26 0.60 0.66 118 TEMPERATURE DIODE CHARACTERISTICS 71.23 85.54 mV mV ∆VBE Temperature Diode Voltage CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I,Q) X-TALK X-TALK Crosstalk from I (Agressor) to Q (Victim) Channel Crosstalk from Q (Agressor) to I (Victim) Channel Zero offset selected in Control Register Zero offset selected in Control Register FIN = 1.0 GHz Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. 1 1 1 LSB LSB LSB Degree dB dB