ADC08D1000WGFQV

ADC08D1000QML High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter November 9, 2009 ADC08D1000QML High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter General Description The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.2 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 Effective Number Of Bits (ENOB) with a 498 MHz input signal and a 1 GHz sample rate while providing a 10-18 Bit Error Rate ( B.E.R.). Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.13V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range. This part will work in a radiation environment, with excellent results, provided the guidelines in applications section 2.1 are followed. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Total Ionizing Dose 300 krad(Si) Single Event Latch-Up >120 MeV/mg/cm2 Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR output clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications ■ ■ ■ ■ ■ ■ Resolution Max Conversion Rate Bit Error Rate ENOB @ 498 MHz Input DNL Power Consumption — Operating — Power Down Mode 8 Bits 1 GSPS (min) 10-18 (typ) 7.4 Bits (typ) ±0.15 LSB (typ) 1.6 W (typ) 3.5 mW (typ) Applications ■ Communication Satellites/Systems ■ Direct RF Down Conversion © 2009 National Semiconductor Corporation 201802 www.national.com ADC08D1000QML Block Diagram www.national.com 2 20180253 ADC08D1000QML Ordering Information NS Part Number ADC08D1000WGFQV SMD Part Number 5962F0520601VZC 300 krad(Si) NS Package Number EM128A Package Description 128L, CERQUAD GULLWING Pin Configuration 20180201 * Bottom of package must be soldered to ground plane to ensure rated performance. 3 www.national.com ADC08D1000QML Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data.See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See Section 1.1.5.2). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See Section 1.5 for detailed description. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. Calibration Cycle Initiate. A minimum 640 input clock cycles logic low followed by a minimum of 640 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.5.2 for an overview of self-calibration and Section 2.5.2.2 for a description of on-command calibration. See Section 2.1 for use in Radiation Environments. Full Scale Range Select and Extended Control Enable. In nonextended control mode, a logic low on this pin sets the full-scale differential input range to 650 mVP-P. A logic high on this pin sets the full-scale differential input range to 870 mVP-P. See Section 1.1.4. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See Section 1.2 for information on the extended control mode. See Section 2.1 for use in Radiation Environments. Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See Section 1.1.1). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See Section 1.1.5.1. See Section 2.1 for use in Radiation Environments. 3 OutV / SCLK 4 OutEdge / DDR / SDATA 15 DCLK_RST 26 29 PD PDQ 30 CAL 14 FSR/ECE 127 CalDly / DES / SCS www.national.com 4 ADC08D1000QML Pin Functions Pin No. Symbol Equivalent Circuit Description 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.4 for an overview of the clock inputs. 11 10 . 22 23 VINI+ VINI− . VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when the FSR pin is high. 7 VCMO Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100μA. See Section 2.3. Bandgap output voltage capable of 100 μA source/sink. 31 VBG 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. 32 REXT External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. 34 35 Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See Section 2.7.2. 5 www.national.com ADC08D1000QML Pin Functions Pin No. 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 79 80 Symbol DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ OR+ OREquivalent Circuit Description I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±325 mV or ±435 mV as defined by the FSR pin). 82 81 DCLK+ DCLK- Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. DCLK outputs are not active during a calibration cycle. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51 ,62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27, 41 www.national.com VA Analog power supply pins. Bypass these pins to ground. VDR Output Driver power supply pins. Bypass these pins to DR GND. GND Ground return for VA. 6 ADC08D1000QML Pin Functions Pin No. 42, 53, 64, 74, 87, 97, 108, 119 52, 63, 98, 109, 120 Symbol DR GND Equivalent Circuit Ground return for VDR. No Connection. Make no connection to these pins. Description NC 7 www.national.com ADC08D1000QML Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage (VA, VDR) Voltage on Any Input Pin Voltage on VIN+, VIN(Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) ESD Susceptibility (Note 4) Human Body Model Soldering Temperature, Infrared, 10 seconds Storage Temperature 2.2V −0.15V to (VA +0.15V) −0.15V to 2.5V 0V to 100 mV ±25 mA ±50 mA   Class 3A (6000V) 235°C −65°C to +175°C Operating Ratings Ambient Temperature Range (Note 1, Note 2) −55°C ≤ TA ≤ +125°C +1.8V to +2.0V +1.8V to VA VCMO ±50mV 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V 0V to VA 0.4VP-P to 2.0VP-P 150°C Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude Maximum Junction Temperature Package Thermal Resistance Package 128L Cer Quad Gullwing θJA 11.5°C/W θJC (Top of Package) θJ-PAD (Thermal Pad) 3.8°C/W 2.0°C/W Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup 1 2 3 4 5 6 7 8A 8B 9 10 11 12 13 14 Description Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Setting time at Setting time at Setting time at Temp (°C) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 www.national.com 8 ADC08D1000QML ADC08D1000 Converter Electrical Characteristics DC Parameters The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX (Note 5, Note 6) Symbol Parameter Conditions Notes Typical (Note 7) Min Max Units Subgroups STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity (Best DC Coupled, 1MHz Sine Wave fit) Overanged Differential Non-Linearity Resolution with No Missing Codes VOFF PFSE NFSE Offset Error Positive Full-Scale Error Negative Full-Scale Error Out of Range Output Code (VIN+) − (VIN−) > + Full Scale (In addition to OR Output (VIN+) − (VIN−) < − Full Scale high) ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN RIN Full Scale Analog Differential Input Range Differential Input Resistance Common Mode Output Voltage Bandgap Reference Output IBG = ±100 µA Voltage Differential Clock Input Level Logic High Input Voltage Logic Low Input Voltage Measured differentially, OutV = VA, VBG = Floating Measured differentially, OutV = GND, VBG = Floating (Note 14) (Note 14) Sine Wave Clock Square Wave Clock FSR pin 14 High 870 100 790 94 950 106 mVP-P Ω 1, 2, 3 1, 2, 3 (Note 8) (Note 8) -0.45 −0.6 −1.31 −1.5 DC Coupled, 1MHz Sine Wave Overanged ±0.3 ±0.15 ±0.9 ±0.6 8 0.5 ±27 ±27 255 0 LSB LSB Bits LSB mV mV 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ANALOG OUTPUT CHARACTERISTICS VCMO VBG 1.26 1.26 0.95 1.20 1.45 1.33 V V 1, 2, 3 1, 2, 3 CLOCK INPUT CHARACTERISTICS VID 0.6 0.6 0.5 0.5 .85xVA .15xVA 2.0 2.0 VP-P VP-P V V 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 DIGITAL CONTROL PIN CHARACTERISTICS VIH VIL DIGITAL OUTPUT CHARACTERISTICS LVDS Differential Output Voltage 710 510 400 280 920 720 mVP-P mVP-P 1, 2, 3 1, 2, 3 VOD 9 www.national.com ADC08D1000QML Symbol Parameter Conditions Notes Typical (Note 7) 660 430 1.8 200 112 0.012 1.6 1.0 3.5 Min Max Units Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 765 508 275 157 1.97 1.27 mA mA mA mA mA mA W W mW IDR Output Driver Supply Current PD Power Consumption www.national.com 10 ADC08D1000QML AC Parameters The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX (Note 5, Note 6) Symbol Parameters Conditions Note Typical s (Note 7) 7.5 7.4 7.4 47 46.3 46.3 48 47.1 47.1 -55 -55 -55 57 57 1.2 47 1.0 −47.5 −47.5 44 44 43.9 43.9 7.0 7.0 Min Max Units Sub groups NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS fIN = 100 MHz, VIN = FSR − 0.5 dB ENOB Effective Number of Bits fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB SNR Signal-to-Noise Ratio fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB THD Total Harmonic Distortion Spurious Free Dynamic Range Maximum Input Clock Frequency fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB SFDR fCLK1 fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB Normal Mode (non DES) Bits Bits Bits dB dB dB dB dB dB dB dB dB dB dB GHz 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS ENOB SINAD SNR THD SFDR Effective Number of Bits Signal to Noise Plus Distortion Ratio Signal to Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB 7.3 7.3 46 46 46.4 46.4 -58 -58 57 57 47 −49 43 42.5 6.8 Bits Bits dB dB dB dB dB dB dB dB 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 AC Timing Parameters The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX (Note 5, Note 6) Symbol Parameters AC TIMING PARAMETERS tRPW Reset Pulse Width Serial Clock Low Time Serial Clock High Time tCAL_L tCAL_H CAL Pin Low Time CAL Pin High Time See Figure 9 See Figure 9 4 4 4 640 640 Clock Cycles ns ns Clock Cycles Clock Cycles 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Conditions Notes Typical (Note 7) Min Max Units Sub groups 11 www.national.com ADC08D1000QML Typical Electrical Characteristics DC Parameters The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. (Note 5, Note 6) Symbol Parameters Conditions Notes Typical (Note 7) ±45 ±20 1.7 10−18 d.c. to 498 MHz d.c. to 1 GHz fIN = 100 MHz, VIN = FSR − 0.5 dB 2nd Harm Second Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB 3rd Harm Third Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB IMD Intermodulation Distortion fIN1 = 321 MHz, VIN = FSR − 7 dB fIN2 = 326 MHz, VIN = FSR − 7 dB ±0.5 ±1.0 −60 −60 −60 −65 −65 −65 −50 Units STATIC CONVERTER CHARACTERISTICS VOFF_ADJ FS_ADJ FPBW B.E.R. Input Offset Adjustment Range Full-Scale Adjustment Range Full Power Bandwidth Bit Error Rate Gain Flatness Extended Control Mode Extended Control Mode Normal Mode (non DES) mV % FS GHz Error/Sample dBFS dBFS dB dB dB dB dB dB dB NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS INTERLEAVE MODE (DES Pin 127=Float) - Dynamic Converter Characteristics FPBW (DES) 2nd Harm 3rd Harm Full Power Bandwidth Second Harmonic Distortion Third Harmonic Distortion Dual Edge Sampling Mode fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN VCMI Full Scale Analog Differential Input Range Analog Input Common Mode Voltage Analog Input Capacitance, Normal operation Analog Input Capacitance, DES Mode Differential Each input pin to ground Differential Each input pin to ground (Note 9) (Note 9) (Note 9) (Note 9) FSR pin 14 Low 650 VCMO 0.02 1.6 0.08 2.2 mVp-p mVp-p mV mV pF pF pF pF 900 -64 -64 -69 -69 MHz dB dB dB dB CIN www.national.com 12 ADC08D1000QML Symbol Parameters Conditions Notes Typical (Note 7) 0.60 0.66 238 80 Units ANALOG OUTPUT CHARACTERISTICS VCMO_LVL VCMO input threshold to set DC Coupling mode Common Mode Output Voltage Temperature Coefficient Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference Load Capacitance 192 µA vs. 12 µA, TJ = 25°C 192 µA vs. 12 µA, TJ = 125°C VA = 1.8V VA = 2.0V TA = −55°C to +125°C V V ppm/°C pF (max) ppm/°C pF (max) TC VCMO CLOAD VCMO Maximum VCMO load Capacitance TC VBG CLOAD VBG TA = −55°C to +125°C, IBG = ±100 µA 61 80 TEMPERATURE DIODE CHARACTERISTICS 71.23 94.8 mV mV ΔVBE Temperature Diode Voltage CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) X-TALK X-TALK Crosstalk from I (Agressor) to Q (Victim) Channel Crosstalk from Q (Agressor) to I (Victim) Channel Input Current Input Capacitance Zero offset selected in Control Register Zero offset selected in Control Register FIN = 1.0 GHz Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. VIN = 0 or VIN = VA Differential Each input to ground DIGITAL CONTROL PIN CHARACTERISTICS CIN Δ VODIFF VOS VOS Δ VOS IOS ZO VOH VOL PSRR1 PSSR2 Input Capacitance Change in LVDS Output Swing Between Logic Levels Output Offset Voltage Output Offset Voltage Output Offset Voltage Change Between Logic Levels Output Short Circuit Current Differential Output Impedance CalRun H level output CalRun L level output D.C. Power Supply Rejection Ratio A.C. Power Supply Rejection Ratio IOH = -400uA IOH = -400uA Change in Full Scale Error with change in VA from 1.8V to 2.0V 248 MHz, 50mVP-P riding on VA (Note 11) (Note 11) Output+ & Output - connected to 0.8V VBG = Floating, See Figure 1 VBG = VA, See Figure 1 (Note 14) Each input to ground (Note 12) 1.2 ±1 800 1130 ±1 ±4 100 1.65 0.15 30 51 pF mV mV mV mV mA Ohms V V dB dB DIGITAL OUTPUT CHARACTERISTICS (Note 9) (Note 9) 1 1 1