ADC08D1520

ADC08D1520 Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter April 7, 2008 ADC08D1520 Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter General Description The ADC08D1520 is a dual, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1500 platform. The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1500, which include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 1.6 Watts in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad, LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Single +1.9V ±0.1V Operation Interleave Mode for 2x Sample Rate Multiple ADC Synchronization Capability Adjustment of Input Full-Scale Range, Clock Phase, and Offset Choice of SDR or DDR Output Clocking 1:1 or 1:2 Selectable Output Demux Second DCLK Output Duty Cycle Corrected Sample Clock Test pattern Key Specifications ■ ■ ■ ■ ■ ■ Resolution 8 Bits Max Conversion Rate 1.5 GSPS (max) Code Error Rate 10-18 (typ) ENOB @ 748 MHz Input 7.4 Bits (typ) DNL ±0.15 LSB (typ) Power Consumption (Non-DES Mode) 1.6 W (typ) — Operating in Non-demux Mode 2.0 W (typ) — Operating in 1:2 Demux Mode 3.5 mW (typ) — Power Down Mode Applications ■ ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC08D1520CIYB ADC08D1520CIYB/NOPB ADC08D1520DEV NS Package Leaded 128-Pin Exposed Pad LQFP Lead-free 128-Pin Exposed Pad LQFP Development Board © 2008 National Semiconductor Corporation 201931 www.national.com ADC08D1520 Block Diagram 20193153 www.national.com 2 ADC08D1520 Pin Configuration 20193101 Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 www.national.com ADC08D1520 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin logic high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See 1.1.6 The LVDS Outputs. When the Extended Control Mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for details on the Extended Control Mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. Power Down Q-channel. A logic high on the PDQ pin puts only the Q-channel into the Power Down Mode. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. See 1.1.5.2 OutEdge and Demultiplex Control Setting. When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the Extended Control Mode is enabled, this pin functions as the SDATA input. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for details on the Extended Control Mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. DCLK Reset. When single-ended DCLK_RST is selected by floating or setting pin 52 logic high, a positive pulse on this pin is used to reset and synchronize the DCLK outputs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. When differential DCLK_RST is selected by setting pin 52 logic low, this pin receives the positive polarity of a differential pulse signal used to reset and synchronize the DCLK outputs of multiple converters. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the self calibration sequence. See 2.4.2 Calibration for an overview of calibration and 2.4.2.2 On-Command Calibration for a description of oncommand calibration. The calibration cycle may similarly be initiated via the CAL bit in the Calibration register (0h). 3 OutV / SCLK 29 PDQ 4 OutEdge / DDR / SDATA 15 DCLK_RST / DCLK_RST+ 26 PD 30 CAL www.national.com 4 ADC08D1520 Pin Functions Pin No. Symbol Equivalent Circuit Description Full Scale Range Select, Alternate Extended Control Enable and DCLK_RST-. This pin has three functions. It can conditionally control the ADC full-scale voltage, enable the Extended Control Mode, or become the negative polarity signal of a differential pair in differential DCLK_RST mode. If pin 52 is floating or at logic high and pin 41 is floating, this pin can be used to set the full-scale-range or can be used as an alternate Extended Control Mode enable pin. When used as the FSR pin, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the Extended Control Mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for information on the Extended Control Mode. Note that pin 41 overrides the Extended Control Mode enable of this pin. When pin 52 is held at logic low, this pin acts as the DCLK_RST- pin. When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. In non-extended control mode, this pin functions as the Calibration Delay select. A logic high or low the number of input clock cycles after power up before calibration begins (See 1.1.1 Calibration). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) Mode is selected where the I-channel is sampled at twice the input clock rate and the Q-channel is ignored. See 1.1.5.1 Dual-Edge Sampling. In extended control mode, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). 14 FSR/ALT_ECE/ DCLK_RST- 127 CalDly / DES / SCS 18 19 CLK+ CLK- Differential clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for a description of acquiring the input and 2.3 THE CLOCK INPUTS for an overview of the clock inputs. 10 11 22 23 VINIVINI+ VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in Non-Extended Control Mode and the Input Full-Scale Voltage Adjust register in the Extended Control Mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the NonExtended Control Mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the Extended Control Mode. 5 www.national.com ADC08D1520 Pin Functions Pin No. Symbol Equivalent Circuit Description Common Mode Voltage. This pin is the common mode output in d.c. coupling mode and also serves as the a.c. coupling mode select pin. When d.c. coupling is used at the analog inputs, the voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN−. When a.c. coupling is used, this pin should be grounded. This pin is capable of sourcing or sinking 100 μA. See 2.2 THE ANALOG INPUT. Bandgap output voltage. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. 7 VCMO 31 VBG 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. 32 REXT External bias resistor connection. Nominal value is 3.3 kΩ (±0.1%) to ground. See 1.1.1 Calibration. 34 35 Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode). This pin is used for die temperature measurements. See 2.6.2 Thermal Management. 41 ECE Extended Control Enable. This pin always enables or disables Extended Control Mode. When this pin is set logic high, the Extended Control Mode is inactive and all control of the device must be through control pins only . When it is set logic low, the Extended Control Mode is active. This pin overrides the Extended Control Enable signal set using pin 14. DCLK_RST select. This pin selects whether the DCLK is reset using a single-ended or differential signal. When this pin is floating or logic high, the DCLK_RST operation is single-ended and pin 14 functions as FSR/ALT_ECE. When this pin is logic low, the DCLK_RST operation becomes differential with functionality on pin 15 (DCLK_RST+) and pin 14 (DCLK_RST-). When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. When pin 41 is set logic low, the Extended Control Mode is active and the FullScale Voltage Adjust registers can be programmed. 52 DRST_SEL www.national.com 6 ADC08D1520 Pin Functions Pin No. 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 Symbol DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ Equivalent Circuit Description I- and Q-channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. In Non-demultiplexed Mode, only these outputs are active. I- and Q-channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI and DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. In Non-demultiplexed Mode, these outputs are disabled and are high impedance. When disabled, these outputs must be left floating. 79 80 OR+/DCLK2+ OR-/DCLK2- Out Of Range, second Data Clock output. When functioning as OR+/-, a differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in Non-extended Control Mode or the Input Full-Scale Voltage Adjust register setting in the Extended Control Mode). This single out of range indication is for both the I- and Q-channels, unless PDQ is asserted, in which case it only applies to the I-channel input. When functioning as DCLK2+/-, DCLK2 is the exact replica of DCLK and outputs the same signal at the same rate. The functionality of these pins is selectable in Extended Control Mode only; default is OR+/-. 7 www.national.com ADC08D1520 Pin Functions Pin No. Symbol Equivalent Circuit Description Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode, this signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. In the Non-demux Mode, DCLK can only be in DDR mode and is at 1/2 the input clock rate. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination resistor trim portion of the cycle can be disabled by setting the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register. This disables all subsequent termination resistor trims after the initial trim which occurs during power-on calibration. This output is not recommended as a system clock unless the resistor trim is disabled. 81 82 DCLKDCLK+ 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51, 62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27 42, 53, 64, 74, 87, 97, 108, 119 63, 98, 109, 120 VA Analog power supply pins. Bypass these pins to ground. VDR GND Output Driver power supply pins. Bypass these pins to DR GND. Ground return for VA. Ground return for VDR. No Connection. Make no connection to these pins. DR GND NC www.national.com 8 ADC08D1520 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA ≤ 85°C ESD Susceptibility (Note 4) Human Body Model Machine Model Charged Device Model Storage Temperature 2.2V 0V to 100 mV −0.15V to (VA +0.15V) 0V to 100 mV ±25 mA ±50 mA 2.35 W   2500V 250V 1000V −65°C to +150°C Operating Ratings Ambient Temperature Range (Notes 1, 2) −40°C ≤ TA ≤ +85°C +1.8V to +2.0V +1.8V to VA VCMO ±50 mV 200mV to VA 0V 0V to VA 0.4VP-P to 2.0VP-P θJC Top of Package 10°C / W θJC Thermal Pad 2.8°C / W Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude Package Thermal Resistance Package 128-Lead, Exposed Pad LQFP θJA 26°C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 5) Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870 mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Demultiplex Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7, 16) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity (Best fit) Differential Non-Linearity Resolution with No Missing Codes VOFF VOFF_ADJ PFSE NFSE FS_ADJ FPBW C.E.R. Offset Error Input Offset Adjustment Range Extended Control Mode Positive Full-Scale Error Negative Full-Scale Error Full-Scale Adjustment Range Full Power Bandwidth Code Error Rate Gain Flatness ENOB SINAD SNR Effective Number of Bits d.c. to 748 MHz d.c. to 1.5 GHz fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB (Note 9) (Note 9) Extended Control Mode Non-DES Mode ±20 2.0 10−18 ±0.5 ±1.0 7.4 7.4 46.5 46.4 46.8 47 44.0 42.5 6.8 −0.75 ±45 ±25 ±25 ±15 DC Coupled, 1 MHz Sine Wave Overranged DC Coupled, 1 MHz Sine Wave Overranged ±0.3 ±0.15 ±0.9 ±0.6 8 LSB (max) LSB (max) Bits LSB mV mV (max) mV (max) %FS GHz Error/Sample dBFS dBFS Bits (min) Bits dB (min) dB dB (min) dB 1:2 DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ Signal-to-Noise Plus Distortion fIN = 373 MHz, VIN = FSR − 0.5 dB Ratio fIN = 748 MHz, VIN = FSR − 0.5 dB Signal-to-Noise Ratio fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB 9 www.national.com ADC08D1520 Symbol THD 2nd Harm 3rd Harm SFDR IMD Parameter Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Out of Range Output Code Conditions fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN1 = 365 MHz, VIN = FSR − 7 dB fIN2 = 375 MHz, VIN = FSR − 7 dB (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB Typical (Note 8) −58 −55 −65 −59 −58 −58 58 55 −50 Limits (Note 8) -47.5 Units (Limits) dB (max) dB dB dB dB dB 47.5 dB (min) dB dB 255 0 7.3 7.3 45.7 45.7 46 46 -57 -57 -63 -63 -64 -64 57 57 1.3 7.0 44 46.3 −47 −55 −64 47 590 730 800 940 VCMO − 0.05 VCMO + 0.05 Bits Bits dB dB dB dB dB dB dB dB dB dB dB dB GHz Bits dB dB dB dB dB dB mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) V (min) V (max) NON-DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1 GHZ ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Effective Number of Bits Signal to Noise Plus Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB Ratio fIN = 498 MHz, VIN = FSR − 0.5 dB Signal to Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious Free Dynamic Range fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB DES Mode fIN = 748 MHz, VIN = FSR − 0.5 dB 1:4 DEMUX DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ FPBW ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Full Power Bandwidth Effective Number of Bits Signal to Noise Plus Distortion fIN = 748 MHz, VIN = FSR − 0.5 dB Ratio Signal to Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB Spurious Free Dynamic Range fIN = 748 MHz, VIN = FSR − 0.5 dB ANALOG INPUT AND REFERENCE CHARACTERISTICS Full Scale Analog Differential Input Range FSR pin 14 Low FSR pin 14 High 650 870 VCMO VIN VCMI Common Mode Input Voltage www.national.com 10 ADC08D1520 Symbol Parameter Analog Input Capacitance, Normal operation (Notes 10, 11) Analog Input Capacitance, DES Mode (Notes 10, 11) Differential Conditions Typical (Note 8) 0.02 1.6 0.08 2.2 100 Limits (Note 8) Units (Limits) pF pF pF pF CIN Each input pin to ground Differential Each input pin to ground RIN Differential Input Resistance 94 106 0.95 1.45 Ω (min) Ω (max) V (min) V (max) ppm/°C V V ANALOG OUTPUT CHARACTERISTICS VCMO TC VCMO VCMO_LVL CLOAD VCMO VBG TC VBG CLOAD VBG Common Mode Output Voltage ICMO = ±100 µA Common Mode Output Voltage TA = −40°C to +85°C Temperature Coefficient VCMO input threshold to set D.C. VA = 1.8V Coupling mode VA = 2.0V Maximum VCMO Load Capacitance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference load Capacitance Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Crosstalk from Q-channel (Aggressor) to I-channel (Victim) Zero offset selected in Control Register Zero offset selected in Control Register fIN = 1.5 GHz Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. 1 1 1