ADC08D1520QML

ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter March 6, 2008 ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter General Description The ADC08D1520QML is an 8–Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1520QML digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, that output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC. The converter typically consumes less than 2.9 mW in the Power Down Mode and is available in a 128-pin, thermally enhanced, multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single +1.9V ±0.1V Operation Interleave Mode for 2x Sample Rate Multiple ADC Synchronization Capability Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment Choice of SDR or DDR output clocking 1:1 or 1:2 Selectable Output Demux Second DCLK output Duty Cycle Corrected Sample Clock Test pattern Serial Interface for Extended Control Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ Resolution Max Conversion Rate Code Error Rate ENOB @ 748 MHz Input DNL Total Ionizing Dose Single Event Latch-up Power Consumption — Operating in 1:2 Demux Output — Power Down Mode 8 Bits 1.5 GSPS (min) 10-18 (typ) 7.2 Bits (typ) ±0.15 LSB (typ) 300 krad(Si) 120 MeV-cm2/mg 2.0 W (typ) 2.9 mW (typ) Applications ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Communications Systems Test Instrumentation Ordering Information NS Part Number ADC08D1520WG-QV ADC08D1520WGFQV SMD Part Number 5962–0721401VZC 5962F0721401VZC 300 krad(Si) NS Package Number EM128A EM128A Package Discription 128L, CERQUAD GULLWING 128L, CERQUAD GULLWING © 2008 National Semiconductor Corporation 300247 www.national.com ADC08D1520QML Block Diagram 30024753 www.national.com 2 ADC08D1520QML Pin Configuration 30024701 Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 www.national.com ADC08D1520QML Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See 1.1.6 The LVDS Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NON-EXTENDED CONTROL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. A logic high on the PDQ pin puts only the Q-Channel ADC into the Power Down mode. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. See 1.1.5.2 OutEdge and Demultiplex Control Setting When this pin is connected to 1/2 the supply voltage,VA/2, DDR clocking is enabled. When the Extended Control Mode is enabled, this pin functions as the SDATA input. See 1.2 NON-EXTENDED CONTROL/ EXTENDED CONTROL for details on the Extended Control Mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. DCLK Reset. When single-ended DCLK_RST is selected by setting pin 52 logic high or to VA/2, a positive pulse on this pin is used to reset and synchronize the DCLK outputs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. When differential DCLK_RST is selected by setting pin 52 logic low, this pin receives the positive polarity of a differential pulse signal used to reset and synchronize the DCLK outputs of multiple converters. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the calibration sequence. See 2.5.2 Calibration for an overview of calibration and 2.5.2.1 Initiating Calibration for a description of calibration. Full Scale Range Select, Alternate Extended Control Enable and DCLK_RST-. This pin has two functions. It can conditionally control the ADC full-scale voltage, or become the negative polarity signal of a differential pair in differential DCLK_RST Mode. If pin 52 and pin 41 are connected at logic high, this pin can be used to set the full-scale-range. When used as the FSR pin, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level. A logic high on this pin sets the full-scale differential input range to Higher VIN input level. See Converter Electrical Characteristics. When pin 52 is held at logic low, this pin acts as the DCLK_RST- pin. When in differential DCLK_RST Mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. 3 OutV / SCLK 29 PDQ 4 OutEdge / DDR / SDATA 15 DCLK_RST/ DCLK_RST+ 26 PD 30 CAL 14 FSR/DCLK_RST- www.national.com 4 ADC08D1520QML Pin Functions Pin No. Symbol Equivalent Circuit Description Dual Edge Sampling and Serial Interface Chip Select. With pin 41 logic low, the device is in Extended Control Mode and this pin is the enable pin for the Serial Interface . When in Non-Extended Control Mode and this pin is connected to VA/2, DES Mode is selected where the I- Channel input is sampled at twice the input clock rate and the Q- Channel input is ignored. See 1.1.5.1 Dual-Edge Sampling. When in Non-Extended Controll Mode and DES is not desired, this pin should be tied to VA. 127 DES / SCS 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for a description of acquiring the input and 2.4 THE CLOCK INPUTS for an overview of the clock inputs. 10 11 .22 23 VINI− VINI+ VINQ+ VINQ− Analog signal inputs to the ADC. These differential input signals must be a.c. coupled to these pins. The differential full-scale input range is programmable using the FSR pin 14 in Non-Extended Control Mode and the Input Full-Scale Voltage Adjust register in the Extended Control Mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the NonExtended Control Mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the Extended Control Mode. Bandgap output voltage. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. 31 VBG 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. 32 REXT External bias resistor connection. Nominal value is 3.3 kΩ (±0.1%) to ground. See 1.1.1 Calibration. 5 www.national.com ADC08D1520QML Pin Functions Pin No. 34 35 Symbol Tdiode_P Tdiode_N Equivalent Circuit Description Temperature Diode Positive (Anode and Negative (Cathode). This pin is used for die temperature measurements. See 2.7.2 Thermal Management. 41 ECE Extended Control Enable. This pin always enables or disables Extended Control Mode. When this pin is set logic high, the Extended Control Mode is inactive and all control of the device must be through control pins only . When it is set logic low, the Extended Control Mode is active. This pin overrides the Extended Control Enable signal set using pin 14. 52 DRST_SEL DCLK_RST select. This pin selects whether the DCLK is reset using a single-ended or differential signal. When this pin is connected at logic high, the DCLK_RST operation is single-ended and pin 14 functions as FSR/ALT_ECE. When this pin is logic low, the DCLK_RST operation becomes differential with functionality on pin 15 (DCLK_RST+) and pin 14 (DCLK_RST-). When in differential DCLK_RST Mode, there is no pin-controlled FSR and the full-scale-range is defaulted to 870mV. When pin 41 is set logic low, the Extended Control Mode is active and the Full-Scale Voltage Adjust registers can be programmed. www.national.com 6 ADC08D1520QML Pin Functions Pin No. 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 Symbol DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ Equivalent Circuit Description I- and Q- channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. I- and Q- channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI and DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. In Non Demux Mode, these outputs are disabled and are high impedance. When disabled, these outputs must be left floating. 79 80 OR+/DCLK2+ OR-/DCLK2- Out Of Range output. A differential high at these pins indicates that the differential input is out of range ±VIN/2 as programmed by the FSR pin in Non-Extended Control Mode or the Input Full-Scale Voltage Adjust register setting in the Extended Control Mode). DCLK2 is the exact mirror of DCLK and should output the same signal at the same rate. Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. In 1:2 Demultiplexed Mode, this signal is at 1/2 the input clock rate in SDR Mode and at 1/4 the input clock rate in the DDR Mode. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination resistor trim portion of the cycle can be disabled by setting the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register (address 9h). This disables all subsequent termination resistor trims after the initial trim which occurs during the power on calibration. Therefore, this output is not recommended as a system clock unless the resistor trim is disabled. When the device is in the Non-Demultiplexed Mode, DCLK can only be in DDR Mode and the signal is at 1/2 the input clock rate. 81 82 DCLKDCLK+ 7 www.national.com ADC08D1520QML Pin Functions Pin No. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51, 62, 73, 88, 99, 110, 121 1, 6, 7, 9, 12, 21, 24, 27 42, 53, 64, 74, 87, 97, 108, 119 63, 98, 109, 120 Symbol Equivalent Circuit Description VA Analog power supply pins. Bypass these pins to ground. VDR Output Driver power supply pins. Bypass these pins to DR GND. GND Ground return for VA. DR GND Ground return for VDR. No Connection. Make no connection to these pins. NC www.national.com 8 ADC08D1520QML Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Junction Temperature ESD Susceptibility (Note 4) Human Body Model Storage Temperature 2.2V 0V to 100 mV −0.15V to (VA +0.15V) 0V to 100 mV ±25 mA ±50 mA Operating Ratings Ambient Temperature Range VA/2 Tolerance for supply 1.9V Supply Voltage (VA) Driver Supply Voltage (VDR) VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude (Notes 1, 2) −55°C ≤ TA ≤ +125°C 650mV ≥ VA/2 ≤ 1.2V +1.8V to +2.0V +1.8V to VA 200mV to VA 0V 0V to VA 0.4VP-P to 2.0VP-P θJC Top of Package 3.8°C/ W θJC Thermal Pad 2.0°C/ W ≤ 175°C   Class 3A (6000V) −65°C to +175°C Package Thermal Resistance Package 128L Cer Quad Gullwing θJA 11.5°C/ W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup 1 2 3 4 5 6 7 8A 8B 9 10 11 12 13 14 Description Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Setting time at Setting time at Setting time at Temp ( C) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 9 www.national.com ADC08D1520QML ADC08D1520QML Converter Electrical Characteristics DC Parameters (Note 14) The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870 mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-Extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Output Demultiplex, duty cycle stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 5, 6) Symbol Parameter Conditions Notes Typical (Note 7) Min Max Units Subgroups STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity (Best fit) Differential Non-Linearity Resolution with No Missing Codes VOFF PFSE NFSE Offset Error Positive Full-Scale Error Negative Full-Scale Error (Note 8) (Note 8) −0.55 −0.6 −1.31 −1.5 DC Coupled, 1 MHz Sine Wave Overanged DC Coupled, 1 MHz Sine Wave Overanged ±0.3 ±0.15 ±.9 ±.6 8 1.5 ±25 ±25 LSB LSB Bits LSB mV mV 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ANALOG INPUT AND REFERENCE CHARACTERISTICS FSR pin 14 Low VIN Full Scale Analog Differential Input Range FSR pin 14 High RIN Differential Input Resistance Bandgap Reference Output Voltage 900 100 600 530 650 840 960 94 106 1.20 1.33 .5 2.0 .5 2.0 0.85 x VA 0.15 x VA Measured differentially, OutV = VA, VBG = Floating Measured differentially, OutV = GND, VBG = Floating (Note 13) (Note 13) 580 920 380 720 mVP-P mVP-P mVP-P mVP-P Ω Ω V V VP-P VP-P VP-P VP-P 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ANALOG OUTPUT CHARACTERISTICS VBG IBG = ±100 µA 1.26 CLOCK INPUT CHARACTERISTICS Sine Wave Clock VID Differential Clock Input Level Square Wave Clock DIGITAL CONTROL PIN CHARACTERISTICS VIH VIL Logic High Input Voltage Logic Low Input Voltage V V 1, 2, 3 1, 2, 3 0.6 0.6 DIGITAL OUTPUT CHARACTERISTICS 780 590 mVP-P mVP-P mVP-P mVP-P 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LVDS Differential Output Voltage VOD www.national.com 10 ADC08D1520QML Symbol Parameter Conditions Notes Typical (Note 7)   820 565 1.5   230 125 0.018   2 1.3 2.9 Min Max Units Subgroups POWER SUPPLY CHARACTERISTICS 1:2 Demux Output PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 1:2 Demux Output PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 1:2 Demux Output PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High   875 615   290 170   2.2 1.49   mA (max) mA (max) mA   mA (max) mA (max) mA   W (max) W (max) mW 1, 2, 3 1, 2, 3 IA Analog Supply Current IDR Output Driver Supply Current 1, 2, 3 1, 2, 3 PD Power Consumption 1, 2, 3 1, 2, 3 AC Parameters Symbol Parameter (Note 14) Conditions Notes Typical (Note 7) 7.4 7.2 46.3 45.4 47 45 −53.4 −53 55.5 53 255 0 7.0 44 44 −55 50 44.1 6.6 41.5 41.5 −45.2 Bits dB dB dB dB 47.5 −47.5 43.9 43.9 Min Max Units Subgroups 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 Non-DES MODE DYNAMIC CONVERTER CHARACTERISTICS, 1:2 DEMUX MODE ENOB SINAD SNR THD SFDR Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free dynamic Range Out of Range Output Code fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 748 MHz, VIN = FSR − 0.5 dB (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB fIN = 373 MHz, VIN = FSR − 0.5 dB 7 Bits (min) Bits (min) dB (min) dB (min) dB (min) dB (min) dB (max) dB (max) dB (min) dB (min) INTERLEAVE MODE (DES Pin 127=VA/2) - DYNAMIC CONVERTER CHARACTERISTICS, 1:4 DEMUX MODE ENOB SINAD SNR THD SFDR Effective Number of Bits Signal to Noise Plus Distortion Ratio Signal to Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range 11 www.national.com ADC08D1520QML AC Timing Parameters Symbol Parameter (Note 14) Conditions Notes Typical (Note 7) Min Max Units Subgroups AC TIMING CHARACTERISTICS Maximum Input Clock Frequency Non-DES Mode or DES Mode in 1:2 Output Demux Non-DES Mode or DES Mode in Non-demux Output 50 45 55 4 1.7 1.5 1.0 GHz GHz % % CLK± Cycles (min) CLK± Cycles CLK± Cycles 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 fCLK(max) DCLK Duty Cycle tPWR tCAL_L tCAL_H Pulse Width DCLK_RST± CAL Pin Low Time CAL Pin High Time See Figure 10 See Figure 10 1280 1280 9, 10, 11 9, 10, 11 www.national.com 12 ADC08D1520QML Typical Electrical Characteristics DC Parameters The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870 mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-Extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Output Demultiplex, duty cycle stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 5, 6) Symbol Parameter Conditions Notes Typical (Note 7) ±45 ±20 0.02 1.6 0.08 2.2 Units STATIC CONVERTER CHARACTERISTICS VOFF_ADJ FS_ADJ Input Offset Adjustment Range Full-Scale Adjustment Range Analog Input Capacitance, Normal operation Analog Input Capacitance, DES Mode Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference load Capacitance 192 µA vs 12 µA, TJ = 25°C 192 µA vs 12 µA, TJ = 125°C Extended Control Mode Extended Control Mode Differential Each input pin to ground Differential Each input pin to ground TA = −55°C to +125°C, IBG = ±100 µA mV %FS pF pF pF pF ANALOG INPUT AND REFERENCE CHARACTERISTICS (Note 9) (Note 9) CIN ANALOG OUTPUT CHARACTERISTICS TC VBG CLOAD VBG 61 80 ppm/°C pF TEMPERATURE DIODE CHARACTERISTICS ΔVBE Temperature Diode Voltage 71.23 94.8 1 Zero offset selected in Control Register Zero offset selected in Control Register fIN = 1.0 GHz Aggressor = 1160 MHz F.S. Victim = 100 MHz F.S. Aggressor = 1160 MHz F.S. Victim = 100 MHz F.S. 1 1