ADC08D500_08

ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter March 11, 2008 ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter General Description The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 800 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR output clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications ■ ■ ■ ■ ■ ■ ■ Resolution Max Conversion Rate Bit Error Rate ENOB @ 250 MHz Input DNL Power Consumption — Operating — Power Down Mode 8 Bits 500 MSPS (min) 10-18 (typ) 7.5 Bits (typ) ±0.15 LSB (typ) 1.4 W (typ) 3.5 mW (typ) Applications ■ ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Block Diagram 20121453 © 2008 National Semiconductor Corporation 201214 www.national.com ADC08D500 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC08D500CIYB ADC08D500EVAL NS Package 128-Pin Exposed Pad LQFP Evaluation Board Pin Configuration 20121401 * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com 2 ADC08D500 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description 3 OutV / SCLK Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. 4 OutEdge / DDR / SDATA DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See Section 1.1.5.2). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface. 15 DCLK_RST DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See Section 1.5 for detailed description. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.4.2 for an overview of self-calibration and Section 2.4.2.2 for a description of on-command calibration. 26 PD 30 CAL 29 PDQ A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. 14 FSR/ECE Full Scale Range Select and Extended Control Enable. In nonextended control mode, a logic low on this pin sets the full-scale differential input range to 650 mVP-P. A logic high on this pin sets the full-scale differential input range to 870 mVP-P. See Section 1.1.4. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See Section 1.2 for information on the extended control mode. 3 www.national.com ADC08D500 Pin Functions Pin No. Symbol Equivalent Circuit Description Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of clock cycles after power up before calibration begins (See Section 1.1.1). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes 0b (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the clock rate and the "Q" input is ignored. See Section 1.1.5.1. 127 CalDly / DES / SCS 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.3 for an overview of the clock inputs. 11 10 . 22 23 VINI+ VINI− . VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when the FSR pin is high. 7 VCMO Common Mode Voltage. This pin is the common mode output in d.c. coupling mode and also serves as the a.c. coupling mode select pin. When d.c. coupling is used, the voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100 μA. See Section 2.2. Bandgap output voltage capable of 100 μA source/sink. 31 VBG 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. www.national.com 4 ADC08D500 Pin Functions Pin No. Symbol Equivalent Circuit Description 32 REXT External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. 34 35 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 79 80 Tdiode_P Tdiode_N DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ OR+ OR- Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See Section 2.6.2. I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±325 mV or ±435 mV as defined by the FSR pin). Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle, therefore this is not recommended as a system clock. 82 81 DCLK+ DCLK- 5 www.national.com ADC08D500 Pin Functions Pin No. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51 ,62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27, 41 42, 53, 64, 74, 87, 97, 108, 119 52, 63, 98, 109, 120 Symbol Equivalent Circuit Description VA Analog power supply pins. Bypass these pins to ground. VDR Output Driver power supply pins. Bypass these pins to DR GND. GND Ground return for VA. DR GND Ground return for VDR. No Connection. Make no connection to these pins. NC www.national.com 6 ADC08D500 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA = 85°C ESD Susceptibility (Note 4) Human Body Model Machine Model Soldering Temperature, Infrared, 10 seconds (Note 5) Storage Temperature 2.2V 0V to 100 mV −0.15V to (VA +0.15V) 0V to 100 mV ±25 mA ±50 mA 2.0 W   2500V 250V 235°C −65°C to +150°C Operating Ratings Ambient Temperature Range (Notes 1, 2) −40°C ≤ TA ≤ +85°C +1.8V to +2.0V +1.8V to VA VCMO ±50mV 200mV to VA 0V 0V to VA 0.4VP-P to 2.0VP-P θJ-PAD (Thermal Pad) Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude Package Thermal Resistance Package 128-Lead Exposed Pad LQFP θJA 25°C / W θJC (Top of Package) 10°C / W 2.8°C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity Differential Non-Linearity Resolution with No Missing Codes VOFF Offset Error Extended Control Mode -0.45 ±45 −0.6 −1.31 Extended Control Mode Normal (non DES) Mode d.c. to 500 MHz fIN = 50 MHz, VIN = FSR − 0.5 dB ENOB Effective Number of Bits fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB SNR Signal-to-Noise Ratio fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB ±20 1.7 10-18 ±0.5 7.5 7.5 7.5 47 47 47 48 48 47.5 45.3 45.3 44.5 44.5 7.1 7.1 ±25 ±25 ±15 DC Coupled, 1MHz Sine Wave Over ranged DC Coupled, 1MHz Sine Wave Over ranged ±0.3 ±0.15 ±0.9 ±0.6 8 −1.5 0.5 LSB (max) LSB (max) Bits LSB (min) LSB (max) mV mV (max) mV (max) %FS GHz Error/Sample dBFS Bits Bits (min) Bits (min) dB dB (min) dB (min) dB dB (min) dB (min) VOFF_ADJ Input Offset Adjustment Range PFSE NFSE FS_ADJ FPBW B.E.R. Positive Full-Scale Error (Note 9) Negative Full-Scale Error (Note 9) Full-Scale Adjustment Range Full Power Bandwidth Bit Error Rate Gain Flatness NORMAL MODE (non DES) DYNAMIC CONVERTER CHARACTERISTICS 7 www.national.com ADC08D500 Symbol Parameter Conditions fIN = 50 MHz, VIN = FSR − 0.5 dB Typical (Note 8) -55 -55 -55 −60 −60 −60 −65 −65 −65 55 55 55 -50 Limits (Note 8) −47.5 −47.5 Units (Limits) dB dB (max) dB (max) dB dB dB dB dB dB dB THD Total Harmonic Distortion fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB 2nd Harm Second Harmonic Distortion fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB 3rd Harm Third Harmonic Distortion fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB SFDR Spurious-Free dynamic Range fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN1 = 121 MHz, VIN = FSR − 7 dB fIN2 = 126 MHz, VIN = FSR − 7 dB (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale 47.5 47.5 dB (min) dB (min) dB IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) 255 0 INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS FPBW (DES) ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Full Power Bandwidth Effective Number of Bits Signal to Noise Plus Distortion Ratio Signal to Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious Free Dynamic Range Dual Edge Sampling Mode fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 100 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB 900 7.4 7.4 46.3 46.3 46.7 46.7 -58 -58 -60 -60 -64 -64 57 57 47 47 570 730 790 950 VCMO − 50 VCMO + 50 7.0 7.0 43.9 43.9 44.1 44.1 -49 -49 MHz Bits (min) Bits (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB dB dB dB dB(min) dB dB (min(min) mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) mV (min) mV (max) pF pF pF pF 94 106 Ω (min) Ω (max) ANALOG INPUT AND REFERENCE CHARACTERISTICS FSR pin 14 Low VIN Full Scale Analog Differential Input Range FSR pin 14 High VCMI Analog Input Common Mode Voltage Analog Input Capacitance, Normal operation (Notes 10, 11) Differential Each input pin to ground 870 VCMO 0.02 1.6 0.08 2.2 100 650 CIN Analog Input Capacitance, DES Mode Differential (Notes 10, 11) Each input pin to ground Differential Input Resistance RIN ANALOG OUTPUT CHARACTERISTICS www.national.com 8 ADC08D500 Symbol VCMO VCMO_LVL TC VCMO CLOAD VCMO VBG TC VBG CLOAD VBG Parameter Common Mode Output Voltage VCMO input threshold to set DC Coupling mode Common Mode Output Voltage Temperature Coefficient Maximum VCMO load Capacitance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference Load Capacitance VA = 1.8V VA = 2.0V Conditions Typical (Note 8) 1.26 0.60 0.66 118 Limits (Note 8) 0.95 1.45 Units (Limits) V (min) V (max) V V ppm/°C TA = −40°C to +85°C 80 IBG = ±100 µA TA = −40°C to +85°C, IBG = ±100 µA 1.26 28 80 1.20 1.33 pF V (min) V (max) ppm/°C pF TEMPERATURE DIODE CHARACTERISTICS 192 µA vs. 12 µA, TJ = 25°C 192 µA vs. 12 µA, TJ = 85°C 71.23 85.54 mV mV ΔVBE Temperature Diode Voltage CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Error Match Positive Full-Scale Error Match Negative Full-Scale Error Match Phase Matching (I, Q) X-TALK X-TALK Crosstalk from I (Aggressor) to Q (Victim) Channel Crosstalk from Q (Aggressor) to I (Victim) Channel Zero offset selected in Control Register Zero offset selected in Control Register FIN = 1.0 GHz Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. 1 1 1