ADC08L060CIMT

ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold January 7, 2008 ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold General Description The ADC08L060 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS. Raising the PD pin puts the ADC08L060 into a Power Down mode where it consumes about 1 mW. The unique architecture achieves 7.6 Effective Bits. The ADC08L060 is resistant to latch-up and the outputs are shortcircuit proof. The top and bottom of the ADC08L060s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/ CMOS compatible with a separate output power supply pin to support interfacing with 1.8V to 3V logic. The output coding is straight binary and the digital inputs (CLK and PD) are TTL/ CMOS compatible. The ADC08L060 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40°C to +85°C. An evaluation board is available to assist in the evaluation of the ADC08L060. Features ■ ■ ■ ■ ■ Single-ended input Internal sample-and-hold function Low voltage (single +3V) operation Small package Power-down feature Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Resolution Conversion rate DNL INL SNR (10.1 MHz) ENOB (10.1 MHz) THD (10.1 MHz) Latency No missing codes Power Consumption — Operating — Power Down Mode 8 bits 60 MSPS ±0.25 LSB (typ) +0.5/−0.2 LSB (typ) 48 dB (typ) 7.6 bits (typ) −57 dB (typ) 5 Clock Cycles Guaranteed 0.65 mW/MSPS (typ) 1.0 mW (typ) Applications ■ ■ ■ ■ ■ ■ Digital Imaging Set-top boxes Portable Instrumentation Communication Systems X-ray imaging Viterbi decoders Pin Configuration 20041701 © 2008 National Semiconductor Corporation 200417 www.national.com ADC08L060 Ordering Information Order Number ADC08L060CIMT ADC08L060CIMTX ADC08L060EVAL Temperature Range −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +85°C Package TSSOP TSSOP (tape and reel) Evaluation Board Block Diagram 20041702 www.national.com 2 ADC08L060 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. Mid-point of the reference ladder. This pin should be bypassed to a quiet point in the analog ground plane with a 0.1 µF capacitor. Analog Input that is the low side (bottom) of the reference ladder of the ADC. Nominal range is 0.0V to (VRT – 0.5V). Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins hold the last conversion result. 9 VRM 10 VRB 23 PD 24 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the rising edge of CLK input. 13 thru 16 and 19 thru 22 D0–D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output after the rising edge of the CLK input. 7 VIN GND Reference ground for the single-ended analog input, VIN. Positive analog supply pin. Connect to a quiet voltage source of +3V. VA should be bypassed with a 0.1 µF ceramic chip capacitor for each pin, plus one 10 µF capacitor. See Section 3.0 for more information. Power supply for the output drivers. If connected to VA, decouple well from VA. The ground return for the output driver supply. The ground return for the analog supply. 1, 4, 12 VA 18 17 2, 5, 8, 11 VDR DR GND AGND 3 www.national.com ADC08L060 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA) Driver Supply Voltage (VDR) Voltage on Any Input or Output Pin Reference Voltage (VRT, VRB) CLK, PD Voltage Range Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temperature, Infrared, 10 seconds (Note 6) Storage Temperature 3.8V VA +0.3V −0.3V to VA VA to AGND −0.05V to (VA + 0.05V) ±25 mA ±50 mA See (Note 4)   2500V 200V 235°C −65°C to +150°C Operating Ratings Operating Temperature Range (Notes 1, 2) −40°C ≤ TA ≤ +85°C +2.4V to +3.6V +2.4V to VA 1.8V to VA 0V to 300 mV 0.5V to (VA −0.3V) 0V to (VRT −0.5V) VRB to VRT Supply Voltage, VA Driver Supply Voltage, VDR Output Driver Voltage, VDR Ground Difference |GND − DR GND| Upper Reference Voltage (VRT) Lower Reference Voltage (VRB) VIN Voltage Range Package Thermal Resistance Package 24-Lead TSSOP θJA 92°C/W Converter Electrical Characteristics The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (Notes 7, 8) Symbol DC ACCURACY INL DNL FSE VOFF Integral Non-Linearity Differential Non-Linearity Missing Codes Full Scale Error Zero Scale Offset Error 3.0 19 +0.5 −0.2 ±0.25 +1.9 −1.35 ±0.90 0 ±13 27 VRB VRT LSB (max) LSB (min) LSB (max) (max) mV (max) mV (max) V (min) V (max) pF pF MΩ MHz VA 0.5 VRT − 0.5 0 2.3 1.0 590 1070 1.5 2.7 V (max) V (min) V (max) V (min) V (max) V (min) Ω (min) Ω (max) mA (min) mA (max) Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN CIN RIN BW VRT VRB Input Voltage VIN Input Capacitance RIN Input Resistance Full Power Bandwidth Top Reference Voltage Bottom Reference Voltage VIN = 0.75V +0.5 Vrms (CLK LOW) (CLK HIGH) 1.6 3 4 >1 270 1.9 0.3 1.6 VRT to VRB VRT to VRB 720 2.2 VRT - VRB Reference Delta RREF Iref Reference Ladder Resistance Reference Ladder Current www.national.com 4 ADC08L060 Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) 2.0 0.8 Units (Limits) V (min) V (max) nA nA pF CLK, PD DIGITAL INPUT CHARACTERISTICS VIH VIL IIH IIL CIN VOH VOL Logical High Input Voltage Logical Low Input Voltage Logical High Input Current Logical Low Input Current Logic Input Capacitance High Level Output Voltage Low Level Output Voltage VA = VDR = 2.7V, IOH = −400 µA VA = VDR = 2.7V, IOL = 1.0 mA fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB fIN = 10.1 MHz, VIN = FS − 0.25 dB fIN = 29 MHz, VIN = FS − 0.25 dB f1 = 11 MHz, VIN = FS − 6.25 dB f2 = 12 MHz, VIN = FS − 6.25 dB DC Input fIN = 10 MHz, VIN = FS − 3 dB DC Input fIN = 10 MHz, VIN = FS − 3 dB DC Input IA + DRID Total Operating Current fIN = 10 MHz, VIN = FS − 3 dB, PD = Low CLK Low, PD = Hi DC Input PC Power Consumption fIN = 10 MHz, VIN = FS − 3 dB, PD = Low CLK Low, PD = Hi PSRR1 PSRR2 Power Supply Rejection Ratio Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in VA SNR reduction with 200 mV at 1MHz on supply VDR = VA = 3.6V VDR = VA = 2.7V VIH = VDR = VA = 3.6V VIL = 0V, VDR = VA = 2.7V 10 −50 3 2.6 0.4 7.6 7.4 47.4 46.1 48 47.2 59.1 54.5 −56.9 −53.3 -61.1 −54.9 −64.2 −63.1 −55 44.5 43.3 2.4 0.5 6.9 DIGITAL OUTPUT CHARACTERISTICS V (min) V (max) Bits (min) Bits dB (min) dB dB (min) dB dBc dBc dBc dBc dBc dBc dBc dBc dBc DYNAMIC PERFORMANCE ENOB SINAD SNR SFDR THD HD2 HD3 IMD Effective Number of Bits Signal-to-Noise & Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion 2nd Harmonic Distortion 3rd Harmonic Distortion Intermodulation Distortion POWER SUPPLY CHARACTERISTICS IA DRID Analog Supply Current Output Driver Supply Current 13 14 0.04 4.2 13 18.2 0.33 39 53 1 −51 45 48.3 16.1 0.2 15.9 mA (max) mA mA (max) mA mA (max) mA mA mW (max) mW mW dB dB 5 www.national.com ADC08L060 Symbol Parameter Conditions Typical (Note 9) 80 10 0.62 0.62 5 95 Limits (Note 9) 60 Units (Limits) MHz (min) MHz ns (min) ns (min) %(min) %(max) ns AC ELECTRICAL CHARACTERISTICS fC1 fC2 tCL tCH DC tOH tOD Maximum Conversion Rate Minimum Conversion Rate Minimum Clock Low Time Minimum Clock High Time Clock Duty Cycle Output Hold Time Output Delay Pipeline Delay (Latency) tAD tAJ Sampling (Aperture) Delay Aperture Jitter CLK Rise to Acquisition of Data CLK to Data Invalid CLK to Data Transition 5.2 7.1 5 2.6 2 5.0 9.4 ns (min) ns (max) Clock Cycles ns ps rms Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.8VDC to ensure accurate conversions. 20041707 Note 8: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1 + … + C71 x f7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the average frequency at which that pin is toggling. www.national.com 6 ADC08L060 Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes high. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 60 MSPS with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is defined as: Vmax + 1.5 LSB – VRT where Vmax is the voltage at which the transition to the maximum (full scale) code occurs. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. Measured at 60 MSPS with a ramp input. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is (VRT − VRB) / 2n where “n” is the ADC resolution, which is 8 in the case of the ADC08L060. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is pre- sented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the Output Delay. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC08L060, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected and is here defined as where SNR0 is the SNR measured with no noise or signal on the supply lines and SNR1 is the SNR measured with a 1 MHz, 200 mVP-P signal riding upon the supply lines. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below onehalf the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is defined as VOFF = VZT − VRB where VZT is the first code transition input voltage. 2nd HARMONIC DISTORTION (2nd HARM) is the difference, expressed in dB, between the rms power in the output fundamental frequency and the power in its 2nd harmonic at the output. 3rd HARMONIC DISTORTION (3rd HARM) is the difference, expressed in dB, between the rms power in the output fundamental frequency and the power in its 3rd harmonic at the output. 7 www.national.com ADC08L060 Timing Diagram 20041710 FIGURE 1. ADC08L060 Timing Diagram Typical Performance Characteristics stated INL VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise INL vs. Temperature 20041753 20041712 www.national.com 8 ADC08L060 INL vs. Supply Voltage, VA INL vs. Sample Rate 20041713 20041714 INL vs. Clock Duty Cycle DNL 20041715 20041754 DNL vs. Temperature DNL vs. Supply Voltage, VA 20041717 20041718 9 www.national.com ADC08L060 DNL vs. Sample Rate DNL vs. Clock Duty Cycle 20041719 20041720 SNR, SINAD and SFDR vs. Temperature SNR, SINAD and SFDR vs. Supply Voltage, VA 20041721 20041722 SNR, SINAD and SFDR vs. Sample Rate SNR, SINAD and SFDR vs. Input Frequency 20041723 20041724 www.national.com 10 ADC08L060 SNR, SINAD and SFDR vs. Clock Duty Cycle Distortion vs. Temperature 20041725 20041726 Distortion vs. Supply Voltage, VA Distortion vs. Sample Rate 20041727 20041728 Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle 20041729 20041730 11 www.national.com ADC08L060 Power Consumption (Active) vs. Sample Rate (fIN = d.c.) Power Consumption (Active) vs. Sample Rate (fIN = d.c.) 20041731 20041738 Power Consumption (Active) vs. Sample Rate (fIN = 1 MHz) Power Consumption (Active) vs. Sample Rate (fIN = 1 MHz) 20041739 20041740 Spectral Response @ fIN = 10 MHz Spectral Response @ fIN = 29 MHz 20041755 20041757 www.national.com 12 ADC08L060 Spectral Response @ fIN = 75 MHz Spectral Response @ fIN = 98.9 MHz 20041756 20041758 13 www.national.com ADC08L060 Functional Description The ADC08L060 uses a unique architecture that achieves over 7 effective bits at input frequencies up to and beyond Nyquist. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. Incorporating a switched capacitor bandgap, the ADC08L060 exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit needs. Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital outputs 5 clock cycles plus tOD later. The ADC08L060 will convert as long as an adequate clock signal is present at pin 24. The output coding is straight binary. The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode, where the output pins hold the last conversion before the PD pin went high and the device consumes about 1.4 mW. Holding the clock input low will further reduce the power consumption in the power down mode to about 1 mW Applications Information 1.0 REFERENCE INPUTS The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings table. Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin to keep these voltages stable. 20041732 FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for some applications. The reference bias circuit of Figure 2 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide reference voltage range. Better reference stability can be achieved by driving the reference pins with low impedance sources. The circuit of Figure 3 will allow a more accurate setting of the reference voltages. The upper amplifier must be able to source the reference current as determined by the value of the reference resistor and the value of (VRT - VRB). The lower amplifier must be able to sink this reference current. Both should be stable with a capacitive load. The LM8272 was www.national.com 14 chosen because of its rail-to-rail input and output capability, its high current output and its ability to drive large capacitance loads. Of course, the divider resistors at the amplifier input could be changed to suit your reference voltage needs, or the divider can be replaced with potentiometers for precise settings. The bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion is 0V. Be sure that the driving source can source sufficient current into the VRT pin and sink enough current from the VRB pin to keep these pins stable. ADC08L060 VRT should always be more positive than VRB by the minimum VRT - VRB difference in the Electrical Characteristics table to minimize noise. Furthermore, the difference between VRT and VRB should not exceed the maxumum value specified in the Electrical Characteristics table to avoid signal distortion. The VRM pin is the center of the reference ladder and should be bypassed to a quiet point in the analog ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float. 20041733 FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. 2.0 THE ANALOG INPUT The analog input of the ADC08L060 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of the analog input causes current spikes that result in voltage spikes at the analog input pin. Any circuit used to drive the analog input must be able to drive that input and to settle within the clock low time. The LMH6702 has been found to be a good amplifier to drive the ADC08L060. Figure 4 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 4. The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material. A resistor value should be chosen between 10Ω and 47Ω and the capacitor value chose according to the formula This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values are both zero. To optimize SINAD, reduce the capacitor value until SINAD performance is optimized. That is, until SNR = −THD. This value will usually be in the range of 20& to 65% of the value calculated with the above formula. An accurate calculation is not possible because of the board material and layout dependence. The circuit of Figure 4 has both gain and offset adjustments. If you eliminate these adjustments normal circuit tolerances may result in signal clipping unless care is exercised in the worst case analysis of component tolerances and the input signal excursion is appropriately limited to account for the worst case conditions. 15 www.national.com ADC08L060 20041734 FIGURE 4. The input amplifier should incorporate some gain for best performance (see text). 3.0 POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source is recommended for the VA and VDR supplies of the ADC08L060, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins. As is the case with all high speed converters, the ADC08L060 should be assumed to have little power supply rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other analog circuitry. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08L060 power pins. 4.0 THE DIGITAL INPUT PINS The ADC08L060 has two digital input pins: The PD pin and the Clock pin. 4.1 The PD Pin The Power Down (PD) pin, when high, puts the ADC08L060 into a low power mode where power consumption is reduced to 1.4 mW with the clock running, or to about 1 mW with the clock held low. Output data is valid and accurate about 1 microsecond after the PD pin is brought low. The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is high. 4.2 The ADC08L060 Clock Although the ADC08L060 is tested and its performance is guaranteed with a 60 MHz clock, it typically will function well with clock frequencies from 10 MHz to 80 MHz. 4.2.1 Clock Duty Cycle The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC08L060 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle and 60 Msps, ADC08L060 performance is typically maintained with clock high and low times of 0.83 ns, corresponding to a clock duty cycle range of 5% to 95% with a 60 MHz clock. Note that minimum low and high times may not be simultaneously asserted. 4.2.2 Clock Line Termination The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If the clock line is longer than www.national.com 16 ADC08L060 where tr is the clock rise time and tprop is the propagation rate of the signal along the trace. The CLOCK pin should be a.c. terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is where “L” is the line length in inches and ZO is the characteristic impedance of the clock line. Typical tPROP is about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes This termination should be located as close as possible to, but within one centimeter of, the ADC08L060 clock pin. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog and digital ground plane should be used. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. The DR GND connection to the ground plane should not use the same feedthrough used by other ground connections. High power digital components should not be located on or near a straight line between the ADC or any linear component and the power supply area as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC. Keeping analog and digital return (ground) currents separate from each other will improve system noise performance. Two methods may be used to do this. Use of traces rather than a solid plane to route power to all components will accomplish this because return currents follow the path of the outgoing currents. However, the advantage of the distributed capacitance of a power plane and a ground plane is lost. Analog and digital power should be routed as far from each other as is practical. The analog power trace should also be routed away from digital areas of the board. The use of power and ground planes in adjacent layers will provide distributed capacitance for a low impedance power distribution system and better system noise performance. The use of separate analog and digital power planes, both in the same PC board layer, and the use of a single, non-split ground plane will keep analog and digital currents separated from each other. Of course, locate all analog circuitry and traces over the analog power plane and the digital circuitry and traces over the digital power plane. To minimize RFI/EMI, give proper attention to any lines crossing the analog/digital power plane boundary. 17 Noise performance is also enhanced by driving a single gate with each ADC output pin and locating the gate as close as possible to the ADC output. Inserting a 47Ω resistor in series with the ADC digital output pins will also help reduce ADC noise. Be sure to keep the resistors as close to the ADC output pins as possible. Eliminating ground plane copper beneath the ADC output lines can also help ADC noise performance, but could produce unacceptable radiation from the board. Analog and digital circuitry should be kept well away from each other. Especially troublesome is high power digital components such as processors and large PLDs. Switch mode power supplies, including capacitive DC-DC converters, can cause noise problems with high speed ADCs. Keep such components well away from ADCs and low level analog signal areas. Such components should be located as close to the power supply as possible and should not be in the path of analog signal or power supply currents. Digital circuits create substantial supply and ground current transients. The noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one that employs non-saturating transistor designs, or has low noise characteristics, like the 74LS and the 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74HC, 74F and 74AC(T) families. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. 20041736 FIGURE 5. Layout Example The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the ground plane. www.national.com ADC08L060 Figure 5 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed together away from any digital components. 6.0 DYNAMIC PERFORMANCE The ADC08L060 is a.c. tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input should exhibit less than 10 ps (rms) of jitter. For best a.c. performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 6. It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the analog path. 20041737 FIGURE 6. Isolating the ADC Clock from Digital Circuitry 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC08L060. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 5 pF. Dynamic performance can also be improved by adding 100Ω series resistors at each digital output, reducing the energy coupled back into the converter input pins. Using an inadequate amplifier to drive the analog input. As explained in Section 2.0, the capacitance seen at the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in Section 1.0, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally inadequate as a clock source. www.national.com 18 ADC08L060 Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93. 24-Lead Package TC Order Number ADC08L060CIMT NS Package Number MTC24 19 www.national.com ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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