ADC1038

ADC1031 ADC1034 ADC1038 10-Bit Serial I O A D Converters with Analog Multiplexer and Track Hold Function January 1995 ADC1031 ADC1034 ADC1038 10-Bit Serial I O A D Converters with Analog Multiplexer and Track Hold Function General Description The ADC1031 ADC1034 and ADC1038 are 10-bit successive approximation A D converters with serial I O The serial input for the ADC1034 and ADC1038 controls a singleended analog multiplexer that selects one of 4 input channels (ADC1034) or one of 8 input channels (ADC1038) The ADC1034 and ADC1038 serial output data can be configured into a left- or right-justified format An input track hold is implemented by a capacitive reference ladder and sampled-data comparator This allows the analog input to vary during the A D conversion cycle Separate serial I O and conversion clock inputs are provided to facilitate the interface to various microprocessors Features Y Y Y Y Y Y Y Y Serial I O (MICROWIRETM compatible) Separate asynchronous converter clock and serial data I O clock Analog input track hold function Ratiometric or absolute voltage referencing No zero or full scale adjustment required 0V to 5V analog input range with single 5V power supply TTL MOS input output compatible No missing codes Resolution 10 bits g 1 LSB (max) Total unadjusted error Single supply 5V g 5% Power dissipation 20 mW (max) Max conversion time (fC e 3 MHz) 13 7 ms (max) Serial data exchange time (fS e 1 MHz) 10 ms (max) Key Specifications Y Y Y Y Y Y Applications Y Y Y Y Engine control Process control Instrumentation Test equipment TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRETM is a trademark of National Semiconductor Corporation Connection Diagrams Dual-In-Line and SO Packages TL H 10556–4 Top View ADC1031 In NS Package N08E TL H 10556 – 3 Top View ADC1034 In NS Packages J16A M16B or N16E TL H 10556 – 2 Top View ADC1038 In NS Packages J20A M20B or N20A Ordering Information Industrial b40 C s TA s a 85 C ADC1031CIN ADC1034CIN ADC1034CIWM ADC1038CIN ADC1038CIWM Military b55 C s TA s a 125 C ADC1034CMJ ADC1038CMJ Package N08E N16E M16B N20A M20B Package J16A J20A C1995 National Semiconductor Corporation TL H 10556 RRD-B30M75 Printed in U S A Absolute Maximum Ratings (Notes 1 3) Operating Ratings (Notes 2 Temperature Range ADC1031CIN ADC1034CIN ADC1034CIWM ADC1038CIN ADC1038CIWM ADC1034CMJ ADC1038CMJ Supply Voltage (VCC) Reference Voltage (VREF e VREF a b VREFb) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Inputs and Outputs Input Current at Any Pin (Note 4) Package Input Current (Note 4) Package Dissipation at TA e 25 C (Note 5) ESD Susceptability (Note 6) Soldering Information N Package (10 sec ) J Package (10 sec ) SO Package (Note 7) Vapor Phase (60 sec ) Infrared (15 sec ) Storage Temperature 6 5V b 0 3V to VCC a 0 3V g 5 mA g 20 mA 3) TMIN s TA s TMAX b 40 C s TA s a 85 C b 55 C s TA s a 125 C 4 75 VDC to 5 25 VDC 2 0 VDC to VCC a 0 05V 500 mW 2000V 260 C 300 C 215 C 220 C b 65 C to a 150 C Electrical Characteristics The following specifications apply for VCC e a 5 0V VREF e a 4 6V fS e 700 kHz and fC e 3 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol Parameter Conditions Typical (Note 8) Limit (Note 9) Units (Limits) CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error Differential Linearity RREF Reference Input Resistance 8 5 11 VREF VIN Reference Voltage Analog Input Voltage On Channel Leakage Current (Note 12) Off Channel Leakage Current (Note 12) Power Supply Sensitivity Zero Error Full Scale Error (Note 11) On Channel e 5 VDC Off Channel e 0 VDC On Channel e 0 VDC Off Channel e 5 VDC On Channel e 5 VDC Off Channel e 0 VDC On Channel e 0 VDC Off Channel e 5 VDC 4 75 VDC s VCC s 5 25 VDC 50 50 50 50 (VCC a 0 05) (VCC a 0 05) (GND b 0 05) 200 500 b 200 b 500 b 200 b 500 CIN CIWM CMJ (Note 10) g1 LSB (max) Bits (min) kX kX (min) kX (max) V (max) V (max) V (min) nA (max) nA (max) nA (max) nA (max) nA (max) nA (max) nA (max) nA (max) LSB (max) LSB (max) 10 200 500 g1 4 g1 4 2 Electrical Characteristics (Continued) The following specifications apply for VCC e a 5 0V VREF e a 4 6V fS e 700 kHz and fC e 3 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol Parameter Conditions Typical (Note 8) Limit (Note 9) Units (Limits) DIGITAL AND DC CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Logical ‘‘1’’ Output Voltage VCC e 5 25 VDC VCC e 4 75 VDC VIN e 5 0 VDC VIN e 0 VDC VCC e 4 75 VDC IOUT e b360 mA IOUT e b10 mA VCC e 4 75 VDC IOUT e 1 6 mA VOUT e 0V VOUT e 5V ISOURCE Output Source Current ISINK ICC Output Sink Current Supply Current VOUT e 0V VOUT e VCC CS e HIGH VREF Open b 0 01 20 08 0 005 b 0 005 V (min) V (max) mA (max) mA (max) V (min) V (min) V (max) mA (max) mA (max) mA (min) mA (min) mA (max) 25 b2 5 24 45 04 b3 VOUT(0) IOUT Logical ‘‘0’’ Output Voltage TRI-STATE Output Current 0 01 b 14 3 b6 5 16 15 80 3 AC CHARACTERISTICS fC fS Conversion Clock (CCLK) Frequency Serial Data Clock (SCLK) Frequency (Note 13) fC e 3 MHz R L e ‘‘0’’ fC e 3 MHz R L e ‘‘1’’ fC e 3 MHz R L e ‘‘0’’ or R L e ‘‘1’’ TC tCA tACC tSET-UP t1H t0H tHDI tSDI Conversion Time Analog Sampling Time Access Time Delay from CS or OE Falling Edge to DO Data Valid Set-up Time of CS Falling Edge to SCLK Rising Edge Delay from OE or CS Rising Edge to DO TRI-STATE DI Hold Time from SCLK Rising Edge DI Set-up Time to SCLK Rising Edge RL e 3 kX CL e 100 pF Not Including MUX Addressing and Analog Input Sampling Times After Address is Latched CS e Low OE e ‘‘0’’ 07 40 183 622 2 10 41 (1 fC) a 200 ns 4 5 (1 fS) a 200 ns 100 75 100 0 50 200 150 120 50 100 30 MHz (min) MHz (max) kHz (min) kHz (min) MHz (max) (max) (max) ns (max) ns (min) ns (max) ns (min) ns (min) 3 Electrical Characteristics (Continued) The following specifications apply for VCC e a 5 0V VREF e a 4 6V fS e 700 kHz and fC e 3 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol Parameter Conditions Typical (Note 8) Limit (Note 9) Units (Limits) AC CHARACTERISTICS (Continued) tHDO tDDO tRDO DO Hold Time from SCLK Falling Edge Delay from SCLK Falling Edge to DO Data Valid DO Rise Time RL e 30 kX CL e 100 pF RL e 30 kX CL e 100 pF RL e 30 kX CL e 100 pF RL e 30 kX CL e 100 pF TRI-STATE to High Low to High TRI-STATE to Low High to Low 70 150 35 75 35 75 50 75 10 250 75 150 75 150 ns (min) ns (max) ns (max) ns (max) ns (max) ns (max) pF pF tFDO DO Fall Time CIN Input Capacitance Analog Inputs (CH0 – CH7) All Other Inputs Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Note 2 Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 3 All voltages are measured with respect to AGND and DGND unless otherwise specified Note 4 When the input voltage (VIN) at any pin exceeds the power supplies (VIN k DGND or VIN l VCC) the current at that pin should be limited to 5 mA The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax iJA and the ambient temperature TA The maximum allowable power dissipation at any temperature is PD e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 125 C The typical thermal resistance (iJA) of these parts when board mounted follow ADC1031 with CIN suffixes 71 C W ADC1034 with CMJ suffixes 52 C W ADC1034 with CIN suffixes 54 C W ADC1034 with CIWM suffixes 70 C W ADC1038 with CMJ suffixes 53 C W ADC1038 with CIN suffixes 46 C W ADC1038 with CIWM suffixes 64 C W Note 6 Human body model 100 pF capacitor discharged through a 1 5 kX resistor Note 7 See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or Linear Databook section ‘‘Surface Mount’’ for other methods of soldering surface mount devices Note 8 Typicals are at TJ e 25 C and represent most likely parametric norm Note 9 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 10 Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors Note 11 Two on-chip diodes are tied to each analog input They will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause an input diode to conduct especially at elevated temperatures which will cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct Exceeding this range on an unselected channel will corrupt the reading of a selected channel To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading Note 12 Channel leakage current is measured after the channel selection Note 13 In order to synchronize the serial data exchange properly SARS needs to go low after completion of the serial I O data exchange If this does not occur the output shift register will be reset and the correct output data lost The minimum limit for SCLK will depend on CCLK frequency and whether right-justified or leftjustified and can be determined by the following equations fS l (8 5 41) (fC) with right-justification (R L e ‘‘1’’) and fS l (2 5 41) (fC) with left-justification (R L e ‘‘0’’) 4 Typical Performance Characteristics Power Supply Current (ICC) vs CCLK Power Supply Current (ICC) vs Ambient Temperature Reference Current (IREF) vs Ambient Temperature Linearity Error vs CCLK Frequency Linearity Error vs Ambient Temperature Linearity Error vs Reference Voltage Zero Error vs Reference Voltage TL H 10556 – 5 5 Test Circuits t1H t0H DO except ‘‘TRI-STATE’’ Leakage Current TL H 10556–6 TL H 10556 – 7 TL H 10556 – 8 Timing Diagrams DO High to Low State DO Low to High State DO ‘‘TRI-STATE’’ Rise and Fall Times TL H 10556–9 TL H 10556 – 10 TL H 10556 – 11 DI Data Input Timing DO Data Output Timing TL H 10556–12 TL H 10556 – 13 6 Timing Diagrams (Continued) ADC1031 CS High during Conversion TL H 10556 – 14 ADC1038 ADC1034 CS High during Conversion CCLK continuously enabled TL H 10556 – 15 7 Timing Diagrams (Continued) ADC1038 ADC1034 CS Low Continuously TL H 10556 – 16 CCLK continuously enabled Multiplexer Address Channel Assignment Tables ADC1038 MUX Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Analog Channel Selected CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ADC1034 MUX Address A2 X X X X Note ‘‘X’’ e don’t care A1 0 0 1 1 A0 0 1 0 1 Analog Channel Selected CH0 CH1 CH2 CH3 8 ADC1038 Functional Block Diagram 9 TL H 10556 – 17 1 0 Pin Descriptions CCLK The clock applied to this input controls the successive approximation conversion time interval The clock frequency applied to this input can be between 700 kHz and 4 MHz The serial data clock input The clock applied to this input controls the rate at which the serial data exchange occurs and the analog sampling time available to acquire an analog input voltage The rising edge loads the information on the DI pin into the multiplexer address shift register (address register) This address controls which channel of the analog input multiplexer (MUX) is selected The falling edge shifts the data resulting from the previous A D conversion out on DO CS and OE enable or disable the above functions The serial data input pin The data applied to this pin is shifted by SCLK into the multiplexer address register The first 3 bits of data (A0–A2) are the MUX channel address (see the Multiplexer Address Channel Assignment tables) The fourth bit (R L) determines the data format of the conversion result in the conversion to be started When R L is low the output data format is leftjustified when high it is right-justified When rightjustified six leading ‘‘0’’s are output on DO before the MSB information thus the complete conversion result is shifted out in 16 clock periods The data output pin The A D conversion result (D0 – D9) is output on this pin This result can be left- or right-justified depending on the value of R L bit shifted in on DI This pin is an output and indicates the status of the internal successive approximation register (SAR) When high it signals that the A D conversion is in progress This pin is set high after the analog input sampling time (tCA) and remains high for 41 CCLK periods When SARS goes low the output shift register has been loaded with the conversion result and another A D conversion sequence can be started The chip select pin When a low is applied to this pin the rising edge of SCLK shifts the data on DI into the address register In the ADC1031 this pin also functions as the OE pin The output enable pin When OE and CS are both low the falling edge of SCLK shifts out the previous A D conversion data on the DO pin The analog inputs of the MUX A channel input is selected by the address information at the DI pin which is loaded on the rising edge of SCLK into the address register Source impedances (RS) driving these inputs should be kept below 1 kX If RS is greater than 1 kX the sampled data comparator will not have enough time to acquire the correct value of the applied input voltage The voltage applied to these inputs should not exceed VCC or go below DGND or AGND by more than 50 mV Exceeding this range on an unselected channel will corrupt the reading of a selected channel VREF a The positive analog voltage reference for the analog inputs In order to maintain accuracy the voltage range of VREF (VREF e VREF a b VREFb) is 2 5 VDC to 5 0 VDC and the voltage at VREF a cannot exceed VCC a 50 mV In the ADC1031 VREFb is always GND The negative voltage reference for the analog inputs In order to maintain accuracy the voltage at this pin must not go below DGND and AGND by more than 50 mV or exceed 40% of VCC (for VCC e 5V VREF b (max) e 2V) In the ADC1031 VREFb is internally connected to the GND pin The power supply pin The operating voltage range of VCC is 4 75 VDC to 5 25 VDC VCC should be bypassed with 10 mF and 0 1 mF capacitors to digital ground for proper operation of the A D converter The digital and analog ground pins for the ADC1034 and the ADC1038 In order to maintain accuracy the voltage difference between these two pins must not exceed 300 mV The digital and analog ground pin for the ADC1031 SCLK VREFb VCC DI DGND AGND GND 2 0 Functional Description 2 1 DIGITAL INTERFACE The ADC1034 and ADC1038 implement their serial interface via seven digital control lines There are two clock inputs for the ADC1034 ADC1038 The SCLK controls the rate at which the serial data exchange occurs and the duration of the analog sampling time window The CCLK controls the conversion time and must be continuously enabled A low on CS enables the rising edge of SCLK to shift in the serial multiplexer addressing data on the DI pin The first three bits of this data select the analog input channel for the ADC1038 and the ADC1034 (see the Channel Addressing Tables) The following bit R L selects the output data format (right-justified or left-justified) for the conversion to be started With CS and OE low the DO pin is active (out of TRI-STATE) and the falling edge of SCLK shifts out the data from the previous analog conversion When the first conversion is started the data shifted out on DO is erroneous as it depends on the state of the Parallel Load 16-Bit Shift Register on power up which is unpredictable The ADC1031 implements its serial interface with only four control pins since it has only one analog input and comes in an eight pin mini-dip package The SCLK CCLK CS and DO pins are available for the serial interface The output data format cannot be selected and defaults to a left-justified format The state of DO is controlled by CS only 2 2 OUTPUT DATA FORMAT When R L is low the output data format is left-justified when high it is right-justified When right-justified six leading ‘‘0’’s are output on DO before the MSB and the complete conversion result is shifted out in 16 clock periods 2 3 0 CS HIGH DURING CONVERSION With a continuous SCLK input CS must be used to synchronize the serial data exchange A valid CS is recognized if it occurs at least 100 ns (tSET-UP) before the rising edge of SCLK thus causing data to be input on DI If this does not DO SARS CS OE CH0 – CH7 10 2 0 Functional Description (Continued) occur there will be an uncertainty as to which SCLK rising edge will clock in the first bit of data CS must remain low during the complete I O exchange Also OE needs to be low if data from the previous conversion needs to be accessed 2 3 1 CS LOW CONTINUOUSLY Another way to accomplish synchronous serial communication is to tie CS low continuously and use SARS and SCLK to synchronize the serial data exchange SCLK can be disabled low during the conversion time and enabled after SARS goes low With CS low during the conversion time a zero will remain on DO until the conversion is completed Once the conversion is complete the falling edge of SARS will shift out on DO the MSB before SCLK is enabled This MSB would be a leading zero if right-justified or D9 if left-justified The rest of the data will be shifted out once SCLK is enabled as discussed previously If CS goes high during the conversion sequence DO is put into TRI-STATE and the conversion result is not affected so long as CS remains high until the end of the conversion 2 4 TYING SCLK and CCLK TOGETHER SCLK and CCLK can be tied together The total conversion time will increase because the maximum clock frequency is now 1 MHz The timing diagrams and the serial I O exchange time (10 SCLK cycles) remain the same but the conversion time (TC e 41 CCLK cycles) lengthens from a minimum of 14 ms to a minimum of 41 ms In the case where CS is low continuously since the applied clock cannot be disabled SARS must be used to synchronize the data output on DO and initiate a new conversion The falling edge of SARS sends the MSB information out on DO The next rising edge of the clock shifts in MUX address bit A2 on DI The following clock falling edge will clock the next data bit of information out on DO A conversion will be started after MUX addressing information has been loaded in (3 more clocks) and the analog sampling time (4 5 clocks) has elapsed The ADC1031 does not have SARS Therefore CS cannot be left low continuously on the ADC1031 An acquisition window of 4 5 SCLK cycles is available to allow the ladder capacitance to settle to the analog input voltage Any change in the analog voltage before or after the acquisition window will not effect the A D conversion result In the most simple case the ladder’s acquisition time is determined by the Ron (9 kX) of the multiplexer switches the CS1 (3 5 pF) and the total ladder (CL) and stray (CS2) capacitance (48 pF) For large source resistance the analog input can be modeled as an RC network as shown in Figure 1 The values shown yield an acquisition time of about 3 ms for 10 bit accuracy with a zero to a full scale change in the reading External source resistance and capacitance will lengthen the acquisition time and should be accounted for The curve ‘‘Signal to Noise Ratio vs Output Frequency’’ (Figure 2) gives an indication of the usable bandwidth of the ADC1031 ADC1034 ADC1038 The signal to noise ratio of an ideal A D is the ratio of the RMS value of the full scale input signal amplitude to the value of the total error amplitude (including noise) caused by the transfer function of the A D An ideal 10 bit A D converter with a total unadjusted error of 0 LSB would have a signal to noise ratio of about 62 dB which can be derived from the equation S N e 6 02(N) a 1 8 where S N is in dB and N is the number of bits Figure 2 shows the signal to noise ratio vs input frequency of a typical ADC1031 4 8 with LSB total unadjusted error The dotted lines show signal-to-noise ratios for an ideal (noiseless) 10 bit A D with 0 LSB error and an A D with a 1 LSB error The sample-and-hold error specifications are included in the error and timing specifications of the A D The hold step and gain error sample hold specs are taken into account in the ADC1031 4 8’s total unadjusted error specification while the hold settling time is included in the A D’s maximum conversion time specification The hold droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the reading of data However once the data is read it is lost and another conversion is started 3 2 INPUT FILTERING Due to the sampling nature of the analog input transients will appear on the input pins They are caused by the ladder capacitance and internal stray capacitance charging current flowing into VIN These transients will not degrade the A D’s performance if they settle out within the sampling window This will occur if external source resistance is kept to a minimum 3 0 Analog Considerations 3 1 THE INPUT SAMPLE AND HOLD The ADC1031 4 8’s sample hold capacitor is implemented in its capacitive ladder structure After the channel address is received the ladder is switched to sample the proper analog input This sampling mode is maintained for 4 5 SCLK cycles after the multiplexer addressing information is loaded in For the ADC1031 4 8 the sampling of the analog input starts on SCLK’s 4th rising edge TL H 10556 – 18 FIGURE 1 Analog Input Model TL H 10556 – 19 FIGURE 2 ADC1031 4 8 Signal to Noise Ratio vs Input Frequency 11 3 0 Analog Considerations (Continued) External Reference 2 5V Full Scale Power Supply as Reference Input Not Referred to GND TL H 10556–20 TL H 10556 – 21 TL H 10556 – 22 Current path must still exist from VIN(b) to ground FIGURE 3 Analog Input Options 3 3 REFERENCE AND INPUT The two VREF inputs of the ADC1031 4 8 are fully differential and define the zero to full-scale input range of the A to D converter This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VREF a and VREFb By reducing VREF (VREF e VREF a b VREFb) to less than 5V the sensitivity of the converter can be increased (i e if VREF e 2V then 1 LSB e 1 95 mV) The input reference arrangement also facilitates ratiometric operation and in many cases the chip power supply can be used for transducer power as well as the VREF source This reference flexibility lets the input span not only be varied but also offset from zero The voltage at VREFb sets the input level which produces a digital output of all zeros Though VIN is not itself differential the reference design allows nearly differential-input capability for many measurement applications Figure 3 shows some of the configurations that are possible The ADC1031 has no VREFb pin VREFb is internally tied to GND Power Supply Bypassing TL H 10556–23 TL H 10556 – 24 12 Protecting the Analog Inputs TL H 10556 – 26 Diodes are IN914 TL H 10556 – 25 Zero-Shift and Span-Adjust (2V s VIN s 4 5V) 1% resistors TL H 10556 – 27 13 14 Physical Dimensions inches (millimeters) Order Number ADC1034CMJ NS Package Number J16A Order Number ADC1038CMJ NS Package Number J20A 15 Physical Dimensions inches (millimeters) (Continued) Order Number ADC1034CIWM NS Package Number M16B Order Number ADC1038CIWM NS Package Number M20B 16 Physical Dimensions inches (millimeters) (Continued) Order Number ADC1031CIN NS Package Number N08E Order Number ADC1034CIN NS Package Number N16E 17 ADC1031 ADC1034 ADC1038 10-Bit Serial I O A D Converters with Analog Multiplexer and Track Hold Function Physical Dimensions inches (millimeters) (Continued) Lit 101002 Order Number ADC1038CIN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications