ADC10D020EVAL

ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter April 2002 ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter General Description The ADC10D020 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 MSPS while consuming a typical 150 mW from a single 3.0V supply. No missing codes is guaranteed over the full operating temperature range. The unique two stage architecture achieves 9.5 Effective Bits over the entire Nyquist band at 20 MHz sample rate. An output formatting choice of straight binary or 2’s complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error. To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D020 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 27 mW and from which recovery is 800 ns. The ADC10D020’s speed, resolution and single supply operation makes it well suited for a variety of applications, including high speed portable applications. Operating over the industrial (−40˚ ≤ TA ≤ +85˚C) temperature range, the ADC10D020 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort. Features n n n n n n n n Internal sample-and-hold Internal reference capability Dual gain settings Offset correction Selectable straight binary or 2’s complement output Multiplexed or parallel output bus Single +2.7V to 3.6V operation Power down and standby modes Key Specifications Resolution 10 Bits Conversion Rate 20 MSPS ENOB 9.5 Bits (typ) DNL 0.35 LSB (typ) Conversion Latency Parallel Outputs 2.5 Clock Cycles — Multiplexed Outputs, I Data Bus 2.5 Clock Cycles — Multiplexed Outputs, Q Data Bus 3 Clock Cycles n PSRR 90 dB n Power Consumption — Normal Operation 150 mW (typ) < 1 mW (typ) — Power Down Mode — Fast Recovery Standby Mode 27 mW (typ) n n n n n Applications n n n n n n Digital Video CCD Imaging Portable Instrumentation Communications Medical Imaging Ultrasound © 2002 National Semiconductor Corporation DS200255 www.national.com ADC10D020 Connection Diagram 20025501 TOP VIEW Ordering Information Industrial Temperature Range (−40˚C ≤ TA ≤ +85˚C) ADC10D020CIVS ADC10D020EVAL NS Package TQFP Evaluation Board www.national.com 2 ADC10D020 Block Diagram 20025502 3 www.national.com ADC10D020 Pin Descriptions and Equivalent Circuits Pin No. 48 47 Symbol I+ I− Equivalent Circuit Description Analog inputs to “I” ADC. Nominal conversion range is 1.25V to 1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high. Analog inputs to “Q” ADC. Nominal conversion range is 1.25V to 1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high. 37 38 Q+ Q− 1 VREF Analog Reference Voltage input. The voltage at this pin should be in the range of 0.8V to 1.5V. With 1.0V at this pin and the GAIN pin low, the full scale differential inputs are 1 VP-P. With 1.0V at this pin and the GAIN pin high, the full scale differential inputs are 2 VP-P. This pin should be bypassed with a minimum 1 µF capacitor. 45 VCMO This is an analog output which can be used as a reference source and/or to set the common mode voltage of the input. It should be bypassed with a minimum of 1 µF low ESR capacitor in parallel with a 0.1 µF capacitor. This pin has a nominal output voltage of 1.5V and has a 1 mA output source capability. 43 VRP Top of the reference ladder. Do not drive this pin. Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor. 44 VRN Bottom of the reference ladder. Do not drive this pin. Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor. www.national.com 4 ADC10D020 Pin Descriptions and Equivalent Circuits Pin No. 33 Symbol CLK Equivalent Circuit (Continued) Description Digital clock input for both converters. The analog inputs are sampled on the falling edge of this clock input. Output Bus Select. With this pin at a logic high, both the “I” and the “Q” data are present on their respective 10-bit output buses (Parallel mode of operation). When this pin is at a logic low, the “I” and “Q” data are multiplexed onto the “I” output bus and the “Q” output lines all remain at a logic low (multiplexed mode). Offset Correct pin. A low-to-high transition on this pin initiates an independent offset correction sequence for each converter, which takes 34 clock cycles to complete. During this time 32 conversions are taken and averaged. The result is subtracted from subsequent conversions. Each input pair should have 0V differential value during this entire 34 clock period. Output Format pin. When this pin is LOW the output format is Straight Binary. When this pin is HIGH the output format is 2’s complement. This pin may be changed asynchronously, but this will result in errors for one or two conversions. Standby pin. The device operates normally with a logic low on this and the PD (Power Down) pin. With this pin at a logic high and the PD pin at a logic low, the device is in the standby mode where it consumes just 27 mW of power. It takes just 800 ns to come out of this mode after the STBY pin is brought low. Power Down pin that, when high, puts the converter into the Power Down mode where it consumes less than 1 mW of power. It takes less than 1 ms to recover from this mode after the PD pin is brought low. If both the STBY and PD pins are high simultaneously, the PD pin dominates. This pin sets the internal signal gain at the inputs to the ADCs. With this pin low the full scale differential input peak-to-peak signal is equal to VREF. With this pin high the full scale differential input peak-to-peak signal is equal to 2 x VREF. 3V TTL/CMOS-compatible Digital Output pins that provide the conversion results of the I and Q inputs. I0 and Q0 are the LSBs, I9 and Q9 are the MSBs. Valid data is present just after the rising edge of the CLK input in the Parallel mode. In the multiplexed mode, I-channel data is valid on I0 through I9 when the I/Q output is high and the Q-channel data is valid on I0 through I9 when the I/Q output is low. Output data valid signal. In the multiplexed mode, this pin transitions from low to high when the data bus transitions from Q-data to I-data, and from high to low when the data bus transitions from I-data to Q-data. In the Parallel mode, this pin transitions from low to high as the output data changes. Positive analog supply pin. This pin should be connected to a quiet voltage source of +2.7V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 2 OS 31 OC 32 OF 34 STBY 35 PD 36 GAIN 8 thru 27 I0–I9 and Q0–Q9 28 I/Q 40, 41 VA 5 www.national.com ADC10D020 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description 4 VD Digital supply pin. This pin should be connected to a quiet voltage source of +2.7V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. Digital output driver supply pins. These pins should be connected to a voltage source of +1.5V to VD and be bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. The ground return for the analog supply. AGND and DGND should be connected together close to the ADC10D020 package. The ground return for the digital supply. AGND and DGND should be connected together close to the ADC10D020 package. The ground return of the digital output drivers. 6, 30 VDR 3, 39, 42, 46 AGND 5 7, 29 DGND DR GND www.national.com 6 ADC10D020 Absolute Maximum Ratings 2) (Notes 1, Operating Ratings (Notes 1, 2) Operating Temperature Range VA, VD Supply Voltage VDR Supply Voltage VIN Differential Voltage Range GAIN = Low GAIN = High VCM Input Common Mode Range GAIN = Low GAIN = High VREF Voltage Range Digital Input Pins Voltage Range VREF/4 to (VA–VREF/4) VREF/2 to (VA–VREF/2) 0.8V to 1.5V −0.3V to (VA +0.3V) −40˚C ≤ TA ≤ +85˚C +2.7V to +3.6V +1.5V to VD If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltages Voltage on Any Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temperature, Infrared, 10 sec. (Note 6) Storage Temperature 2500V 250V 235˚C −65˚C to +150˚C 3.8V −0.3V to (VA or VD +0.3V) ± 25 mA ± 50 mA See (Note 4) ± VREF/2 ± VREF Converter Electrical Characteristics The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (ac coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) LSB(max) LSB(max) LSB(min) Bits LSB(max) LSB(min) LSB(max) LSB(min) %FS(max) %FS(min) Bits 9.0 Bits(min) Bits Bits dB 56 dB(min) dB dB dB 56 dB(min) dB dB dB −62 dB(min) dB dB STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity Differential Non-Linearity Resolution with No Missing Codes Without Offset Correction VOFF Offset Error With Offset Correction GE Gain Error +0.5 −4 −5 ± 0.65 ± 0.35 ± 1.8 +1.2 −1.0 10 +10 −16 +1.5 −0.5 +6 −14 DYNAMIC CONVERTER CHARACTERISTICS fIN = 1.0 MHz, VIN = FSR −0.1 dB ENOB Effective Number of Bits fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB SINAD Signal-to-Noise Plus Distortion Ratio fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB SNR Signal-to-Noise Ratio fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB THD Total Harmonic Distortion fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB 9.5 9.5 9.5 9.5 59 59 59 59 59 59 59 59 −73 −73 −73 −73 7 www.national.com ADC10D020 Converter Electrical Characteristics (Continued) The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (ac coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Parameter Conditions fIN = 1.0 MHz, VIN = FSR −0.1 dB Typical (Note 8) −84 −92 −87 −87 −80 −78 −78 −78 76 75 75 74 65 1023 0 140 1 MHz input to tested channel, 4.75 MHz input to other channel fIN = 8 MHz MHz Limits (Note 9) Units (Limits) dB dB dB dB dB dB dB dB dB dB dB dB dB Symbol HS2 Second Harmonic fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB fIN1 < 4.9 MHz, VIN = FSR −6.1 dB fIN2 < 5.1 MHz, VIN = FSR −6.1 dB (VIN+−VIN−) > 1.1V (VIN+−VIN−) < −1.1V HS3 Third Harmonic SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion Overrange Output Code Underrange Output Code FPBW Full Power Bandwidth INTER-CHANNEL CHARACTERISTICS Crosstalk Channel - Channel Aperture Delay Match Channel - Channel Gain Matching REFERENCE AND ANALOG CHARACTERISTICS VIN CIN RIN VREF IREF VCMO TC VCMO VIH VIL IIH IIL Analog Differential Input Range Analog Input Capacitance (each input) Analog Differential Input Resistance Reference Voltage Reference Input Current Common Mode Voltage Output Common Mode Voltage Temperature Coefficient Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current VD = +2.7V VD = +3.6V VIH = VD VIL = DGND 1 mA load to ground (sourcing current) Gain Pin = AGND Gain Pin = VA Clock High Clock Low 1 2 6 3 27 1.0 0.8 1.5 1.35 1.6 VP-P VP-P pF pF kΩ V(min) V(max) µA V(min) V(max) ppm/˚C −90 8.5 0.03 dB ps %FS