ADC10D1000_09

ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC November 19, 2009 ADC10D1000/ADC10D1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC 1.0 General Description The ADC10D1000/1500 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C. The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is guaranteed to have no missing codes over the full operating temperature range. Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes. 2.0 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Excellent accuracy and dynamic performance Low power consumption, further reduced at lower Fs Internally terminated, buffered, differential analog inputs R/W SPI Interface for Extended Control Mode Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate Test patterns at output for system debug Programmable 15-bit gain and 12-bit plus sign offset Programmable tAD adjust feature 1:1 non-demuxed or 1:2 demuxed LVDS outputs AutoSync feature for multi-chip systems Single 1.9V ± 0.1V power supply 292-ball BGA package (27mm x 27mm x 2.4mm with 1.27mm ball-pitch); no heat sink required LC sampling clock filter for jitter reduction 3.0 Key Specifications (Non-Demux Non-DES Mode, Fs=1.0/1.5 GSPS, Fin = 100 MHz) 10 Bits ■ Resolution ■ Conversion Rate — Dual channels at 1.0/1.5 GSPS (typ) — Single channel at 2.0/3.0 GSPS (typ) 10-18/10-18 (typ) ■ Code Error Rate 9.1/9.0 bits (typ) ■ ENOB 57/56.8 dB (typ) ■ SNR 70/68 dBc (typ) ■ SFDR 2.8/3.1 GHz (typ) ■ Full Power Bandwidth ±0.25/±0.25 LSB (typ) ■ DNL ■ Power Consumption 1.61/1.92W (typ) — Single Channel Enabled 2.77/3.59W (typ) — Dual Channels Enabled 6/6 mW (typ) — Power Down Mode 4.0 Applications ■ Wideband Communications ■ Data Acquisition Systems ■ Digital Oscilloscopes 5.0 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC10D1000/1500CIUT/NOPB ADC10D1000/1500CIUT ADC10D1000/1500RB NS Package Lead-free 292-Ball BGA Thermally Enhanced Package Leaded 292-Ball BGA Thermally Enhanced Package Reference Board If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Distributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/ ibis_models. © 2009 National Semiconductor Corporation 300663 www.national.com ADC10D1000/1500 6.0 Block Diagram 30066353 FIGURE 1. Simplified Block Diagram www.national.com 2 ADC10D1000/1500 Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Ordering Information ....................................................................................................................... 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Connection Diagram ........................................................................................................................ 6 8.0 Ball Descriptions and Equivalent Circuits ............................................................................................ 7 9.0 Absolute Maximum Ratings ............................................................................................................ 16 10.0 Operating Ratings ....................................................................................................................... 16 11.0 Converter Electrical Characteristics ................................................................................................ 16 12.0 Specification Definitions ................................................................................................................ 27 13.0 Transfer Characteristic ................................................................................................................. 29 14.0 Timing Diagrams ......................................................................................................................... 30 15.0 Typical Performance Plots ............................................................................................................ 33 16.0 Functional Description .................................................................................................................. 43 16.1 OVERVIEW ......................................................................................................................... 43 16.2 CONTROL MODES .............................................................................................................. 43 16.2.1 Non-Extended Control Mode ........................................................................................ 43 16.2.1.1 Dual Edge Sampling Pin (DES) ........................................................................... 43 16.2.1.2 Non-Demultiplexed Mode Pin (NDM) ................................................................... 43 16.2.1.3 Dual Data Rate Phase Pin (DDRPh) .................................................................... 44 16.2.1.4 Calibration Pin (CAL) ......................................................................................... 44 16.2.1.5 Calibration Delay Pin (CalDly) ............................................................................ 44 16.2.1.6 Power Down I-channel Pin (PDI) ......................................................................... 44 16.2.1.7 Power Down Q-channel Pin (PDQ) ...................................................................... 44 16.2.1.8 Test Pattern Mode Pin (TPM) ............................................................................. 44 16.2.1.9 Full-Scale Input Range Pin (FSR) ....................................................................... 44 16.2.1.10 AC/DC-Coupled Mode Pin (VCMO) ..................................................................... 44 16.2.1.11 LVDS Output Common-mode Pin (VBG) ............................................................. 44 16.2.2 Extended Control Mode ............................................................................................... 45 16.2.2.1 The Serial Interface ........................................................................................... 45 16.3 FEATURES ......................................................................................................................... 47 16.3.1 Input Control and Adjust .............................................................................................. 48 16.3.1.1 AC/DC-coupled Mode ........................................................................................ 48 16.3.1.2 Input Full-Scale Range Adjust ............................................................................ 48 16.3.1.3 Input Offset Adjust ............................................................................................ 48 16.3.1.4 DES/Non-DES Mode ......................................................................................... 48 16.3.1.5 Sampling Clock Phase Adjust ............................................................................. 48 16.3.1.6 LC Filter on Sampling Clock ............................................................................... 48 16.3.1.7 VCMO Adjust ..................................................................................................... 49 16.3.2 Output Control and Adjust ............................................................................................ 49 16.3.2.1 DDR Clock Phase ............................................................................................. 49 16.3.2.2 LVDS Output Differential Voltage ........................................................................ 49 16.3.2.3 LVDS Output Common-Mode Voltage ................................................................. 49 16.3.2.4 Output Formatting ............................................................................................. 49 16.3.2.5 Demux/Non-demux Mode .................................................................................. 49 16.3.2.6 Test Pattern Mode ............................................................................................ 49 16.3.3 Calibration Feature ..................................................................................................... 50 16.3.3.1 Calibration Control Pins and Bits ......................................................................... 50 16.3.3.2 How to Execute a Calibration .............................................................................. 50 16.3.3.3 Power-on Calibration ......................................................................................... 50 16.3.3.4 On-command Calibration ................................................................................... 51 16.3.3.5 Calibration Adjust .............................................................................................. 51 16.3.3.6 Read/Write Calibration Settings .......................................................................... 51 16.3.3.7 Calibration and Power-Down .............................................................................. 51 16.3.3.8 Calibration and the Digital Outputs ...................................................................... 51 16.3.4 Power Down .............................................................................................................. 51 17.0 Applications Information ............................................................................................................... 52 17.1 THE ANALOG INPUTS ......................................................................................................... 52 17.1.1 Acquiring the Input ...................................................................................................... 52 17.1.2 FSR and the Reference Voltage ................................................................................... 52 17.1.3 Out-Of-Range Indication .............................................................................................. 52 17.1.4 Maximum Input Range ................................................................................................ 52 3 www.national.com ADC10D1000/1500 17.1.5 AC-coupled Input Signals ............................................................................................ 17.1.6 DC-coupled Input Signals ............................................................................................ 17.1.7 Single-Ended Input Signals .......................................................................................... 17.2 THE CLOCK INPUTS ........................................................................................................... 17.2.1 CLK Coupling ............................................................................................................. 17.2.2 CLK Frequency .......................................................................................................... 17.2.3 CLK Level .................................................................................................................. 17.2.4 CLK Duty Cycle .......................................................................................................... 17.2.5 CLK Jitter .................................................................................................................. 17.2.6 CLK Layout ................................................................................................................ 17.3 THE LVDS OUTPUTS ........................................................................................................... 17.3.1 Common-mode and Differential Voltage ......................................................................... 17.3.2 Output Data Rate ........................................................................................................ 17.3.3 Terminating RSV Pins ................................................................................................. 17.3.4 Terminating Unused LVDS Output Pins ......................................................................... 17.4 SYNCHRONIZING MULTIPLE ADC10D1000/1500S IN A SYSTEM ............................................ 17.4.1 AutoSync Feature ....................................................................................................... 17.4.2 DCLK Reset Feature ................................................................................................... 17.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ................................. 17.5.1 Power Planes ............................................................................................................. 17.5.2 Bypass Capacitors ...................................................................................................... 17.5.3 Ground Planes ........................................................................................................... 17.5.4 Power System Example ............................................................................................... 17.5.5 Thermal Management ................................................................................................. 17.6 SYSTEM POWER-ON CONSIDERATIONS ............................................................................. 17.6.1 Power-on, Configuration, and Calibration ....................................................................... 17.6.2 Power-on and Data Clock (DCLK) ................................................................................. 17.7 RECOMMENDED SYSTEM CHIPS ........................................................................................ 17.7.1 Temperature Sensor ................................................................................................... 17.7.2 Clocking Device ......................................................................................................... 17.7.3 Amplifier .................................................................................................................... 18.0 Register Definitions ...................................................................................................................... 19.0 Physical Dimensions .................................................................................................................... 52 53 53 53 53 53 53 53 54 54 54 54 54 54 54 54 55 55 55 55 56 56 56 57 57 57 59 59 59 60 60 61 68 List of Figures FIGURE 1. Simplified Block Diagram ............................................................................................................. 2 FIGURE 2. ADC10D1000/1500 Connection Diagram ......................................................................................... 6 FIGURE 3. LVDS Output Signal Levels ......................................................................................................... 27 FIGURE 4. Input / Output Transfer Characteristic ............................................................................................ 29 FIGURE 5. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 30 FIGURE 6. Clocking in Non-Demux Non-DES Mode* ........................................................................................ 30 FIGURE 7. Clocking in 1:4 Demux DES Mode* ............................................................................................... 31 FIGURE 8. Clocking in Non-Demux Mode DES Mode* ...................................................................................... 31 FIGURE 9. Data Clock Reset Timing (Demux Mode) ........................................................................................ 32 FIGURE 10. Power-on and On-Command Calibration Timing .............................................................................. 32 FIGURE 11. Serial Interface Timing ............................................................................................................. 32 FIGURE 12. Serial Data Protocol - Read Operation .......................................................................................... 45 FIGURE 13. Serial Data Protocol - Write Operation .......................................................................................... 46 FIGURE 14. DDR DCLK-to-Data Phase Relationship ........................................................................................ 49 FIGURE 15. AC-coupled Differential Input ..................................................................................................... 53 FIGURE 16. Single-Ended to Differential Conversion Using a Balun ...................................................................... 53 FIGURE 17. Differential Input Clock Connection .............................................................................................. 53 FIGURE 18. RSV Pin Connection ................................................................................................................ 54 FIGURE 19. AutoSync Example ................................................................................................................. 55 FIGURE 20. Power and Grounding Example .................................................................................................. 56 FIGURE 21. HSBGA Conceptual Drawing ..................................................................................................... 57 FIGURE 22. Power-on with Control Pins set by Pull-up/down Resistors .................................................................. 58 FIGURE 23. Power-on with Control Pins set by FPGA pre Power-on Cal ................................................................ 58 FIGURE 24. Power-on with Control Pins set by FPGA post Power-on Cal ............................................................... 59 FIGURE 25. Supply and DCLK Ramping ....................................................................................................... 59 FIGURE 26. Typical Temperature Sensor Application ....................................................................................... 60 List of Tables TABLE 1. Analog Front-End and Clock Balls ................................................................................................... 7 TABLE 2. Control and Status Balls .............................................................................................................. 10 TABLE 3. Power and Ground Balls .............................................................................................................. 13 www.national.com 4 ADC10D1000/1500 TABLE 4. High-Speed Digital Outputs .......................................................................................................... TABLE 5. Package Thermal Resistance ........................................................................................................ TABLE 6. Static Converter Characteristics ..................................................................................................... TABLE 7. Dynamic Converter Characteristics ................................................................................................ TABLE 8. Analog Input/Output and Reference Characteristics ............................................................................. TABLE 9. I-Channel to Q-Channel Characteristics ............................................................................................ TABLE 10. Sampling Clock Characteristics ................................................................................................... TABLE 11. Digital Control and Output Pin Characteristics ................................................................................... TABLE 12. Power Supply Characteristics ...................................................................................................... TABLE 13. AC Electrical Characteristics ........................................................................................................ TABLE 14. Non-ECM Pin Summary ............................................................................................................. TABLE 15. Serial Interface Pins .................................................................................................................. TABLE 16. Command and Data Field Definitions ............................................................................................. TABLE 17. Features and Modes ................................................................................................................ TABLE 18. LC Filter Code vs. fc .................................................................................................................. TABLE 19. LC Filter Bandwidth vs. Level ....................................................................................................... TABLE 20. Test Pattern by Output Port in Demux Mode .................................................................................... TABLE 21. Test Pattern by Output Port in Non-Demux Mode .............................................................................. TABLE 22. Calibration Pins ....................................................................................................................... TABLE 23. Output Latency in Demux Mode ................................................................................................... TABLE 24. Output Latency in Non-Demux Mode ............................................................................................. TABLE 25. Unused AutoSync and DCLK Reset Pin Recommendation ................................................................... TABLE 26. Temperature Sensor Recommendation .......................................................................................... TABLE 27. Amplifier Recommendation ......................................................................................................... TABLE 28. Register Addresses .................................................................................................................. 14 16 16 17 20 21 21 22 23 24 43 45 45 47 49 49 50 50 50 52 52 55 59 60 61 5 www.national.com ADC10D1000/1500 7.0 Connection Diagram 30066301 FIGURE 2. ADC10D1000/1500 Connection Diagram The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 17.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS for more information. www.national.com 6 ADC10D1000/1500 8.0 Ball Descriptions and Equivalent Circuits TABLE 1. Analog Front-End and Clock Balls Ball No. Name Equivalent Circuit Description Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Qinput may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC-coupled Mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Qchannels have the same full-scale input range. In ECM, the full-scale input range of the I- and Qchannel inputs may be independently set via the Control Register (Addr: 3h and Addr: Bh). Note that the high and low full-scale input range setting in Non-ECM corresponds to the mid and minimum full-scale input range in ECM. The input offset may also be adjusted in ECM. H1/J1 N1/M1 VinI+/VinQ+/- U2/V1 CLK+/- Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled. V2/W1 DCLK_RST+/- Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC10D1000/1500s in order to synchronize them with other ADC10D1000/1500s in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. 7 www.national.com ADC10D1000/1500 Ball No. Name Equivalent Circuit Description Common Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing/ sinking up to 100 µA. For DC-coupled operation, this pin should be left floating or terminated into high-impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. Bandgap Voltage Output or LVDS Commonmode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing/sinking 100 uA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2V LVDS common-mode voltage is selected; 0.8V is the default. C2 VCMO B1 VBG C3/D3 Rext+/- External Reference Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used as a reference to trim internal circuits which affect the linearity of the converter; the value and precision of this resistor should not be compromised. C1/D2 Rtrim+/- Input Termination Trim Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100Ω input impedance of VinI, VinQ and CLK. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not guaranteed for such an alternate value. E2/F3 Tdiode+/- Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. It has not been fully characterized. www.national.com 8 ADC10D1000/1500 Ball No. Name Equivalent Circuit Description Y4/W5 RCLK+/- Reference Clock Input. When the AutoSync feature is active, and the ADC10D1000/1500 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM via Control Register (Addr: Eh). Y5/U6 V6/V7 RCOut1+/RCOut2+/- Reference Clock Output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in Master or Slave Mode. They are used to drive the RCLK of another ADC10D1000/1500, to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1 and RCOut2 to the RCLK of another ADC10D1000/1500 should be 100Ω differential. Having two clock outputs allows the autosynchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable/ disable this feature; default is disabled. 9 www.national.com ADC10D1000/1500 TABLE 2. Control and Status Balls Ball No. Name Equivalent Circuit Description Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, the DES Mode of operation is selected, meaning that the VinI input is sampled by both channels in a time-interleaved manner. The VinQ input is ignored. When this input is set to logic-low, the device is in Non-DES Mode, i.e. the I- and Q-channels operate independently. In the Extended Control Mode (ECM), this input is ignored and DES Mode selection is controlled through the Control Register by the DES Bit (Addr: 0h, Bit 7); default is Non-DES Mode operation. V5 DES V4 CalDly Calibration Delay select. By setting this input logic-high or logic-low, the user can select the device to wait a longer or shorter amount of time, respectively, before the automatic power-on selfcalibration is initiated. This feature is pincontrolled only and is always active during ECM and Non-ECM. D6 CAL Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. If this input is held high at the time of power-on, the automatic power-on calibration cycle is inhibited until this input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. B5 CalRun Calibration Running indication. This output is logic-high while the calibration sequence is executing. This output is logic-low otherwise. www.national.com 10 ADC10D1000/1500 Ball No. Name Equivalent Circuit Description Power Down I- and Q-channel. Setting either input to logic-high powers down the respective Ior Q-channel. Setting either input to logic-low brings the respective I- or Q-channel to a operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to powerdown the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. U3 V3 PDI PDQ A4 TPM Test Pattern Mode select. With this input at logichigh, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12). A5 NDM Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and NonECM. Y3 FSR W4 DDRPh Full-Scale input Range select. In Non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both Iand Q-channel inputs is set to the lower or higher FSR value, respectively. In the ECM, this input is ignored and the full-scale range of the I- and Qchannel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the high (lower) FSR value in NonECM corresponds to the mid (min) available selection in ECM; the FSR range in ECM is greater. DDR Phase select. This input, when logic-low, selects the 0° Data-to-DCLK phase relationship. When logic-high, it selects the 90° Data-to-DCLK phase relationship, i.e. the DCLK transition indicates the middle of the valid data outputs. This pin only has an effect when the chip is in 1:2 Demuxed Mode, i.e. the NDM pin is set to logiclow. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0° Mode. 11 www.national.com ADC10D1000/1500 Ball No. Name Equivalent Circuit Description Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this signal is de-asserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled via the control pins. B3 ECE C4 SCS Serial Chip Select bar. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data which is present on SDI and to source serial data on SDO. When this signal is deasserted (logic-high), SDI is ignored and SDO is in tri-stated. C5 SCLK Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logiclow, as long as timing specifications are not violated when the clock is enabled or disabled. B4 SDI Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). A3 SDO Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is tri-stated when SCS is de-asserted. D1, D7, E3, F4, W3, U7 C7 DNC NONE Do Not Connect. These pins are used for internal purposes and should not be connected, i.e. left floating. Do not ground. Not Connected. This pin is not bonded and may be left floating or connected to any potential. NC NONE www.national.com 12 ADC10D1000/1500 TABLE 3. Power and Ground Balls Ball No. A2, A6, B6, C6, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 A8, B9, C8, V8, W9, Y8 Name Equivalent Circuit Description Power Supply for the Analog circuitry. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply. VA NONE VTC NONE Power Supply for the Track-and-Hold and Clock circuitry. VDR NONE Power Supply for the Output Drivers. VE NONE Power Supply for the Digital Encoder. Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND. Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND. J4, K2 VbiasI NONE L2, M4 VbiasQ NONE A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20 A9, B8, C9, V9, W8, Y9 GND NONE Ground Return for the Analog circuitry. GNDTC NONE Ground Return for the Track-and-Hold and Clock circuitry. GNDDR NONE Ground Return for the Output Drivers. GNDE NONE Ground Return for the Digital Encoder. 13 www.national.com ADC10D1000/1500 TABLE 4. High-Speed Digital Outputs Ball No. Name Equivalent Circuit Description K19/K20 L19/L20 DCLKI+/DCLKQ+/- Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. K17/K18 L17/L18 ORI+/ORQ+/- Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the over- or under-range condition exists, i.e. the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current Data, with which it is clocked out. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. www.national.com 14 ADC10D1000/1500 Ball No. J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 V10/U10 Y10/W10 W19/W20 W18/V17 B19/B20 B18/C17 C10/D10 A10/B10 Name DI9+/DI8+/DI7+/DI6+/DI5+/DI4+/DI3+/DI2+/DI1+/DI0+/· DQ9+/DQ8+/DQ7+/DQ6+/DQ5+/DQ4+/DQ3+/DQ2+/DQ1+/DQ0+/DId9+/DId8+/DId7+/DId6+/DId5+/DId4+/DId3+/DId2+/DId1+/DId0+/· DQd9+/DQd8+/DQd7+/DQd6+/DQd5+/DQd4+/DQd3+/DQd2+/DQd1+/DQd0+/RSV7+/RSV6+/RSV5+/RSV4+/RSV3+/RSV2+/RSV1+/RSV0+/- Equivalent Circuit Description I- and Q-channel Digital Data Outputs. In NonDemux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, i.e. the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are tristated. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, i.e. the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. NONE Reserved. These pins are used for internal purposes. They may be left unconnected and floating or connected as recommended in Section 17.3.3 Terminating RSV Pins. 15 www.national.com ADC10D1000/1500 9.0 Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage (VA, VTC, VDR, VE) Supply Difference max(VA/TC/DR/E)min(VA/TC/DR/E) Voltage on Any Input Pin (except VIN+/-) VIN+/- Voltage Range Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) Input Current at Any Pin (Note 3) ADC10D1000 Package Power Dissipation at TA ≤ 85°C (Note 3) ADC10D1500 Package Power Dissipation at TA ≤ 70°C (Note 3) ESD Susceptibility (Note 4) Human Body Model Charged Device Model Machine Model Storage Temperature 2.2V 10.0 Operating Ratings (Note 1, Note 2) Ambient Temperature Range ADC10D1000 ADC10D1500 (Standard JEDEC thermal model) ADC10D1500 (Enhanced thermal model/heatsink) Junction Temperature Range Supply Voltage (VA, VTC, VE) Driver Supply Voltage (VDR) VIN+/- Voltage Range (Maintaining Common Mode) −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +70°C −40°C ≤ TA ≤ +85°C TJ ≤ +138°C +1.8V to +2.0V +1.8V to VA 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V to 100 mV −0.15V to (VA + 0.15V) -0.15V to 2.5V 0V to 100 mV ±50 mA 3.7 W 4.4 W   2500V 750V 250V −65°C to +150°C Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) CLK+/- Voltage Range Differential CLK Amplitude Common Mode Input Voltage 0V 0V to VA 0.4VP-P to 2.0VP-P VCMO - 150mV < VCMI < VCMO +150mV θJC1 θJC2 TABLE 5. Package Thermal Resistance Package θJA 292-Ball BGA Thermally 16°C/W Enhanced Package 2.9°C/W 2.5°C/W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 5) 11.0 Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = +1.9V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; CL = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, fCLK = 1.0/1.5 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Non-Extended Control Mode; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Note 6, Note 7, Note 8, Note 12) TABLE 6. Static Converter Characteristics Symbol Parameter Resolution with No Missing Codes INL DNL VOFF VOFF_ADJ PFSE NFSE Integral Non-Linearity (Best fit) Differential Non-Linearity Offset Error Input Offset Adjustment Range Positive Full-Scale Error Negative Full-Scale Error Extended Control Mode (Note 9) (Note 9) 1 MHz DC-coupled over-ranged sine wave 1 MHz DC-coupled over-ranged sine wave ±0.65 ±0.25 -2 ±45 ±25 ±25 1023 0 Conditions ADC10D1000 Typ Lim 10 ±1.4 ±0.5 ±0.65 ±0.25 -2 ±45 ±25 ±25 1023 0 ADC10D1500 Typ Lim 10 ±1.4 ±0.55 Units (Limits) bits LSB (max) LSB (max) LSB mV mV (max) mV (max) Out-of-Range Output Code (Note (VIN+) − (VIN−) > + Full Scale 10) (VIN+) − (VIN−) < − Full Scale www.national.com 16 ADC10D1000/1500 TABLE 7. Dynamic Converter Characteristics Symbol FPBW Parameter Full Power Bandwidth Conditions Non-DES Mode DES Mode DESIQ Mode Gain Flatness CER NPR Code Error Rate Noise Power Ratio fc,notch = 325 MHz, Notch width = 5% AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SINAD Signal-to-Noise Plus Distortion Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SNR Signal-to-Noise Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS THD Total Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 2nd Harm Second Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 3rd Harm Third Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SFDR Spurious-Free Dynamic Range AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 66 57.9 65 70 66 57.9 -69 -65 68 68 63 54 -70 -70 -71 -70 -68 -72 -63 -76 -71 -66 -60 -63 -76 -71 -71 -67 -69 -60 56.5 52.7 55 -65 -63 -60 -53.6 57 57 52.7 56 52 54.5 56.8 56.4 56.4 50 56.5 56.5 52 9.0 8.3 8.8 56.1 55.6 54.9 48.4 D.C. to Fs/2 D.C. to Fs ADC10D1000 Typ 2.8 1.25 2.15 ±0.35 ±0.5 10-18 48 Lim ADC10D1500 Typ 3.1 1.25 2.15 ±0.4 ±1.2 10-18 48 Lim Units (Limits) GHz GHz GHz dBFS dBFS Error/ Sample dB 1:2 Demux Non-DES Mode ENOB Effective Number of Bits 9.1 9.1 8.3 9.0 8.9 8.8 7.8 bits (min) bits (min) bits (min) bits (min) bits (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (max) dB (max) dB (max) dB (max) dB (max) dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc (min) dBc (min) dBc (min) dBc (min) dBc (min) 17 www.national.com ADC10D1000/1500 Symbol Parameter Conditions ADC10D1000 Typ 9.1 9.1 9.0 56.6 56.5 56 57 57 56.5 -67 -66 -66 -85 -71 -71 -68 -70 -70 68 66 66 59 57.9 -60 -60 53.5 52.7 52.6 52.0 8.4 8.3 Lim ADC10D1500 Typ 9.1 9.1 9.0 56.5 56.5 56 57 57 56.5 -67 -66 -66 -85 -71 -71 -68 -70 -70 68 66 66 Lim Units (Limits) bits (min) bits (min) bits (min) bits (min) bits (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (min) dB (max) dB (max) dB (max) dB (max) dB (max) dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc (min) dBc (min) dBc (min) dBc (min) dBc (min) Non-Demux Non-DES Mode (Fclk = 1GHz) (Note 12) ENOB Effective Number of Bits AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SINAD Signal-to-Noise Plus Distortion Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SNR Signal-to-Noise Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS THD Total Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 2nd Harm Second Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 3rd Harm Third Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SFDR Spurious-Free Dynamic Range AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS www.national.com 18 ADC10D1000/1500 Symbol Parameter Conditions ADC10D1000 Typ 8.6 8.5 8.4 Lim ADC10D1500 Typ 8.9 8.7 8.5 8.3 Lim Units (Limits) bits bits bits bits bits dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc DES Mode (Demux and Non-Demux Modes, Q-input only) ENOB Effective Number of Bits AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SINAD Signal-to-Noise Plus Distortion Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SNR Signal-to-Noise Ratio AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS THD Total Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 2nd Harm Second Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 3rd Harm Third Harmonic Distortion AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS SFDR Spurious-Free Dynamic Range AIN = 100 MHz @ -0.5 dBFS AIN = 248 MHz @ -0.5 dBFS AIN = 373 MHz @ -0.5 dBFS AIN = 498 MHz @ -0.5 dBFS AIN = 748 MHz @ -0.5 dBFS 57.4 59 59.3 58.9 -63 -62 67 62 60 -69 -65 -66 -70 -67 -70 -62 -77 -66 -63 -62 -80 -66 -64 -67 -64 52.7 52.1 -66 -62 -59 53.8 53.3 52.3 51.7 55.9 54.6 53.8 53.6 52.9 55.5 53.9 52.7 19 www.national.com ADC10D1000/1500 TABLE 8. Analog Input/Output and Reference Characteristics Symbol Analog Inputs VIN_FSR Analog Differential Input Full Scale Non-Extended Control Mode Range FSR Pin Low 600 660 FSR Pin High 790 860 Extended Control Mode FM(14:0) = 0000h FM(14:0) = 4000h (default) FM(14:0) = 7FFFh CIN Analog Input Capacitance, Non-DES Mode (Note 10) Analog Input Capacitance, DES Mode (Note 10) RIN Differential Input Resistance Differential Each input pin to ground Differential Each input pin to ground 600 790 980 0.02 1.6 0.08 2.2 100 96 104 1.15 1.35 600 790 980 0.02 1.6 0.08 2.2 100 93 107 1.15 1.35 mVP-P mVP-P mVP-P pF pF pF pF Ω (min) Ω (max) V (min) V (max) ppm/°C V 80 1.15 1.35 pF V (min) V (max) ppm/°C 80 pF 720 790 860 mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) Parameter Conditions ADC10D1000 Typ Lim ADC10D1500 Typ Lim Units (Limits) 540 600 540 660 720 Common Mode Output VCMO TC_VCMO VCMO_LVL CL_VCMO VBG TC_VBG CL_VBG Common Mode Output Voltage Common Mode Output Voltage Temperature Coefficient VCMO input threshold to set DC-coupling Mode Maximum VCMO Load Capacitance (Note 10) Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference load Capacitance IBG = ±100 µA IBG = ±100 µA (Note 10) ICMO = ±100 µA ICMO = ±100 µA 1.25 38 0.63 80 1.15 1.35 1.25 38 0.63 Bandgap Reference 1.25 32 80 1.25 32 www.national.com 20 ADC10D1000/1500 TABLE 9. I-Channel to Q-Channel Characteristics Symbol Parameter Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) X-TALK Zero offset selected in Control Register Zero offset selected in Control Register fIN = 1.0 GHz Conditions ADC10D1000 Typ 2 2 2