ADC10DV200CISQ

ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel Outputs February 5, 2009 ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs General Description The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single 1.8V power supply operation. Power scaling with clock frequency. Internal sample-and-hold. Internal or external reference. Power down mode. Offset binary or 2's complement output data format. LVDS or CMOS output signals. 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Clock Duty Cycle Stabilizer. IF Sampling Bandwidth > 900MHz. Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ ■ Resolution Conversion Rate ENOB SNR SINAD SFDR LVDS Power CMOS Power Operating Temp. Range 10 Bits 200 MSPS 9.6 bits (typ) @Fin=70MHz 59.9 dBFS (typ) @Fin=70MHz 59.9 dBFS (typ) @Fin=70MHz 82 dBFS (typ) @Fin=70MHz 450mW (typ) @Fs=200MSPS 280mW (typ) @Fs=170MSPS −40°C to +85°C. Applications ■ ■ ■ ■ Communications Medical Imaging Portable Instrumentation Digital Video Block Diagram 30082002 © 2009 National Semiconductor Corporation 300820 www.national.com ADC10DV200 Connection Diagram 30082001 Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) ADC10DV200CISQ ADC10DV200CISQE ADC10DV200EB Package 60 Pin LLP 60 Pin LLP, 250 pc. Tape and Reel Evaluation Board www.national.com 2 ADC10DV200 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 13 3 VINA+ VINB+ Differential analog input pins. The differential full-scale input signal level is 1.5VP-P with each input pin signal centered on a common mode voltage, VCM. Symbol Equivalent Circuit Description 14 2 VINAVINB- 10 6 11 5 VRPA VRPB VRMA VRMB VRNA VRNB 9 7 These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible. VRP and VRN should not be loaded. VRM may be loaded to 1mA for use as a temperature stable 0.9V reference. It is recommended to use VRM to provide the common mode voltage, VCM for the differential analog inputs. Reference Voltage select pin and external reference input. The relationship between the voltage on the pin and the reference voltage is as follows: The internal 0.75V reference is 1.4V ≤ VREF ≤ VA used. The external reference voltage is 0.2V ≤ VREF ≤ 1.4V used. Note: When using an external reference, be sure to bypass with a 0.1µF capacitor to AGND as close to the pin as possible. The internal 0.5V reference is AGND ≤ VREF ≤ 0.2V used. 17 VREF 19 REXT Programming resistor for analog bias current. Nominally a 3.3kΩ to AGND for 200MSPS, or tie to VA to use the internal frequency scaling current. 20 DF/DCS Data Format/Duty Cycle Correction selection pin. (see Table 1) 3 www.national.com ADC10DV200 Pin No. DIGITAL I/O Symbol Equivalent Circuit Description Clock input pins signal. The analog inputs are sampled on the rising edge of this signal. The clock can be configured for single-ended mode by shorting the CLK- pin to AGND. When in differential mode, the common mode voltage for the clock is internally set to 1.2V. 57 56 CLK + CLK - 36 53 PD_A PD_B Two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Two-state input controlling Output Mode. OUTSEL = VD, LVDS Output Mode. OUTSEL = AGND, CMOS Output Mode. 23 OUTSEL LVDS Output Mode 24, 25 26, 27 28, 29 32, 33 34, 35 39, 40 41, 42 43, 44 47, 48 49, 50 37 38 D0+,D0D1+, D1D2+, D2D3+, D3D4+, D4D5+, D5D6+, D6D7+, D7D8+, D8D9+, D9DRDY+ DRDYLVDS Output pairs for bits 0 through 9. A-channel and Bchannel digital LVDS outputs are interleaved. A channel is ready at rising edge of DRDY and B channel is ready at the falling edge of DRDY. Data Ready Strobe. This signal is a LVDS DDR clock used to capture the output data. A-channel data is valid on the rising edge of this signal and B-channel data is valid on the falling edge. ADC over-range Signal. This signals timing is formatted similarly to the data output signals. A channel is valid on DRDY rising and B channel is valid on DRDY falling. This signal will go high when the respective channel exceeds the allowable range of the ADC. Nominally this signal will be low. 51 52 OR+ OR- www.national.com 4 ADC10DV200 Pin No. CMOS Output Mode 24-29, 32-35 Symbol Equivalent Circuit Description Digital data output pins that make up the 10-bit conversion result for Channel A. DA0 (pin 24) is the LSB, while DA9 (pin 35) is the MSB of the output word. Output levels are CMOS compatible. Digital data output pins that make up the 10-bit conversion result for Channel B. DB0 (pin 39) is the LSB, while DB9 (pin 50) is the MSB of the output word. Output levels are CMOS compatible. Data Ready Strobe for channel A. This signal is used to clock the A-Channel output data. DRDYA is a SDR clock with same frequency as CLK rate and data is valid on the rising edges. Data Ready Strobe for channel B. This signal is used to clock the B-Channel output data. DRDYB is a SDR clock with same frequency as CLK rate and data is valid on the rising edges. Overrange indicator for channel A. A high on this pin indicates that the input exceeded the allowable range for the converter. Overrange indicator for channel B. A high on this pin indicates that the input exceeded the allowable range for the converter. Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. The ground return for the analog supply. Exposed pad must be soldered to AGND to ensure rated performance. Positive digital supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pin should be connected to the system digital ground. DA0-DA9 39-44, 47-50 DB0-DB9 37 DRDYA 38 DRDYB 51 52 ANALOG POWER 8, 16, 18, 59, 60 1, 4, 12, 15, 22, 55, 58, EP DIGITAL POWER 21, 54 ORA ORB VA AGND VD 31, 45 VDR 30, 46 DRGND TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response Voltage on DF/DCS Min 0 mV 250 mV 750 mV 1400mV Max 200mV 600 mV 1250 mV VA DF 1 0 1 0 DCS 1 0 0 1 2's complement data, duty cycle correction on Offset binary data, duty cycle correction off 2's complement data, duty cycle correction off Offset binary data, duty cycle correction on Tie to VA Tie to AGND Leave floating Results Suggestions 5 www.national.com ADC10DV200 Absolute Maximum Ratings (Notes 3, 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD VDR) Voltage on Any Pin (Not to exceed 2.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) Max Junction Temp (TJ) −0.3V to 2.2V −0.3V to (VA +0.3V) ±25 mA ±50 mA +150°C 30°C/W Operating Ratings Operating Temperature Supply Voltage (VA, VD, VDR) Clock Duty Cycle (DCS Enabled) (DCS disabled) VCM (Notes 1, 3) −40°C ≤ TA ≤ +85°C +1.7V to +1.9V 30/70 % 48/52 % 0.8V to 1.0V Thermal Resistance (θJA) ESD Rating (Note 6) Human Body Model 2500V Machine Model 250V Human Body Model 750V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 7) Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) 10 ±300 ±170 0.57 0.60 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +85°C 13 15 0.1 −40°C ≤ TA ≤ +85°C 4 0 1023 0 1023 1 0.85 V (min) V (max) V pF pF V V V 0.5 1.0 V (Min) V (max) +0.75 -0.75 ±920 ±430 3.11 2.72 Units (Limits) Bits (min) mLSB (max) mLSB (max) %FS (max) %FS (max) ppm/°C ppm/°C %FS (max) ppm/°C STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL PGE NGE Integral Non Linearity Differential Non Linearity Positive Gain Error Negative Gain Error TC PGE Positive Gain Error Tempco TC NGE Negative Gain Error Tempco VOFF Offset Error TC VOFF Offset Error Tempco Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VRM VCM CIN VRP VRN EXT VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to AGND) (Note 11) Internal Reference Top Internal Reference Bottom Internal Reference Accuracy External Reference Voltage (VRP-VRN) VIN = 0.75 Vdc ± 0.5 V (CLK LOW) (CLK HIGH) 0.9 0.9 1 2.5 1.33 0.55 0.78 www.national.com 6 ADC10DV200 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) MHz dBFS 59 70 9.48 -70 -70 58.9 dBFS (min) dBFS dBFS (min) Bits Bits (min) dBFS dBFS (min) dBFS dBFS (min) dBFS dBFS (min) dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR SFDR ENOB H2 H3 SINAD IMD Full Power Bandwidth (Note 16) Signal-to-Noise Ratio (Note 13) Spurious Free Dynamic Range (Note 14) Effective Number of Bits Second Harmonic Distortion Third Harmonic Distortion Signal-to-Noise and Distortion Ratio (Note 15) Intermodulation Distortion (Note 16) Cross Talk (Note 16) -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 10 MHz fIN = 70 MHz fIN = 10 MHz fIN = 70 MHz fIN = 10 MHz fIN = 70 MHz fIN = 10 MHz fIN = 70 MHz fIN = 10 MHz fIN = 70 MHz fIN1 = 69 MHz AIN1 = -7 dBFS fIN2 = 70 MHz AIN2 = -7 dBFS fIN1 = 69 MHz AIN1 = -1 dBFS fIN2 = 70MHz AIN2 = -1 dBFS 900 59.9 59.9 82 82 9.65 9.65 -94 -94 -85 -84 59.8 59.8 93 97 Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol LVDS OUTPUT MODE IA ID IDR Analog Supply Current Digital Supply Current Output Driver Supply Current Power Consumption Power Down Power Consumption CMOS OUTPUT MODE (Note 12) IA ID Analog Supply Current Digital Supply Current Power Consumption Power Down Power Consumption Full Operation, Internal Bias Full Operation, External 3.3kΩ Bias Full Operation Internal Bias External 3.3kΩ Bias PDA=PDB=VA 138 124 31 310 280 60 mA mA mW mW Internal Bias External 3.3kΩ Bias PDA=PDB=VA Full Operation, Internal Bias Full Operation, External 3.3kΩ Bias Full Operation 160 148 36 64 473 450 57 524 184 43 80 mA mA (max) mA (max) mA (max) mW mW (max) mW Parameter Conditions Typical (Note 10) Limits Units (Limits) 7 www.national.com ADC10DV200 Input/Output Logic Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA pF mVP-P 50 mV V 50 100 VDR = 1.8V (Unloaded) VDR = 1.8V (Unloaded) VOUT = 0V VOUT = VDR 1.8 0 -20 20 2 mV Ω V V mA mA pF DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B,OUTSEL) VIN(1) VIN(0) IIN(1) IIN(0) CIN VOD ±VOD VOS ±VOS RL VOH VOL +IOSC -IOSC COUT Logical “1” Input Voltage (Note 16) Logical “0” Input Voltage (Note 16) Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance LVDS differential output voltage Output Differential Voltage Unbalance LVDS common-mode output voltage (Note 16) Offset Voltage Unbalance Intended Load Resistance Logical "1" Output Voltage Logical "0" Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance (Note 16) VA = 1.9V VA = 1.7V VIN = 1.8V VIN = 0V 10.6 -7.6 2 330 0 1.25 0.89 0.67 LVDS OUTPUT CHARACTERISTICS (D0-D9,DRDY,OR) CMOS OUTPUT CHARACTERISTICS (DA0-DA9,DB0-DB9,DRDY,OR) (Note 12) Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol LVDS OUTPUT MODE Maximum Clock Frequency Minimum Clock Frequency tCH tCL tCONV tODA tODB tSU tH tAD tAJ tSKEW Clock High Time Clock Low Time Conversion Latency Output Delay of CLK to A-Channel Data Relative to rising edge of CLK Output Delay of CLK to B-Channel Data Relative to falling edge of CLK Data Output Setup Time Data Output Hold Time Aperture Delay Aperture Jitter Data-Data Skew Relative to DRDY Relative to DRDY 2.7 2.7 1.2 1.2 0.7 0.3 20 470 DCS On DCS Off DCS On DCS Off DCS On DCS Off 200 65 45 1.5 2.4 1.5 2.4 5/5.5 (A/B) 1.46 1.46 0.7 0.7 MHz (max) MHz (min) ns (min) ns (min) Clock Cycles ns (min) ns (min) ns (min) ns (min) ns ps rms ps Parameter Conditions Typical (Note 10) Limits Units (Limits) www.national.com 8 ADC10DV200 Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) MHz MHz ns ns Clock Cycles ns (min) ns (max) ns (min) ns (min) ns ps rms CMOS OUTPUT MODE (Notes 12, 16) Maximum Clock Frequency Minimum Clock Frequency tCH tCL tCONV tOD tSU tH tAD tAJ Conversion Latency Output Delay of CLK to DATA Data Output Setup Time(Note 16) Data Output Hold Time(Note 16) Aperture Delay Aperture Jitter Relative to falling edge of CLK Relative to DRDY Relative to DRDY 4.5 2.5 3.4 0.7 0.3 Clock High Time DCS On DCS Off DCS On DCS Off DCS On DCS Off 170 65 25 1.76 2.82 1.76 2.82 5.5 3.15 5.81 1.79 2.69 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: Units of dBFS indicates the value that would be attained with a full-scale input signal. Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10. Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 4). However, errors in the A/D conversion can occur if the input goes above VA or below AGND. 30082011 Note 9: With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV. Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance. Note 12: CMOS Specifications are for FCLK = 170 MHz. Note 13: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower. Note 14: SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower. Note 15: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower. Note 16: This parameter is guaranteed by design and/or characterization and is not tested in production. 9 www.national.com ADC10DV200 Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. The amount of SNR reduction can be calculated as SNR Reduction = 20 x log10[½ x π x ƒA x tj] CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition from code 511 to 512. OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the FullScale output of the ADC with the supply at the maximum DC supply limit, expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first six harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. www.national.com 10 ADC10DV200 Timing Diagrams 30082009 FIGURE 1. LVDS Output Timing 30082016 FIGURE 2. CMOS Output Timing 11 www.national.com ADC10DV200 Transfer Characteristic 30082010 FIGURE 3. Transfer Characteristic www.national.com 12 ADC10DV200 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS Enabled, LVDS Output, VCM = VRM, TA = 25°C. DNL INL 30082041 30082042 13 www.national.com ADC10DV200 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C. SNR, SINAD, SFDR vs. VA Distortion vs. VA 30082051 30082052 SNR, SINAD, SFDR vs. Temperature Distortion vs. Temperature 30082053 30082054 SNR, SINAD, SFDR vs. Clock Duty Cycle, fIN = 10MHz Distortion vs. Clock Duty Cycle, fIN = 10MHz 30082055 30082056 www.national.com 14 ADC10DV200 SNR, SINAD, SFDR vs. Ext. Reference Voltage Distortion vs. Ext. Reference Voltage 30082057 30082058 SNR, SINAD, SFDR vs. Clock Frequency Distortion vs. Clock Frequency 30082059 30082060 SNR, SINAD, SFDR vs. Ext. VCM Distortion vs. Ext. VCM 30082061 30082062 15 www.national.com ADC10DV200 Spectral Response @ 10 MHz Input Spectral Response @ 70 MHz Input 30082063 30082064 Spectral Response @ 170 MHz Input IMD, fIN1 = 69 MHz, fIN2 = 70 MHz 30082065 30082066 Total Power vs. Clock Frequency, fIN = 10 MHz 30082067 www.national.com 16 ADC10DV200 Functional Description Operating on a single +1.8V supply, the ADC10DV200 digitizes two differential analog input signals to 10 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user has the choice of using an internal 0.75V stable reference, or using an external 0.75V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty cycle stabilization and output data format are selectable using the quad state function DF/DCS pin (pin 20). The output data can be set for offset binary or two's complement. For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 1024 ( 1 - sin (90° + dev)) Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 5). For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Applications Information 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC10DV200: 1.7V ≤ VA ≤ 1.9V 1.7V ≤ VDR ≤ VA 45 MHz ≤ fCLK ≤ 200 MHz, with DCS off 65 MHz ≤ fCLK ≤ 200 MHz, with DCS on 0.75V internal reference VREF = 0.75V (for an external reference) VCM = 0.9V (from VRM) 2.0 ANALOG INPUTS 2.1 Signal Inputs 2.1.1 Differential Analog Input Pins The ADC10DV200 has a pair of analog signal input pins for each of two channels. V IN+ and VIN− form a differential input pair. The input signal, VIN, is defined as VIN = (VIN+) – (VIN−) Figure 4shows the expected input signal range. Note that the common mode input voltage, VCM, should be 0.9V. Using VRM (pins 5,11) for VCM will ensure the proper input common mode level for the analog input signal. The positive peaks of the individual input signals should each never exceed 2.2V. Each analog input pin of the differential pair should have a maximum peak-to-peak voltage of 1.5V, be 180° out of phase with each other and be centered around VCM.The peak-topeak voltage swing at each analog input pin should not exceed the 1V or the output data will be clipped. 30082081 FIGURE 5. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source impedance for the differential inputs will improve even ordered harmonic performance (particularly second harmonic). Table 2 indicates the input to output relationship of the ADC10DV200. 30082080 FIGURE 4. Expected Input Signal Range 17 www.national.com ADC10DV200 TABLE 2. Input to Output Relationship VIN+ VCM − VREF/2 VCM − VREF/4 VCM VCM + VREF/4 VCM + VREF/2 VIN− VCM + VREF/2 VCM + VREF/4 VCM VCM − VREF/4 VCM − VREF/2 Binary Output 00 0000 0000 01 0000 0000 10 0000 0000 11 0000 0000 11 1111 1111 2’s Complement Output 10 0000 0000 11 0000 0000 00 0000 0000 01 0000 0000 01 1111 1111 Positive Full-Scale Mid-Scale Negative Full-Scale 2.1.2 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC10DV200 have an internal sample-and-hold circuit which consists of an analog switch followed by a switched-capacitor amplifier. Figure 6 and Figure 7 show examples of single-ended to differential conversion circuits. The circuit in Figure 6 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 7 works well above 70MHz. 30082082 FIGURE 6. Low Input Frequency Transformer Drive Circuit 30082083 FIGURE 7. High Input Frequency Transformer Drive Circuit One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed to the ADC core. 2.1.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 0.8V to 1.0V and be a value such that the peak excursions of the analog signal do not go more negative than ground or more positive than the VA supply. It is recommended to use VRM (pins 5,11) as the input common mode voltage. If the ADC10DV200 is operated with VA=1.8V, a resistor of approximately 1K Ω should be used from the VRM pin to AGND. This will help maintain stability over the entire temperature range when using a high supply voltage. 2.2 Reference Pins The ADC10DV200 is designed to operate with an internal or external voltage reference. The voltage on the VREF pin selects the source and level of the reference voltage. An internal 0.75 Volt reference is used when a voltage between 1.4 V to VA is applied to the VREF pin. An internal 0.5 Volt reference is used when a voltage between 0.2V and AGND is applied to the VREF pin. If a voltage between 0.2V and 1.4V is applied to the VREF pin, then that voltage is used for the reference. SNR will improve without a significant degradation in SFDR for VREF=1.0V. SNR will decrease if VREF=0.5V, yet linearity will be maintained. If using an external reference the VREF pin should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The Reference Bypass Pins (VRP, VRM, and VRN) for channels A and B are made available for bypass purposes. These pins should each be bypassed to AGND with a low ESL (equivalent 18 www.national.com ADC10DV200 series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible. This configuration is shown in Figure 8. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. VRM may be loaded to 1mA for use as a temperature stable 0.9V reference. The remaining pins should not be loaded. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. Loading any of these pins, other than VRM may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VRM = 0.9 V VRP = 1.33 V VRN = 0.55 V 2.3 DF/DCS Pin Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate a stable internal clock, improving the performance of the part. See Table 1 for DF/ DCS voltage vs output format description. DCS mode of operation is limited to 65 MHz ≤ fCLK ≤ 200 MHz. 3.0 DIGITAL INPUTS Digital CMOS compatible inputs consist of CLK, PD_A, PD_B, and OUTSEL. 3.1 Clock Input The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. If the clock is interrupted, or its frequency is too low, the charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC clock pins only drive that pin. The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC10DV200 has a Duty Cycle Stabilizer. 4.0 DIGITAL OUTPUTS Digital outputs consist of the LVDS signals D0-D9, OR, and DRDY. The ADC10DV200 has 12 LVDS compatible data output pins: 10 data output pins corresponding to the converted input value, a data ready (DRDY) signal that should be used to capture the output data and an over-range indicator (OR) which is set high when the sample amplitude exceeds the 10-Bit conversion range. Valid data is present at these outputs while the PD pin is low. A-Channel data should be captured and latched with the rising edge of the DRDY signal and B-Channel data should be captured and latched with the falling edge of DRDY. To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can be achieved by keeping the PCB traces less than 2 inches long; longer traces are more susceptible to noise. The characteristic impedance of the LVDS traces should be 100Ω, and the effective capacitance < 10pF. Try to place the 100Ω termination resistor as close to the receiving circuit as possible. (See Figure 8) 19 www.national.com ADC10DV200 www.national.com 30082085 20 FIGURE 8. Application Circuit ADC10DV200 5.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor close to each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC10DV200 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. 21 www.national.com ADC10DV200 Physical Dimensions inches (millimeters) unless otherwise noted TOP View...............................SIDE View...............................BOTTOM View 60-Lead LLP Package Ordering Numbers: ADC10DV200CISQ NS Package Number SQA60A www.national.com 22 ADC10DV200 Notes 23 www.national.com ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel Outputs Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero SolarMagic™ Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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