ADC12D1XXX

Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature The AutoSync feature, new on National’s 10- and 12-bit GSPS ADC family, is capable of synchronizing the data at the output of multiple ADCs in a system. The novel architecture of this feature departs significantly from previous DCLK reset style solutions and has considerable advantages. National Semiconductor Application Note 2132 Marjorie Plisch May 10, 2011 This Applications Note covers an overview of synchronization, implementation of the feature, and FAQs. See Figure 1 for an example. For this Apps Note, "ADC" refers to the ADC12D1800/1600/1000 and the ADC10D1500/1000. 30154504 FIGURE 1. Synchronizing Multiple ADCs using AutoSync Overview of Synchronization THE GOAL: SYNCHRONIZING MULTIPLE ADCS The purpose of the AutoSync feature is to facilitate aligning the Data and DCLKs of multiple ADCs in a system, as illustrated in Figure 2. (1) when all ADCs in the system must sample multiple inputs at the same time and (2) when the ADCs in the system must sample the input with a known phase relationship with respect to one another. An example of the first case is a 4-channel oscilloscope which must simultaneously sample and display each analog input. For the second case, any system in which the ADCs are interleaved requires that their data output are aligned with a known phase relationship in order to correctly interleave the data in digital post-processing. In both cases, the inputs may be designed to arrive at each ADC with the desired relationship with respect to one another and the Sampling Clock may arrive at each ADC at the same time, but if the converted data at each ADC output has an unknown relationship with respect to the other ADC outputs, then the critical information which was carefully set up at analog inputs and Sampling Clocks, would be lost. THE PROBLEM: UNSYNCHRONIZED DCLKS It is not guaranteed by design whether the rising Sampling Clock edge which samples the data will generate a rising or falling DCLK transition when data appears at the output. For the Demux Mode, it is also not certain which one of two Sampling Clock edges will generate the DCLK (and Data). In order to completely synchronize the DCLKs, three requirements must be met: (1) the Sampling Clock must arrive to each ADC at the same instant; (2) each DCLK must be generated from the same edge of the Sampling Clock; (3) the phase of each DCLK must be the same. DCLK is generated from the Sampling Clock, which is why the Sampling Clock must arrive to each ADC at the same time. Any delta in the arrival of the Sampling Clocks translates to the same delta between DCLKs. For 1:2 Demux Mode, in which the output Data is produced on two 12-bit busses at half the non-demultiplexed rate, the DCLK runs at ¼ the rate of the Sampling Clock, a.k.a. www.national.com 30154501 FIGURE 2. Multiple ADCs in a System In general, this feature is useful in systems where the relationships of the analog inputs to each ADC, with respect to one another, must be known. The two most general cases are © 2011 National Semiconductor Corporation 301545 AN-2132 AN-2132 "FCLK". See Figure 3. When each ADC starts up, there is inherent uncertainty whether the DCLK will start up generated by the first edge of the Sampling Clock, (DCLK1 and DCLK3) or the second edge (DCLK2 and DCLK4) and whether DCLK will be rising (DCLK1 and DCLK2) or falling (DCLK3 and DCLK4). Since the DCLK is a subsample of the Sampling Clock by 4x, there are 4 possibilities for DCLK. THE SOLUTION: AUTOSYNC The AutoSync feature operates by configuring one ADC as the Master and all other ADCs as Slaves; the Slave DCLKs are synchronized to the Master DCLK. A Reference Clock, RCLK, runs from the Master ADC to Slave ADC(s) to control the phase of the Slave DCLKs, as shown in Figure 1. Each ADC may be configured as either a Master or a Slave; it is a Master by default. Each ADC can provide up to two Reference Clocks, RCOut1 and RCOut2 to control the phase of Slave ADCs. RCOut1 and RCOut2 are turned off by default; when enabled, they run at FCLK/4. During AutoSync system configuration, each RCLK is configured for a clean capture at each Slave ADC; the RCLK is used to select the correct one of four possible phases of DCLK. The Master and all Slave DCLKs must be observed, e.g., by an FPGA, in order to configure the AutoSync feature, as well as verify DCLK synchronization. It is only necessary to configure the AutoSync system for one unit; all other production units (with identical layout, RCLK trace / cable length, etc.) may be simply written with the same AutoSync settings. AutoSync provides significant advantages over previous DCLK reset style solutions: AutoSync The system can recover itself from a phase error. AutoSync is continuously active; any DCLK phase errors quickly propagate out of the system. DCLK Reset If the DCLK phase becomes in error, it is not possible to correct it except via another pulse because this method relies on a single pulse. 30154503 FIGURE 3. Unsynchronized DCLKs, Demux Mode For the Non-Demux Mode, the DCLK rate is ½ the Sampling Clock rate; therefore, there are two possibilities for DCLK. See Figure 4. No precise setup and hold Precise setup and hold times are required for RCLK times are required for the because it is generated by DCLK reset pulse. the ADC and configured in a control feedback loop. There is some flexibility in the system configuration. The Reference Clocks may be configured as a binary tree, daisy chain, or sourced independently. When one system is configured, these settings are valid for all production units. There is only one system configuration. The DCLK reset pulse must arrive at each ADC at the same time, similar to the Sampling Clock. Each unit must be synchronized via a pulse upon power-up. 30154517 FIGURE 4. Unsynchronized DCLKs, Non-Demux Mode Therefore, because the Data and associated DCLK of unsynchronized ADCs are not guaranteed to be generated at the same time or on the same phase of DCLK, the capture of the Data at the FPGA becomes a difficult task. The solution is to synchronize the DCLKs and Data, which removes any data capture difficulties at the FPGA, via the AutoSync feature. www.national.com 2 AN-2132 AutoSync Configurations AutoSync may be configured as a binary tree as in Figure 5, daisy chain as in Figure 6, or independently sourced as in Figure 7, depending upon system requirements. The daisy chain configuration is simply a special case of the binary tree. If RCLK is driven externally, then it must be derived from the Sampling Clock. 30154505 FIGURE 5. Binary Tree Configuration 30154506 FIGURE 6. Daisy Chain Configuration 30154507 FIGURE 7. Driving RCLK Externally 3 www.national.com AN-2132 Implementing AutoSync The key to implementing AutoSync correctly lies with guaranteeing that the Sampling Clock arrives to each ADC in the system at the same time, configuring the RCLK to each Slave ADC, and verifying that the synchronization has been correctly set up. IMPLEMENTING THE SAMPLING CLOCK Designing the Sampling Clock to arrive at each ADC at the same time is the most difficult part of implementing the AutoSync feature. It is necessary to accomplish this for two reasons; each analog input to ADC must be sampled at the same instant; and, the DCLK generated by each ADC must transition at the same time. For example, National's LMK01xxx family is ideal for clocking the ADC up to 1.6GHz and the LMK04xxx may be used for higher frequencies. Selecting a Clocking Chip A Sampling Clock generation or distribution chip should be selected for at least the following qualities: multiple differential outputs, low jitter and programmable output skew. Singleended outputs are not recommended; since the Sampling Clock which drives the ADC must be differential, a singleended to differential conversion stage can introduce unknown skew into the system. For example, a balun is commonly used for single-ended to differential conversion, but some baluns do not have a guaranteed phase relationship from input-tooutput. Simply selecting a clock generator with differential outputs will avoid these potential complications. Low jitter is necessarily a requirement for ultra high-speed ADCs, but this Applications Note will not cover extensive details regarding that topic. Another key is matching the traces from the clock generation chip to each ADC; traces should be well-matched between each +/- output as well as the length of each output pair to each ADC. Programmable output skew is a nice to have feature for tuning out any systematic skew on the board, but care must be taken when using this feature because adding delay typically also adds jitter. The ADC also has a feature for adjusting the incoming Sampling Clock, Sampling Clock Phase Adjust. When using the Sampling Clock Phase Adjust feature, it should be noted that this will also affect the timing of the DCLK. The effect of adjusting the incoming Sampling Clock also adjusts all clocks which are subsequently generated from it. For example, if the incoming Sampling Clock is delayed by Δt, then the DCLK as well as the Data is also delayed by Δt. Generating DCLK from the Sampling Clock From the rising edge of the Sampling Clock (FCLK in Figure 8), the DCLK edge transitions after a delay which is composed of three components; the latency, the Sampling Clock-to-data output delay, and the aperture delay. See Figure 8. The latency, tLAT, is the integer number of Sampling Clock cycles (or half cycles), guaranteed by design, which depends upon the Demux and DES Mode selection, for an analog sample to be converted into a digital value. The actual numbers are the same for all of the ADC and are available in the datasheet. The Sampling Clock-to-data output delay, tOD, is a fixed time delay in addition to the latency, independent of the Sampling Clock frequency, which is due to gate and parasitic delays. The Aperture Delay, tAD, is the amount of delay, measured from the sampling edge of the clock input, after which the signal present at the input pin is sampled inside the device. 30154508 FIGURE 8. DCLK Generation Timing If the same Sampling Clock arrives at each ADC at the same time, then the skew between DCLK transitions from ADC to ADC is only dependent upon tOD and tAD. These parameters are slightly different for the ADC10D1x00 and ADC12D1x00 families: ADC10D1x00 tOD tAD 2.4 ns (typ) 1.1 ns (typ) ADC12D1x00 3.2 ns (typ) 1.15 ns (typ) The routing for the Reference Clock does not have any stringent requirements, which is one of the advantages of the AutoSync feature. It is only necessary to match the length of the differential outputs to each other. In the case that the Slave ADC is on the same board, the trace may be any length; in the case that the Slave ADC is on a different board, the cable may be any length. The length of any Reference Clock trace / cable pair does not need to be the same length as any other pair. This is because the Reference Clock can be adjusted for clean capture at each Slave ADC. If the Slave Reference Clock is being driven by another ADC, then the trace / cable may be DC-coupled. The trace impedance should be 50Ω single-ended or 100Ω differential. For routing the Reference Clock from one board to another, a shielded, twisted-pair, 50Ω single-ended cable which is rated up to the RCLK frequency is sufficient. Some off the shelf examples include: USB2.0, USB3.0, Firewire, Display Port, HDMI, Ethernet/RJ-45 for CAT-5/6/7, PCI-Express, and SA- It is not possible for tOD and tAD to vary so much that they upset the AutoSync scheme. IMPLEMENTING THE REFERENCE CLOCK The Reference Clock must be routed from RCOut1/2 on the Master ADC to the RCLK on the Slave ADC and then configured. It is also possible to drive the Reference Clock externally. www.national.com 4 AN-2132 TA/SAS. An example of an automotive grade cable and connector with a locking mechanism is Rosenburger HSD. Configuring the Reference Clock The AutoSync configuration register from the ADC datasheet is provided below as a reference: Note that Bit 6 is different between the ADC10D1x00 and the ADC12D1x00. For the ADC10D1x00, Bit 6 is available as part of the DRC control bits and for the ADC12D1x00, Bit 6 is reserved. ADC10D1x00 AutoSync Register Addr: Eh (1110b) Bit Name POR 0 0 0 0 15 14 13 12 11 0 10 0 9 0 8 0 7 0 6 0 5 Res 0 4 0 3 0 DRC(9:0) SP(1:0) POR state: 0003h 2 ES 0 1 DOC 1 0 DR 1 ADC12D1x00 AutoSync Register Addr: Eh (1110b) Bit Name POR 0 0 0 0 15 14 13 12 11 DRC(8:0) 0 0 0 0 0 0 10 9 8 7 6 Res 0 5 4 0 3 0 SP(1:0) POR state: 0003h 2 ES 0 1 DOC 1 0 DR 1 ADC10D1x00 Bits 15:6 DRC(9:0): Delay Reference Clock. These bits may be used to increase the delay on the input Reference Clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1200 ps (639d). The delay remains the maximum of 1200 ps for any codes above or equal to 639d. Each bit equates to approximately 1.9 ps delay. ADC12D1x00 Bits 15:7 DRC(8:0): Delay Reference Clock. These bits may be used to increase the delay on the input Reference Clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1200 ps (319d). The delay remains the maximum of 1200 ps for any codes above or equal to 319d. Each bit equates to approximately 3.8 ps delay. Bit 6 Reserved. Must be set as shown. ADC10D1x00 / ADC12D1x00 Bit 5 Reserved. Must be set as shown. Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the Reference Clock which is latched. The codes correspond to the following phase shift: 00b = 0°; 01b =90°; 10b = 180°; 11b = 270° Bit 2 ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are synchronized with the Reference Clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this bit is set to 0b, then the devices is in Master Mode. Bit 1 DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the devices is operating in Master or Slave Mode, as determined by ES (Bit 2). Bit 0 DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality. FIGURE 9. ADC AutoSync Register Step #1 - Configure the ADC into Master / Slave Mode Configuring the ADC into Master / Slave is accomplished via Bit 2 (Enable Slave). By default, each ADC is configured as a Master, so that it is generating its own unsynchronized DCLK. Each ADC whose DCLK will be synchronized to another DCLK should be configured into Slave Mode. For a system which is configured as either a binary tree or daisy chain, there will be one ADC in Master Mode and the rest of the ADCs will be in Slave Mode. Generally, for a system in which RCLK is driven externally, all ADCs will be in Slave Mode. In this case, the DCLK of any one of the ADCs should be designated as a reference, similar to the Master ADC, to which the phase of the other ADCs will be synchronized. Step #2 - Enable the Reference Clocks Enabling / disabling the output Reference Clocks is accomplished via Bit 1 (Disable Output reference Clocks). Leaving the Reference Clocks disabled will save a small amount of power and reduce any spurious energy at that frequency, so it is generally recommended to leave the output Reference Clocks disabled if they are not used. Both Reference Clocks are enabled / disabled together; it is not possible to enable just one or the other. 5 www.national.com AN-2132 Step #3 - Adjust each Slave ADC's Reference Clock for a clean capture The incoming Reference Clock to each ADC may be delayed by using the Delay Reference Clock (DRC) Bits. As the Reference Clock is delayed by increasing DRC from 0 to the maximum code, the behavior of the Slave ADC's DCLK will change. An example is shown in Figure 10. The codes in certain regions will provide a stable DCLK output, as shown by the regions labeled: "DCLK", "DCLK + 90°", and "DCLK + 180°". The codes in the shaded region will not produce a stable DCLK output; instead, DCLK will generally be logic-high in the unstable region. There may also be 1 or 2 codes on the border of the stable / unstable region which produce an intermittent DCLK. As the codes increase from 0 to the max code, the DCLK produced will be 90° delayed as compared to the DCLK produced in the previous stable region. The DRC code should be set to the center of the widest available stable region, as indicated by the arrow in the center of the "DCLK + 90°" region in Figure 10. At this step, due to the nature of the AutoSync feature, it is not actually relevant what the phase of the Slave DCLK is (as compared to the Master / Reference DCLK), only that the DCLK is generated by selecting a DRC code in the center of the stable region. Therefore, the length of trace or cable from where RCLK is generated to each Slave ADC may be any length. The minimum code of DRC = 0d translates to a delay of 0 ps and the maximum code translates to a delay of 1200 ps for both the ADC10D1x00 and the ADC12D1x00. The amount of delay scales linearly with the code. Therefore, the code in the center of the stable region will be the average value of the codes which trigger the start of the unstable region on either side of the stable region. The delay is an absolute amount of time and is not related to the Sample Clock frequency. A faster Sample Clock frequency and, consequently, faster RCLK, will result in more transitions from stable to unstable region (and vice versa) over the full range of codes. Step #4 - Select the correct DCLK phase for each Slave ADC to match the Master DCLK phase The phase of the Slave DCLK can be adjusted to match that of the Master DCLK using Bits 4:3 (Select Phase). There are only four possible settings: 0°, 90°, 180°, and 270°. Select the phase which matches the Master DCLK, e.g. SP = 01b as shown in Figure 11. The phase shifted DCLK for the other three SP codes are also shown on the same plot. 30154513 FIGURE 10. DRC Code vs. DCLK Behavior 30154515 FIGURE 11. Slave DCLK vs. SP Selection www.national.com 6 AN-2132 Driving the Reference Clock Externally Depending upon what architecture is most convenient for the system, it is also possible to drive the Reference Clocks externally. There are two options; in either case, the RCLK must be derived from the Sampling Clock so that it runs at precisely the same frequency as the DCLK. In the first case, one clock generation and distribution chip can drive all the Slave ADC Sampling Clocks and Reference Clocks, as in Figure 7. In the second case, the Reference Clock from one Master ADC is distributed to the Slave ADCs, e.g. National's LMK01000, as in Figure 12. IMPLEMENTING THE DCLK Since the DCLKs must be synchronized when they reach the FPGA, the DCLK routing from each ADC to the FPGA should be matched in length. If the ADCs are mounted on separate boards, then it is a system-level design challenge to match the DCLK routing to the FPGA. Alternately, the data captured at each FPGA may be synchronized at a different levels in the system. It is strongly recommended to add probe points on each DCLK, at the same distance from each ADC DCLK output to each probe point. This will enable verification of AutoSync via an oscilloscope during the process of system debug if the FPGA does not initially work to accomplish this. 30154516 FIGURE 12. RCLK Distribution and External Drive The Equivalent Circuit for RCLK is shown in Figure 13. When driving RCLK externally, it must be done differentially. It should be AC-coupled, as the input buffer will create its own bias internally. The differential RCLK should have Vpp > 250mV. The maximum limits are given in the datasheet. RCLK, as generated by the ADC, has the same characteristics as the DCLK: it is a square wave with duty-cycle 50% and frequency FCLK/4. RCLK may not be a pulse. 30154518 FIGURE 14. AutoSync Closed Loop Configuration 30154512 FIGURE 13. RCLK Equivalent Circuit 7 www.national.com AN-2132 Frequently Asked Questions 1. How should unused I/O on the AutoSync and DCLK reset features be terminated? TABLE 1. Unused Synchronization Pin Recommendation Pin(s) RCLK+/RCOUT1+/RCOUT2+/DCLK_RST+ DCLK_RSTUnused termination Do not connect. Do not connect. Do not connect. Connect to GND via 1kΩ resistor. Connect to VA via 1kΩ resistor. 2. Is it okay to drive the RCLK on a Slave ADC which is powered down? Driving the RCLK of an ADC which is not powered on will activate the ESD diodes of each RCLK+/- input. In order to achieve the maximum lifetime of the product, it is not recommended to do this. The Reference Clocks of an upstream ADC, RCOut1 and RCOut2, may be turned on or off via the Configuration Register (Addr: Eh, Bit 1). For system operation, all ADCs should be first powered up, and then the Slave ADCs may be safely driven with RCLK. 3. What happens to DCLK if the Slave ADC loses its RCLK? An ADC in Slave Mode which receives no RCLK will produce a static logic level at its DCLK output; DCLK will not transition. The AutoSync feature cannot be turned on or off, but rather, the ADC is configured into either Master Mode or Slave Mode. If the ADC is in Master Mode, then it is not synchronized to any other ADCs. If it is in Slave Mode, then it must receive a RCLK signal else it produces no DCLK. 4. Is it necessary to synchronize DCLKI and DCLKQ? By design, the DCLKI and DCLKQ from each ADC are phase aligned with respect to one another; no additional effort is required to align them. For this reason, either DCLKI or DCLKQ may be used to capture data by the FPGA. Which DCLK is selected may simply be a matter of which is more convenient from a layout perspective. The other DCLK may be used as a system clock or left unused. As long as the ADC is receiving power and a Sampling Clock, and the channel is not powereddown (set via PDI or PDQ), and either configured in Master Mode or configured in Slave Mode and properly receiving an RCLK signal, then that channel will generate a DCLK. In the description and conceptual block diagrams, DCLK1, DCLK2, etc. always refers to the DCLKs from ADC1, ADC2, etc. and not to DCLKI and DCLKQ. 5. What is the phase relationship between RCLK and DCLK? This relationship is uncharacterized because it is not essential to the functionality of the AutoSync feature. RCLK is configured empirically at each Slave ADC. 6. How can it be verified that the AutoSync system was correctly implemented? The DCLKs from all ADC must be monitored, at least to configure the AutoSync feature, e.g. via an FPGA or oscilloscope. In the case of an oscilloscope, it is a good idea to plan for probe points on each ADC DCLK. Once the feature is configured, then if all DCLKs are on the same phase, then the feature has been correctly implemented. An exception to this is the setting of DRC; it is possible to choose a code for DRC which is not maximally ideal, i.e. not centered in the stable region, and the feature will still function. 7. Can the Test Pattern Mode be used to verify the AutoSync configuration? No. The Test Pattern Mode (TPM) does not start up in a synchronized manner. Therefore, it is possible the multiple ADCs in the system are synchronized, but the output of their Test Pattern Modes may not be. 8. Can tOD and tAD vary enough over voltage, temperature, and process to disrupt the AutoSync system? From simulation, the largest expected variation is as follows: • tOD and tAD vs. Temperature: +8% / -12% • tOD and tAD vs. Supply: +5% / -5% • tOD and tAD vs. Process: +23% / -15% • tOD and tAD vs. Composite PVT: +30% / -30% tOD and tAD variance do not actually affect the AutoSync system. If the DRC code selection places the Reference Clock in the center of a stable region, then the system is robust enough that PVT variation cannot disrupt the AutoSync scheme. 9. Can RCLK shift enough over temperature to shift the DCLK phase? If the AutoSync feature has been correctly implemented, then this cannot happen. However, if DRC is not placed in the middle of a stable region, but instead is placed close to an unstable region boundary, then it is possible that the Reference Clock could shift enough over temperature to cross the boundary into the unstable region and disrupt the correct DCLK phase. 10. Does AutoSync have any limitations? AutoSync relies on the Sampling Clock arriving to each ADC at the same time. If this timing is too seriously compromised, the AutoSync feature is not able to compensate for it. Although AutoSync is very convenient to use because the RCLK trace / cable may be any length, it is still necessary to monitor each Slave DCLK as compared to the Master / Reference DCLK while configuring the feature. In the case that the ADCs to be synchronized are located on multiple boards, it is a system design challenge to guarantee that each DCLK is routed back to a single FPGA with minimal skew for comparison. 11. Is RCLK FCLK/4 for both Demux and Non-Demux Mode? Yes. 12. How is the DDR Clock Phase related to AutoSync? Should it be configured before or after AutoSync is configured? All ADCs in the system should be configured in the same DDR Clock Phase, either 0° or 90°. Theoretically, it should make no difference to AutoSync if the DDR Phase is set before or after AutoSync is configured. Practically, it is more reasonable to configure the DDR Phase before configuring AutoSync. 13. Is the order of AutoSync setting configuration important for the Slave ADCs? Yes, it is important for topologies in which the Slave ADCs receive their RCLK from an upstream ADC. For such topologies, the Slave ADCs should be configured starting from the Master ADC and progressing to each downstream Slave ADC in order. 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