ADC12DL080EVAL

ADC12DL080 Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling February 2006 ADC12DL080 Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling General Description The ADC12DL080 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 600 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC12DL080 achieves 11.0 effective bits at Nyquist and consumes just 447mW at 80 MSPS. The Power Down feature reduces power consumption to 50 mW. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a singleended input. Full use of the differential input is recommended for optimum performance. Duty cycle stabilization and output data format are selectable. The output data can be set for offset binary or two’s complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL080 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Features n n n n n n n Single +3.3V supply operation Internal sample-and-hold Internal or External reference Outputs 2.4V to 3.6V compatible Power down mode Duty Cycle Stabilizer Pin compatible with ADC12DL040, ADC12DL065, ADC12DL066 Key Specifications n n n n n n n n Resolution Max Conversion Rate DNL SNR (fIN=40MHz) SNR (fIN=200MHz) SFDR (fIN=40MHz) SFDR (fIN=200MHz) Power Consumption — Operating — Power Down Mode 12 Bits 80 MSPS ± 0.4 LSB (typ) 69 dB (typ) 67 dB (typ) 82 dB (typ) 81 dB (typ) 447 mW (typ) 50 mW (typ) Applications n n n n Instrumentation Communications Receivers Sonar/Radar xDSL, Cable Modems Connection Diagram 20169401 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201694 www.national.com ADC12DL080 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) ADC12DL080CIVS ADC12DL080EVAL Package 64 Pin TQFP Evaluation Board Block Diagram 20169402 www.national.com 2 ADC12DL080 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 15 2 VINA+ VINB+ Differential analog input pins. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VCM. The negative input pins may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. This pin is used in conjunction with REFSEL/DCS (pin 11) to select the internal 1.0V reference, or as the external reference input. If VREF is tied HIGH, the internal 1.0V reference is selected. REFSEL/DCS must be LOW or tied to VRMA or VRMB. If a voltage in the range of 0.8V to 1.2V is applied to this pin, that voltage is used as the reference. VREF should be bypassed to AGND with a 0.1 µF low ESL capacitor when an external reference is used. The nominal external reference voltage is 1.0V but values in the range of 0.8V to 1.2V may be used. REFSEL/DCS must be HIGH or tied to VRMA or VRMB. See Table 3 in Section 2.2 for more information. This pin is used in conjunction with VREF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer (DCS) on or off. When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V reference is selected and DCS is On. When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the VREF input. DCS is On. With this pin connected to VRMA or VRMB, DCS is Off. See Table 3 in Section 2.2 for more information. Symbol Equivalent Circuit Description 16 1 VINA− VINB− 7 VREF 11 REFSEL/DCS 13 5 VRPA VRPB These are reference bypass pins. These pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins. These pins should not be loaded. 14 4 VRMA VRMB 12 6 DIGITAL I/O VRNA VRNB 60 CLK Digital clock input. The range of frequencies for this input is as specified in the electrical tables with guaranteed performance at 80 MHz. The inputs are sampled on the rising edge. 3 www.national.com ADC12DL080 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description 21 OF/DOEN OF/DOEN selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also controls the function of pins 22 and 41. When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin 22 is used to select the output format. Output Enable for channels A and B are not available in this mode. When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is 2’s complement. See Table 4 in Section 2.3 for more information. Output Enable for Channel A (OEA ) or Output format (OF). The function of this pin is controlled by the state of pin 21. When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin sets the output format. When LOW, the output data format is offset binary. When HIGH, the output format is 2’s complement. When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the Output Enable for Channel A. When LOW the outputs for Channel A are active. When HIGH, the outputs for Channel A are in a high impedance state. See Table 4 in Section 2.3 for more information. Output Enable for Channel B (OEB ) or Data Ready Output strobe (DRDY). The function of this pin is controlled by the state of pin 21. When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin is the DRDY output. The data outputs are synchronized with the falling edge of this signal. This signal switches at the same rate as the input clock. When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the Output Enable for Channel B. When LOW the outputs for Channel B are active. When HIGH, the outputs for Channel B are in a high impedance state. See Table 4 in Section 2.3 for more information. 22 OEA/OF 41 OEB/DRDY 59 PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 24–29 34–39 DA0–DA5 DA6-DA11 42–47 52–57 DB0–DB5 DB6-DB11 Digital data output pins that make up the 12-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are TTL/CMOS compatible. Optimum loading is < 10pF. www.national.com 4 ADC12DL080 Pin Descriptions and Equivalent Circuits Pin No. ANALOG POWER 9, 18, 19, 62, 63 3, 8, 10, 17, 20, 61, 64 DIGITAL POWER Symbol Equivalent Circuit (Continued) Description VA Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors located near the power pins, and with a 10 µF capacitor. The ground return for the analog supply. AGND 33, 48 VD Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and be bypassed to DGND with a 0.1 µF capacitor located near the power pins, and with a 10 µF capacitor. The ground return for the digital supply. Positive driver supply pin for the ADC12DL080’s output drivers. This pin should be connected to a voltage source of +2.4V to VD and be bypassed to DRGND with a 0.1 µF capacitor. This supply should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage on VD. All 0.1 µF bypass capacitors should be located near the supply pin. The ground return for the digital supply for the ADC12DL080’s output drivers. These pins should be connected to the system digital ground, but not be connected in close proximity to the ADC12DL080’s DGND or AGND pins. See Section 5 (Layout and Grounding) for more details. 32, 49 DGND 30, 51 VDR 23, 31, 40, 50, 58 DRGND 5 www.national.com ADC12DL080 Absolute Maximum Ratings 2) (Notes 1, Operating Ratings (Notes 1, 2) Operating Temperature Supply Voltage (VA, VD) Output Driver Supply (VDR) CLK, PD, OF/DOEN, OEA/OF, OEB/DRDY Analog Input Pins VCM |AGND–DGND| Clock Duty Cycle (DCS On) Clock Duty Cycle (DCS Off) −40˚C ≤ TA ≤ +85˚C +3.0V to +3.6V +2.4V to VD −0.05V to (VD + 0.05V) 0V to 2.6V 1.0V to 2.0V ≤100mV 30% to 70% 40% to 60% If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VA, VD, VDR |VA–VD| Voltage on Any Input or Output Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C ESD Susceptibility Human Body Model (Note 5) Machine Model (Note 5) Charge Device Model Soldering Temperature, Infrared, 10 sec. (Note 6) Storage Temperature 2500V 250V 750V 235˚C −65˚C to +150˚C 4.2V ≤ 100 mV −0.3V to (VA or VD +0.3V) ± 25 mA ± 50 mA See (Note 4) Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) 12 fIN = 0, Best Fit Method fIN = 0 Units (Limits) Bits (min) LSB (max) LSB (max) %FS (max) %FS (max) ppm/˚C +0.75 -1.1 %FS (max) %FS (min) ppm/˚C 0 4095 1.0 2.0 V (min) V (max) V pF pF 0.8 1.2 V (min) V (max) MΩ (min) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL PGE NGE TC GE VOFF TC VOFF Integral Non Linearity (Note 11) Differential Non Linearity Positive Gain Error Negative Gain Error Gain Error Tempco Offset Error (VIN+ = VIN−) Offset Error Tempco Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM VRMA, VRMB CIN VREF Common Mode Input Voltage Reference Output Voltage VIN Input Capacitance (each pin to GND) External Reference Voltage (Note 13) Reference Input Resistance www.national.com 6 ± 0.9 ± 0.4 ± 0.3 ± 0.3 10 -0.2 ± 3.5 ± 1.0 ± 3.5 ± 3.5 −40˚C ≤ TA ≤ +85˚C −40˚C ≤ TA ≤ +85˚C 16 0 4095 1.5 1.5 VIN = 1.5 Vdc ± 0.5V (CLK LOW) (CLK HIGH) 8 7 1.00 1 ADC12DL080 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) 600 69.3 67 69 66.5 11 10.75 −80 −76.8 −85 −84 −82 −81 82 81 −70 73 -74 -73 -71 10.75 66.5 67 Limits (Note 10) Units (Limits) MHz dBFS (min) dBFS dBFS (min) dBFS Bits (min) Bits dBc (min) dBc dBc (min) dBc dBc (min) dBc dBc (min) dBc dBFS DYNAMIC CONVERTER CHARACTERISTICS FPBW SNR SINAD ENOB THD H2 H3 SFDR IMD Full Power Bandwidth Signal-to-Noise Ratio (Note 16) Signal-to-Noise and Distortion (Note 16) Effective Number of Bits (Note 16) Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion 0 dBFS Input, Output at −3 dB fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 40 MHz, VIN = −1 dBFS fIN = 200 MHz, VIN = −1 dBFS fIN = 19.6 MHz and 20.2 MHz, each = −6.5 dBFS INTER-CHANNEL CHARACTERISTICS Channel — Channel Offset Match Channel — Channel Gain Match Crosstalk 10 MHz Tested, Channel; 20 MHz Other Channel ± 0.3 ± 0.4 90 %FS %FS dBc DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) 2.0 1.0 10 −10 5 VDR = 2.5V VDR = 3V 100 −100 −20 20 5 2.3 2.7 0.4 Units (Limits) V (min) V (max) µA µA pF V (min) V (min) V (max) nA nA mA mA pF DIGITAL INPUT CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) CIN Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V DIGITAL OUTPUT CHARACTERISTICS VOUT(1) VOUT(0) IOZ +ISC −ISC COUT Logical “1” Output Voltage Logical “0” Output Voltage TRI-STATE ® Output Current Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance IOUT = −0.5 mA IOUT = 1.6 mA, VDR = 3V VOUT = 2.5V or 3.3V VOUT = 0V VOUT = 0V VOUT = VDR 7 www.national.com ADC12DL080 DC and Logic Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) 112.5 15 23 0 15 0 447 50 80 535 Limits (Note 10) 136 26 Units (Limits) mA (max) mA mA (max) mA mA mA mW (max) mW dB POWER SUPPLY CHARACTERISTICS IA ID IDR Analog Supply Current Digital Supply Current Digital Output Supply Current Total Power Consumption PSRR Power Supply Rejection Ratio PD Pin = DGND, VREF = VA PD Pin = VD PD Pin = DGND PD Pin = VD , fCLK = 0 PD Pin = DGND, CL = 10 pF (Note 14) PD Pin = VD, fCLK = 0 PD Pin = DGND, CL = 10 pF (Note 15) PD Pin = VD Rejection of Full-Scale Error with VA = 3.0V vs. 3.6V AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol fCLK1 fCLK2 tCH tCL tCH tCL tr, tf tCONV tOD Parameter Maximum Clock Frequency Minimum Clock Frequency Clock High Time Clock Low Time Clock High Time Clock Low Time Clock Rise and Fall Times Conversion Latency Data Output Delay after Rising Clock Edge Output Set up time from data output transition to rising edge of DRDY Output Hold time from rising edge of DRDY to next data output transition Aperture Delay Aperture Jitter Data outputs into Hi-Z Mode Data Outputs Active after Hi-Z Mode Power Down Mode Exit Cycle 0.1 µF on pins 4,5,6,12,13,14; 10 µF between pins 5, 6 and between pins 12, 13 (Note 17) 7.5 Duty Cycle Stabilizer On Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer Off 10 6.25 6.25 6.25 6.25 2 7 3.5 11 4 3.75 3.75 5 5 Conditions Typical (Note 10) Limits (Note 10) 80 Units (Limits) MHz (min) MHz ns (min) ns (min) ns (min) ns (min) ns (max) Clock Cycles ns (min) ns (max) ns (min) tOSU 7.2 tOH tAD tAJ tDIS tEN (Note 17) 5.3 2 0.3 10 10 4 ns (min) ns ps rms ns ns tPD 100 µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. www.national.com 8 ADC12DL080 AC Electrical Characteristics (Continued) Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 64-pin TQFP, θJA is 50˚C/W, so PDMAX = 2 Watts at 25˚C and 800 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this device under normal operation will typically be about 497 mW (447 typical power consumption + 50 mW TTL output loading). The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: Reflow Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. 20169407 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Note 10: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for external reference applications. Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 15: Excludes IDR. See (Note 14). Note 16: This parameter is specified in units of dBFS - indicating the equivalent value that would be attained with a full-scale input signal Note 17: This parameter is guaranteed by design and/or characterization and is not tested in production. 9 www.national.com ADC12DL080 Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error Gain Error can also be expressed as Positive Gain Error and Negative Gain Error, which are: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average gain of the converters. INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12DL080 is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. www.national.com 10 NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of 1⁄2 LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN−)] required to cause a transition from code 2047 to 2048. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal input range to a specified voltage within the normal input range and the converter makes a conversion with its rated accuracy. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 11⁄2 LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12DL080, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. ADC12DL080 Timing Diagram 20169409 Output Timing Transfer Characteristic 20169410 FIGURE 1. Transfer Characteristic 11 www.national.com ADC12DL080 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 0, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C DNL INL 20169441 20169445 DNL vs. fCLK INL vs. fCLK 20169442 20169446 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20169443 20169447 www.national.com 12 ADC12DL080 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 0, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) DNL vs. Temperature INL vs. Temperature 20169444 20169448 DNL vs. VDR, VA = VD = 3.6V INL vs. VDR, VA = VD = 3.6V 20169470 20169471 DNL vs. VA INL vs. VA 20169476 20169477 13 www.national.com ADC12DL080 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C SNR, SINAD, SFDR vs. VA Distortion vs. VA 20169449 20169456 SNR,SINAD,SFDR vs. VDR, VA = VD = 3.6V Distortion vs. VDR, VA = VD = 3.6V 20169450 20169457 SNR, SINAD, SFDR vs. VCM Distortion vs. VCM 20169451 20169458 www.national.com 14 ADC12DL080 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) SNR, SINAD, SFDR vs. fCLK Distortion vs. fCLK 20169452 20169459 SNR, SINAD, SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle 20169453 20169460 SNR, SINAD, SFDR vs. Clock Duty Cycle (DCS=OFF) Distortion vs. Clock Duty Cycle (DCS=OFF) 20169474 20169475 15 www.national.com ADC12DL080 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) SNR, SINAD, SFDR vs. VREF Distortion vs. VREF 20169454 20169461 SNR, SINAD, SFDR vs. fIN Distortion vs. fIN 20169472 20169473 SNR, SINAD, SFDR vs. Temperature Distortion vs. Temperature 20169455 20169462 www.national.com 16 ADC12DL080 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) tOD vs. VDR, VA = VD = 3.6V Spectral Response @ 20 MHz Input 20169463 20169467 Spectral Response @ 39 MHz Input Spectral Response @ 200 MHz Input 20169468 20169469 Intermodulation Distortion, fIN1= 19.6 MHz, fIN2 = 20.2 MHz Power Consumtion vs. fCLK 20169438 20169436 17 www.national.com ADC12DL080 Functional Description Operating on a single +3.3V supply, the ADC12DL080 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.0 Volt or an external reference. Any external reference is buffered on-chip to ease the task of driving that pin. The output word rate is the same as the clock frequency, which can be between 10 MSPS and 80 MSPS (typical) with fully specified performance at 80 MSPS. The analog input for both channels is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle stabilization and output data format are selectable. The output data format can be set for offset binary or two’s complement. A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW. degraded noise performance. Loading any of these pins other than VRMA and VRMB may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VRM = 1.5 V VRP = VRM + VREF / 2 VRN = VRM − VREF / 2 User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA. If a voltage in the range of 0.8V to 1.2V is applied to the VREF pin, that is used for the voltage reference. When an external reference is used, the VREF pin should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin. There is no need to bypass the VREF pin when the internal reference is used. 1.3 Signal Inputs The signal inputs are VIN A+ and VINA− for one ADC and VINB+ and VINB− for the other ADC . The input signal, VIN, is defined as VIN A = (VINA+) – (VINA−) for the "A" converter and VIN B = (VINB+) – (VINB−) for the "B" converter. Figure 2 shows the expected input signal range. Note that the common mode input voltage, VCM, should be in the range of 1.0V to 2.0V. The peaks of the individual input signals should never exceed 2.6V. The ADC12DL080 performs best with a differential input signal with each input centered around a common mode voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Applications Information 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12DL080: 3.0V ≤ VA ≤ 3.6V VD = V A 2.4V ≤ VDR ≤ VD 10 MHz ≤ fCLK ≤ 80 MHz 0.8V ≤ VREF ≤ 1.2V (for an external reference) 1.0V ≤ VCM ≤ 2.0V 1.1 Analog Inputs There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external reference. The ADC12DL080 has two analog signal input pairs, VIN A+ and VIN A- for one converter and VIN B+ and VIN Bfor the other converter. Each pair of pins forms a differential input pair. 1.2 Reference Pins The ADC12DL080 is designed to operate with an internal 1.0V reference or an external 1.0V reference, but performs well with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-tonoise ratio (SNR) of the ADC12DL080. Increasing the reference voltage (and the input signal swing) beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins, as shown in Figure 4. This configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in 20169411 FIGURE 2. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 4096 ( 1 - sin (90˚ + dev)) Where dev is the angular difference in degrees between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. 18 www.national.com ADC12DL080 Applications Information (Continued) VIN+ VCM VCM + VREF/2 VCM + VREF VIN− VCM VCM VCM Binary Output 1000 0000 0000 1100 0000 0000 1111 1111 1111 2’s Complement Output 0000 0000 0000 0100 0000 0000 0111 1111 1111 20169412 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM. 1.3.1 Single-Ended Operation Performance with differential input signals is better than with single-ended signals. For this reason, single-ended operation is not recommended. However, if single ended-operation is required and the resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the driven input. The peak-topeak input signal at the driven input pin should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 1.0V, bias VIN− to 1.5V and drive VIN+ with a signal range of 0.5V to 2.5V. Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12DL080. TABLE 1. Input to Output Relationship – Differential Input VIN+ VCM − VREF/2 VCM − VREF/4 VCM VCM + VREF/4 VCM + VREF/2 VIN− VCM + VREF/2 VCM + VREF/4 VCM VCM − VREF/4 VCM − VREF/2 Binary Output 0000 0000 0000 0100 0000 0000 1000 0000 0000 1100 0000 0000 1111 1111 1111 2’s Complement Output 1000 0000 0000 1100 0000 0000 0000 0000 0000 0100 0000 0000 0111 1111 1111 1.3.2 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC12DL080 consist of an analog switch followed by a switched-capacitor amplifier. As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in voltage spikes at the signal input pins. As the driving source attempts to counteract these voltage spikes, it may add noise to the signal at the ADC analog input. To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in Figure 4 and Figure 5. These components should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. The values of the RC shown in Figure 4 and Figure 5 are suitable for applications with input frequencies up to approximately 70MHz. 1.3.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 1.0V to 2.0V and be a value such that the peak excursions of the analog signal does not go more negative than ground or more positive than 2.6V. See Section 1.2 2.0 DIGITAL INPUTS Digital TTL/CMOS compatible inputs consist of CLK, REFSEL/DCS, OF/DOEN, OEA/OF, OEB/DRDY. The OEB/ DRDY pin may also be configured as the DRDY output. 2.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 10 MHz to 80 MHz. The higher the input frequency, the more critical it is to have a low jitter clock. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90˚. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated TABLE 2. Input to Output Relationship – Single-Ended Input VIN+ VCM − VREF VCM − VREF/2 VIN− VCM VCM Binary Output 0000 0000 0000 0100 0000 0000 2’s Complement Output 1000 0000 0000 1100 0000 0000 19 www.national.com ADC12DL080 Applications Information (Continued) with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is With this pin connected to VRMA or VRMB, DCS is Off. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate a stable internal clock, improving the performance of the part. TABLE 3. VREF, REFSEL/DCS Pin Functions REFSEL/DCS (pin 11) VREF (pin 7) Reference DCS ON OFF where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12DL080 has a Duty Cycle Stabilizer which can be enabled using the REFSEL/DCS pin. It is designed to maintain performance over a clock duty cycle range of 30% to 70% at 80 MSPS. 2.2 REFSEL/DCS This pin is used in conjunction with VREF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer (DCS) on or off. When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V reference is selected and DCS is On. When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the VREF input. DCS is On. Logic LOW Logic High VRMA or VRMB VRMA or VRMB Logic HIGH 0.8 to 1.2V Logic High 0.8 to 1.2V Internal 1.0 V ON External External Internal 1.0V OFF 2.3 OF/DOEN, OEA/OF, and OEB/DRDY OF/DOEN (pin 21) selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also controls the function of pins 22 (OEA/OF) and 41 (OEB/DRDY). When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin 22 is used to select the output format. Output Enable for channels A and B are not available in this mode. When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is 2’s complement. The following table describes the function of these pins. TABLE 4. OF/DOEN, OEA/OF, OEB/DRDY Pin Functions Pin 21 State VRMA or VRMB Pin 21 Function DRDY output is enabled Pin 22 Function Output Format LOW = Offset Binary HIGH = 2’s Complement Pin 41 Function DRDY Output Logic LOW Logic HIGH Output Format = Offset Binary Output Enable for Channel A LOW = outputs are enabled Output Format = 2’s Complement HIGH = outputs are in high impedance state Output Enable for Channel B LOW = outputs are enabled HIGH = outputs are in high impedance state 2.4 PD The PD pin, when high, holds the ADC12DL080 in a powerdown mode to conserve power when the converter is not being used. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and 14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. 3.0 OUTPUTS The ADC12DL080 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at these outputs while the OE and PD pins are low. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers (74LVTH162374, for example) between the ADC outputs and any other circuitry. Only one driven input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. www.national.com 20 ADC12DL080 Applications Information (Continued) 20169413 FIGURE 4. Application Circuit using Transformer Drive Circuit 20169418 FIGURE 5. Optional Amplifier Drive for Circuit in Figure 4 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor near each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC12DL080 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VD. This can simplify interfacing to lower voltage devices and systems. Note, however, that tOD increases with reduced VDR. DO NOT operate the VDR pin at a voltage higher than VD. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12DL080 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can 21 www.national.com ADC12DL080 Applications Information (Continued) exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12DL080’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90˚ crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. 20169416 FIGURE 6. Example of a Suitable Layout Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. 22 www.national.com ADC12DL080 Applications Information (Continued) series with any offending digital input, close to the signal source, will eliminate the problem. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. Be careful not to overdrive the inputs of the ADC12DL080 with a device that is powered from supplies outside the range of the ADC12DL080 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12DL080, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in Figure 5) will improve performance. Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, VREF should be in the range of 0.8V ≤ VREF ≤ 1.2V Operating outside of these limits could lead to performance degradation. Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in Section 1.2, these pins should be bypassed with 0.1 µF capacitors to ground at VRMA and VRMB and with a 10 µF between pins VRPA and VRNA and between VRPB and VRNB for best performance. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Figure 6 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be placed in the digital area of the board. The ADC12DL080 should be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single, quiet point. All ground connections should have a low inductance path to ground. 6.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 7. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. Best performance will be obtained with a differential input drive, compared with a single-ended drive, as discussed in Sections 1.3.1 and 1.3.2. As mentioned in Section 5.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of the clock line. 20169417 FIGURE 7. Isolating the ADC Clock from other Circuitry with a Clock Tree 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in 23 www.national.com ADC12DL080 Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead TQFP Package Ordering Number ADC12DL080CIVS NS Package Number VECO64A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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