ADC12EU050CIPLQ

ADC12EU050 Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter July 6, 2009 ADC12EU050 Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter General Description The ADC12EU050 is a 12-bit, ultra-low power, octal A/D converter for use in high performance analog to digital applications. The ADC12EU050 uses an innovative continuous time sigma delta architecture offering ultra low power consumption and an alias free sample bandwidth up to 25MHz. The input stage of each channel features a proprietary system to ensure instantaneous recovery from overdrive. Instant overload recovery (IOR) with no memory effect guarantees the elimination of phase errors resulting from out of range input signals. The ADC12EU050 reduces interconnection complexity by using programmable serialized outputs which offer the industry standard LVDS and SLVS modes. Power consumption of only 48mW per channel @ 50MSPS gives a total chip power consumption of 384mW. The ADC12EU050 can operate entirely from a 1.2V supply, although a separate output driver supply of up to 1.8V can be used. The device operates from -40 to +85 °C and is supplied in a 10 x 10 mm2, 68 pin package. Features ■ ■ ■ ■ ■ ■ ■ CT∑Δ ADC architecture with 40-50MSPS throughput Anti-alias filter free Nyquist sample range Unique Instant Overload Recovery (IOR) Wide 2.10 VPP input range 1.2V supply voltage Integrated precision LC PLL Serial control via SPI compatible interface Key Specifications ■ Resolution ■ Conversion Rate ■ SNR ■ THD ■ ■ ■ ■ Per Channel Power Total Active Power Inter-Channel Isolation Operating Temp. Range 12 Bits 40 to 50 MSPS 69.3 dBFS (typ) @ 50 MSPS fIN = 4.4MHz –76.6 dB (typ) @ 50 MSPS fIN = 4.4MHz 48 mW/ch (typ) @ 50MSPS 385 mW (typ) @ 50MSPS >110 dB @ fIN = 4.4MHz -40 to +85 °C Applications ■ ■ ■ ■ Medical imaging, ultrasound Industrial ultrasound, such as non-destructive testing Communications Battery powered portable systems © 2009 National Semiconductor Corporation 300511 www.national.com ADC12EU050 Block Diagram 30051102 www.national.com 2 ADC12EU050 Connection Diagram 30051101 Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) ADC12EU050CIPLQ ADC12EU050EB Package 68 Pin LLP Evaluation Board 3 www.national.com ADC12EU050 Pin Descriptions Pin No. ANALOG I/O 2 3 67 68 64 65 61 62 58 59 55 56 52 53 49 50 4 VIN0+ VIN0VIN1+ VIN1VIN2+ VIN2VIN3+ VIN3VIN4+ VIN4VIN5+ VIN5VIN6+ VIN6VIN7+ VIN7VREFB Name Type Function and Connection Input Differential analog inputs to the ADC, for channels 0 to 7. The negative input pin may be connected via a capacitor to AGND or the inputs may be transformer coupled for single ended operation. Differential inputs are recommended for best performance. Optional negative reference voltage to improve multi-channel ADC matching. This pin must be connected to AGND. Optional positive reference voltage to improve multi-channel ADC matching. If using the internal reference, this pin should be left tied to AGND through a 100nF capacitor. If using an external reference voltage, this pin should be connected to the positive reference voltage, which must lie in the range specified in the Electrical Characteristics table. This pin provides the capacitance for the low pass filter in the modulator’s DAC. It must be connected to AGND through a minimum 100nF capacitor. It is possible to decrease the noise close to the carrier by increasing this capacitor, up to a maximum of 10μF. See Applications Information for further information on the selection of this capacitor. External bias reference resistor. This pin must always be connected to AGND through a resistor, whether the internal reference or an external reference voltage is used. The resistor value must be 10kΩ ±1%. This pin is an active low reset for the entire ADC, both analog and digital components. The pin must be held low for 500ns then returned to high in order to ensure that the chip is reset correctly. Sleep mode. Toggling this pin to high will cause the ADC to enter the low power sleep mode. When the pin is returned to low, the chip will, after the specified time to exit sleep mode, return to normal operation. 5 VREFT 6 DCAP Input 7 RREF Input/Output DIGITAL I/O 9 RST Input 10 SLEEP Input www.national.com 4 ADC12EU050 Pin No. 15 16 18 19 20 21 23 24 25 26 28 29 31 32 33 34 Name DO0+ DO0DO1+ DO1DO2+ DO2DO3+ DO3DO4+ DO4DO5+ DO5DO6+ DO6DO7+ DO7- Type Function and Connection Output Differential Serial Outputs for channels 0 to 7. Each pair of outputs provides the serial output for the specific channel. The default output is reduced common mode LVDS format, but by programming the appropriate control registers, the output format can be changed to SLVS or LVDS. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100 ohm resistors. 36 37 BCLK+ BCLK- Output Bit clock. Differential output clock used for sampling the serial outputs. Information on timing can be seen in the Electrical Specifications section of the datasheet. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100 ohm resistors. Word Clock. Differential output frame clock. Information on timing can be seen in the Electrical Specifications section of the datasheet. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100 ohm resistors. SPI data input and output. This pin is used to send and receive SPI address and data information. The direction of the pin is controlled internally by the ADC based on the SPI protocol. SPI clock. In order to use the SPI interface, a clock must be provided on this pin. See Electrical Specifications for SPI clock and timing information. SPI chip select. This active low pin is used to enable the serial interface. Differential Input Clock. The input clock must lie in the range of 40MHz to 50MHz. It is used by the PLL to generate the internal sampling clocks. A single ended clock can also be used, and should be connected to pin 47. Analog Power Supply. All pins should be connected to the same 1.2V supply, with voltage limits as in the Electrical Specification. Analog Ground Return. Digital Power Supply. Connect to 1.2V, with voltage limits as in the Electrical Specification. Digital and Output Driver Ground Return. Output Driver Power Supply. Can be connected to 1.2V – 1.8V, depending on application requirements. Voltage limits are described in more detail in the Electrical Specification. 38 39 WCLK+ WCLK- Output 44 SDATA Input/Output 45 SCLK SSEL CLK+ (SE) CLK- Input 46 Input 47 48 POWER SUPPLY 1, 8, 51, 54, 57, 60, 63, 66 0 11, 12, 42, 43 13, 14, 22, 30, 40, 41 17, 27, 35 Input VA AGND VD DGND Power Ground Power Ground VDR Power 5 www.national.com ADC12EU050 Absolute Maximum Ratings (Notes 1, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) IO Supply Voltage (VDR) Voltage at Analog Inputs Voltage at SPI Inputs Input Current, VIN+, VINInput Current, other pins ESD Susceptibility Human Body Model Machine Model Charged Device Mode Soldering Temperature Infrared, 10 seconds −0.3V to 1.4V -0.3 to 2.0V -0.3 to 1.4V -0.3 to 2.5V ±1mA ±10mA 2000V 200V 1,000V 235°C Storage Temperature Range −65°C to +125°C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. Operating Ratings (Notes 2, 3) −40°C to +85°C +1.14 to +1.26V +1.14 to +1.89V 40µs -0.10 to VA +1.14 to +2.50V 475mV to 525mV AGND 0.4V to 1.2V 1.8V R = 4.7 kohm, VDR = 1.2V 50 50 Guaranteed by design Test run at 2MHz, VDR = 1.2V Test run at 2MHz, VDR = 1.2V 5 VDR DRGND 850 250 -0.75 1 Test run at 2MHz Test run at 2MHz 900 300 1 -1 mV (min) mV (max) µA (max) µA (min) pF mV (min) mV (max) mA (min) mA (max) pF pF Digital Outputs (SDATA) Output Drive Capability (SDATA) CLOAD Load capacitance Open Drain Mode VEXT RSDATA Maximum allowed external voltage on Open Drain mode activated SDATA Recommended SDATA external pullup resistor Open Drain mode activated 4.7 2.5 V kΩ 11 www.national.com ADC12EU050 AC and Timing Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Symbol Parameter Conditions Typical (Note 4) Limits Units General ADC Output Timing Parameters fs Sample Rate Conversion Latency tBCLK tWCLK tS tH tDV tR, tF tDFS Bit clock period Word clock period Outputs Data Edge to Output Clock Edge Setup Time Output Data Edge to Output Clock Edge Hold Time Output Data Valid Window Output Rise/Fall time Data Edge to Word Edge Skew fCLK = 50MHz fCLK = 40MHz fCLK = 50MHz fCLK = 40MHz fCLK = 50MHz fCLK = 40MHz (Note 7) fCLK = 50MHz fCLK = 40MHz (Note 7) fCLK = 50MHz (Note 7) fCLK = 40MHz (Note 7) fCLK = 50MHz fCLK = 50MHz 19 3.33 4.16 20 25 800 900 850 1150 1380 1820 320 -295 -720 220 325 480 470 770 885 1410 40 50 MSPS (min) MSPS (max) Samples ns ns ns ns ps (min) ps (min) ps (min) ps (min) ps (min) ps (min) ps (min) ps (min) ps (max) mV 318 428 mV (min) mV (max) mV 895 1000 mV (min) mV (max) mV 280 417 mV (min) mV (max) mV 1200 1340 SLVS Output Parameters SLVS mode, I_drive[1:0] = 00 (2.5mA), RL = 100Ω VOD Differential Output Voltage SLVS mode, I_drive[1:0] = 01 (3.5mA), RL = 100Ω SLVS mode, I_drive[1:0] = 11 (5.0mA), RL = 100Ω VOCM Output Common Mode Voltage SLVS mode 225 185 270 mV (min) mV (max) 475 330 262 393 mV (min) mV (max) mV 245 mV mV (min) mv (max) LVDS Output Parameters, OCM = 0 (VDR = 1.2V) LVDS mode, I_drive[1:0] = 00 (2.5mA), RL = 100Ω VOD Differential Output Voltage LVDS mode, I_drive[1:0] = 01 (3.5mA), RL = 100Ω LVDS mode, I_drive[1:0] = 11 (5.0mA), RL = 100Ω VOCM Output Common Mode Voltage LVDS mode, OCM = 0 (for VDR = 1.2V) 945 520 370 270 LVDS Output Parameters, OCM = 1 (VDR = 1.8V) LVDS mode, I_drive[1:0] = 00 (2.5mA), RL = 100Ω VOD Differential Output Voltage LVDS mode, I_drive[1:0] = 01 (3.5mA), RL = 100Ω LVDS mode, I_drive[1:0] = 11 (5.0mA), RL = 100Ω VOCM Output Common Mode Voltage LVDS mode, OCM = 1 1265 485 350 265 www.national.com 12 ADC12EU050 AC and Timing Characteristics (Serial Interface) Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Symb ol Serial Interface tSSELS tSSELH tWS tWH tSCLK tSCLKL tSCLKH tSCLKR tSCLKF SSEL setup time SSEL hold time SDATA setup time, write transaction SDATA hold time, write transaction SCLK period SCLK low time SCLK high time SCLK rise time SCLK fall time Applies to read and write transactions SDATA valid setup time, read transaction SDATA valid hold time, read transaction 250 250 250 250 1 450 450 50 50 500 100 250 -5 10 15 10 0.2 ns ns ns (max) ns (max) µs (min) ns (min) ns (min) ns ns ns ns (min) ns (min) Parameter Conditions Typical (Note 4) Limits Units tSSELHI SSEL high time tRS tRH Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. Guaranteed specifications and test conditions are specified in the Electrical Characterisitcs section. Operation of the device beyond the Operating Ratings is not recommended as it may degrade the device lifetime. Note 3: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 4: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 5: This parameter is specified in dBFS. This indicates the value which would be obtained with a full-scale input. Note 6: As the filter is a digital circuit, Digital Decimation Filter Characteristics scale with input clock frequency, fCLK. Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 8: The combination of common mode and voltage swing on the clock input must ensure that the positive voltage peaks are not above VDR and the negative votlage peaks are not below AGND. Note 9: See the "Clock Conditioner Owner's Manual", Chapter 2 (www.national.com/appinfo/interface/files/clk_conditioner_owners_manual.pdf) for a discussion on jitter. 13 www.national.com ADC12EU050 Timing Diagrams 30051103 FIGURE 1. LVDS/SLVS Output Timing 30051129 FIGURE 2. Output Level Definitions www.national.com 14 ADC12EU050 30051104 FIGURE 3. SPI Write Timing 30051105 FIGURE 4. SPI Read Timing 15 www.national.com ADC12EU050 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. DNL INL 30051130 30051131 Spectral Response @ fIN=10MHz, fCLK= 40MHz, IOR off Spectral Response @ fIN=10MHz, fCLK= 40MHz, IOR on 30051132 30051133 Spectral Response @ fIN=10MHz, fCLK= 50MHz, IOR off Spectral Response @ fIN=10MHz, fCLK= 50MHz, IOR on 30051134 30051135 www.national.com 16 ADC12EU050 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs fCLK, IOR off Distortion vs fCLK, IOR off 30051139 30051140 SNR, SINAD, SFDR vs fCLK, IOR on Distortion vs fCLK, IOR on 30051141 30051142 SNR, SINAD, SFDR vs VA, fCLK = 40MHz, IOR off Distortion vs VA, fCLK = 40MHz, IOR off 30051143 30051153 17 www.national.com ADC12EU050 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs VA, fCLK = 50MHz, IOR off Distortion vs VA, fCLK = 50MHz, IOR off 30051144 30051154 SNR, SINAD, SFDR vs Temperature, fCLK = 40MHz, IOR off Distortion vs Temperature, fCLK = 40MHz, IOR off 30051156 30051157 SNR, SINAD, SFDR vs Temperature, fCLK = 50MHz, IOR off Distortion vs Temperature, fCLK = 50MHz, IOR off 30051160 30051161 www.national.com 18 ADC12EU050 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs fIN, fCLK = 40MHz, IOR off Distortion vs fIN, fCLK = 40MHz, IOR off 30051145 30051146 SNR, SINAD, SFDR vs fIN, fCLK = 40MHz, IOR on Distortion vs fIN, fCLK = 40MHz, IOR on 30051149 30051148 SNR, SINAD, SFDR vs fIN, fCLK = 50MHz, IOR off Distortion vs fIN, fCLK = 50MHz, IOR off 30051147 30051150 19 www.national.com ADC12EU050 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs fIN, fCLK = 50MHz, IOR on Distortion vs fIN, fCLK = 50MHz, IOR on 30051151 30051152 Spectral Response @ fIN1= 9.6MHz, fIN2= 10.1MHz, IOR off Spectral Response @ fIN1= 9.6MHz, fIN2= 10.1MHz, IOR on 30051136 30051137 Histogram of output code for zero input Current vs fCLK, Equalizer off, LVDS output 30051138 30051155 www.national.com 20 ADC12EU050 Functional Description The ADC12EU050 employs a number of unique strategies to provide a high performance multi-channel ADC that offers a significant power consumption reduction when compared to compteting architectures, as well as easing system level design. The ultra-low power performance of the ADC12EU050 is derived from the implementation of a fast continuous time sigma delta (CT∑Δ) modulator. Other features of this technology are: • Intrinsic anti-alias filter – the digital decimating filter provides an intrinsic anti-alias filter, eliminating external analog filter components, and simplifying multi-channel designs. • Instant overload recovery (IOR) system guarantees extremely fast recovery from overload (