ADC12L038CIWM

ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold June 1999 ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. These devices are fully tested with a single 3.3V power supply. The ADC12L032, ADC12L034 and ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12L030 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected. On request, these A/Ds go through a self calibration process that adjusts linearity, zero and full-scale errors to less than ± 1⁄2 LSB each. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range (0V to +3.3V) can be accommodated with a single +3.3V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign two’s compliment output data format. The serial I/O is configured to comply with NSC’s MICROWIRE™ and Motorola’s SPI standards. For voltage references, see the LM4040 or LM4041 data sheets. Features n 0V to 3.3V analog input range with single 3.3V power supply n Serial I/O ( MICROWIRE and SPI Compatible) n 2, 4, or 8 channel differential or single-ended multiplexer n Analog input sample/hold function n Power down mode n Variable resolution and conversion rate n Programmable acquisition time n Variable digital output word length and format n No zero or full scale adjustment required n Fully tested and guaranteed with a 2.5V reference n No Missing Codes over temperature Key Specifications n n n n n n n Resolution 12-bit plus sign conversion time 12-bit plus sign sampling rate Integral linearity error Single supply Power dissipation Power down 12-bit plus sign 8.8 µs (min) 73 kHz (max) ± 1 LSB (max) 3.3V ± 10% 15 mW (max) 40 µW (typ) Applications n Portable Medical instruments n Portable computing n Portable Test equipment ADC12L038 Simplified Block Diagram DS011830-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. COPS™ microcontrollers, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. Microsoft™ is a trademark of Microsoft Corporation. © 1999 National Semiconductor Corporation DS011830 www.national.com Ordering Information Industrial Temperature Range −40˚C ≤ TA ≤ +85˚C ADC12L030CIWM ADC12L032CIWM ADC12L034CIWM ADC12L038CIWM NS Package Number M16B M20B M24B M28B Connection Diagrams 16-Pin Wide Body SO Packages 24-Pin Wide Body SO Packages DS011830-2 Top View DS011830-4 20-Pin Wide Body SO Packages Top View 248-Pin Wide Body SO Packages DS011830-3 Top View DS011830-5 Top View www.national.com 2 Pin Descriptions CCLK The clock applied to this input controls the sucessive approximation conversion time interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. This address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data input pin. The data applied to this pin is shifted by the rising edge of SCLK into the multiplexer address and mode select register. Tables 2, 3, 4, 5 show the assignment of the multiplexer address and the mode select data. The data output pin. This pin is an active push/ pull output when CS is Low. When CS is High this output is in TRI-STATE. The A/D conversion result (D0–D12) and converter status data are clocked out by the falling edge of SCLK on this pin. The word length and format of this result can vary (see Table 1). The word length and format are controlled by the data shifted into the multiplexer address and mode select register (see Table 5). This pin is an active push/pull output and indicates the status of the ADC12L030/2/4/8. When low, it signals that the A/D is busy with a conversion, auto-calibration, auto-zero or power down cycle. The rising edge of EOC signals the end of one of these cycles. This is the chip select pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data on DI into the address register. This low also brings DO out of TRI-STATE. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The falling edge of CS resets a conversion in progress and starts the sequence for a new conversion. When CS is brought back low during a conversion, that conversion is prematurely ended. The data in the output latches may be corrupted. Therefore, when CS is brought back low during a conversion in progress the data output at that 3 SCLK time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied, it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin. Table 5 details the data required. DOR This is the data output ready pin. This pin is an active push/pull output. It is low when the conversion result is being shifted out and goes high to signal that all the data has been shifted out. A logic low is required on this pin to program any mode or change the ADC’s configuration as listed in the Mode Programming Table (Table 5) such as 12-bit conversion, 8-bit conversion, Auto Cal, Auto Zero etc. When this pin is high the ADC is placed in the read data only mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock out on DO any data stored in the ADCs output shift register. The data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously programmed. Read data only cannot be performed while a conversion, Auto-Cal or Auto-Zero are in progress. This is the power down pin. When PD is high the A/D is powered down; when PD is low the A/D is powered up. The A/D takes a maximum of 700 µs to power up after the command is given. These are the analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register (see Tables 2, 3, 4). The voltage applied to these inputs should not exceed VA+ or go below GND. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. This pin is another analog input pin. It is used as a pseudo ground when the analog multiplexer is single-ended. These are the multiplexer output pins. These are the converter input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2 it may be necessary to protect these pins. The voltage at these pins should not exceed VA+ or go below AGND (see Figure 5 ). This is the positive analog voltage reference input. In order to maintain accuracy the voltage range of VREF (VREF = VREF+ − VREF−) is CONV DI DO PD CH0–CH7 EOC CS COM MUXOUT1, MUXOUT2 A/DIN1, A/DIN2 VREF+ www.national.com Pin Descriptions (Continued) 1 VDCto 3.3 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 6 for recommended bypassing. VREF− The negative voltage reference input. In order to maintain accuracy the voltage at this pin must not go below GND or exceed VA+. (See Figure 6 ). These are the analog and digital power supply pins. VA+ and VD+ are not connected together on the chip. These pins should be tied to the same power supply and bypassed separately (see Figure 6 ). The operating voltage range of VA+ and VD+ is 3.0 VDC to 5.5 VDC. This is the digital ground pin (see Figure 6 ). This is the analog ground pin (see Figure 6 ). VA+, VD+ DGND AGND www.national.com 4 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V+ = VA+ = VD+) Voltage at Inputs and Outputs except CH0–CH7 and COM Voltage at Analog Inputs CH0–CH7 and COM |VA+ − VD+| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C (Note 4) ESD Susceptability (Note 5) Human Body Model Soldering Information N Packages (10 seconds) SO Package (Note 6): Vapor Phase (60 seconds) Infrared (15 seconds) Storage Temperature 6.5V −0.3V to V +0.3V GND −5V to V +5V 300 mV ± 30 mA ± 120 mA 500 mW 1500V 260˚C 215˚C 220˚C −65˚C to +150˚C + + Operating Ratings (Notes 1, 2) TMIN ≤ TA ≤ TMAX Operating Temperature Range ADC12L030CIWM, ADC12L032CIWM, ADC12L034CIWM, ADC12L038CIWM Supply Voltage (V+ = VA+ = VD+) |VA+ − VD+| VREF+ VREF− VREF (VREF+ − VREF−) VREF Common Mode Voltage Range −40˚C ≤ TA ≤ +85˚C +3.0V to +5.5V ≤ 100 mV 0V to VA+ 0V to VREF+ 1V to VA+ A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 Voltage Range A/D IN Common Mode Voltage Range 0V to VA+ Converter Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) 12 + sign After Auto-Cal (Notes 12, 18) After Auto-Cal (Notes 12, 18) After Auto-Cal After Auto-Cal (Notes 12, 18) After Auto-Cal (Notes 12, 18) After Auto-Cal (Notes 5, 18) VIN(+) = VIN (−) = 1.250V After Auto-Cal (Note 15) After Auto-Cal (Notes 12, 13, 14) Resolution with No Missing Codes +INL −INL DNL Positive Integral Linearity Error Negative Integral Linearity Error Differential Non-Linearity Positive Full-Scale Error Negative Full-Scale Error Offset Error 8-bit + sign mode 8-bit + sign mode (Note 12) 8-bit + sign mode (Note 12) 8-bit + sign mode 8-bit + sign mode (Note 12) 8-bit + sign mode (Note 12) 8-bit + sign mode, after Auto-Zero (Note 13) VIN(+) = VIN(−) = + 1.250V TUE Total Unadjusted Error 8-bit + sign mode after Auto-Zero (Notes 12, 13, 14) 8 + sign Bits (min) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes +ILE −ILE DNL Positive Integral Linearity Error Negative Integral Linearity Error Differential Non-Linearity Positive Full-Scale Error Negative Full-Scale Error Offset Error DC Common Mode Error TUE Total Unadjusted Error Bits (min) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ±2 ±1 ±1 ±1 ±1 ±2 ±2 ±2 ± 3.5 ± 1/2 ± 1/2 ± 3/4 ± 1/2 ± 1/2 ± 1/2 ± 3/4 LSB (max) 5 www.national.com Converter Electrical Characteristics (Continued) The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) STATIC CONVERTER CHARACTERISTICS Multiplexer Channel to Channel Matching Power Supply Sensitivity Offset Error + Full-Scale Error − Full-Scale Error + Integral Linearity Error − Integral Linearity Error Output Data from “12-Bit Conversion of Offset” (see Table 5) Output Data from “12-Bit Conversion of Full-Scale” (see Table 5) UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus fIN = 1 kHz, VIN = 2.5 VPP Distortion Ratio fIN = 20 kHz, VIN = 2.5 VPP −3 dB Full Power Bandwidth fIN = 40 kHz, VIN = 2.5 VPP VIN = 2.5 VPP, where S/(N+D) drops 3 dB 69.4 68.3 65.7 31 dB dB dB kHz (Note 20) 4095 4093 LSB (max) LSB (min) (Note 20) V+ = +3.3V ± 10% ± 0.05 LSB ± 0.5 ± 0.5 ± 0.5 ± 0.5 ± 0.5 ±1 ± 1.5 ± 1.5 LSB (max) LSB (max) LSB (max) LSB LSB +10 −10 LSB (max) LSB (min) DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus fIN = 1 kHz, VIN = ± 2.5V Distortion Ratio fIN = 20 kHz, VIN = ± 2.5V −3 dB Full Power Bandwidth fIN = 40 kHz, VIN = ± 2.5V VIN = ± 2.5V, where S/(N+D) drops 3 dB 77.0 73.9 67.0 40 dB dB dB kHz REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS CREF CA/D Reference Input Capacitance A/DIN1 and A/DIN2 Analog Input Capacitance A/DIN1 and A/DIN2 Analog Input Leakage Current CH0–CH7 and COM Input Voltage CCH CMUXOUT CH0–CH7 and COM Input Capacitance MUX Output Capacitance Off Channel Leakage (Note 16) CH0–CH7 and COM Pins On Channel = 3.3V and Off Channel = 0V On Channel = 0V and Off Channel = 3.3V On Channel = 3.3V and Off Channel = 0V On Channel = 0V and Off Channel = 3.3V www.national.com 6 85 75 VIN = +3.3V or VIN = 0V pF pF ± 0.1 ± 1.0 GND − 0.05 VA+ + 0.05 µA (max) V (min) V (max) pF pF 10 20 −0.01 0.01 0.01 −0.01 −0.3 0.3 0.3 −0.3 µA (min) µA (max) µA (max) µA (min) On Channel Leakage (Note 16) CH0–CH7 and COM Pins Converter Electrical Characteristics (Continued) The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) 0.3 1900 Units (Limits) REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS MUXOUT1 and MUXOUT2 VMUXOUT = 3.3V or Leakage Current RON MUX On Resistance RON Matching Channel to Channel Channel to Channel Crosstalk MUX Bandwidth VMUXOUT = 0V VIN = 1.65V and VMUXOUT = 1.55V VIN = 1.65V and VMUXOUT = 1.55V VIN = 3.3 VPP, fIN = 40 kHz 0.01 1300 5 −72 90 µA (max) Ω (max) % dB kHz DC and Logic Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage V+ = 3.6V VIN(0) IIN(1) IIN(0) Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current V+ = 3.0V VIN = 3.3V VIN = 0V 0.005 −0.005 Limits (Note 11) 2.0 0.8 1.0 −1.0 2.4 2.9 0.4 −0.1 0.1 14 16 1.1 600 12 2.2 10 0.1 70 0.1 3.0 −3.0 3.0 6.5 8.0 1.5 Units (Limits) V (min) V (max) µA (max) µA (min) V (min) V (min) V (max) µA (max) µA (max) mA (min) mA (min) mA (max) µA µA mA (max) µA µA µA µA DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage V+ = 3.0V, IOUT = −360 µA V+ = 3.0V, IOUT = − 10 µA VOUT(0) IOUT +ISC −ISC ID+ Logical “0” Output Voltage TRI-STATE ® Output Current Output Short Circuit Source Current Output Short Circuit Sink Current Digital Supply Current V+ = 3.0V, IOUT = 1.6 mA VOUT = 0V VOUT = 3.3V VOUT = 0V VOUT = VD+ Awake CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off Awake CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off Awake CS = HIGH, Powered Down POWER SUPPLY CHARACTERISTICS IA+ Positive Analog Supply Current IREF Reference Input Current 7 www.national.com AC Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17) Symbol fCK fSK Parameter Conversion Clock (CCLK) Frequency Serial Data Clock SCLK Frequency Conversion Clock Duty Cycle Serial Data Clock Duty Cycle tC Conversion Time 12-Bit + Sign or 12-Bit 8-Bit + Sign or 8-Bit tA Acquisition Time (Note 19) 6 Cycles Programmed 44(tCK) 21(tCK) 6(tCK) Conditions Typical (Note 10) 10 1 10 0 40 60 40 60 44(tCK) 8.8 21(tCK) 4.2 6(tCK) 7(tCK) 1.2 1.4 10 Cycles Programmed 10(tCK) 10(tCK) 11(tCK) 2.0 2.2 18 Cycles Programmed 18(tCK) 18(tCK) 19(tCK) 3.6 3.8 34 Cycles Programmed 34(tCK) 34(tCK) 35(tCK) 6.8 7.0 tCAL tAZ tSYNC Self-Calibration Time Auto-Zero Time Self-Calibration or Auto-Zero Synchronization Time from DOR tDOR DOR High Time when CS is Low Continuously for Read Data and Software Power Up/Down tCONV tHPU CONV Valid Data Time Hardware Power-Up Time, Time from PD Falling Edge to EOC Rising Edge 8(tSK) 250 9(tSK) 4944(tCK) 76(tCK) 2(tCK) 4944(tCK) 988.8 76(tCK) 15.2 2(tCK) 3(tCK) 0.40 0.60 9(tSK) 1.8 8(tSK) 1.6 700 5 Limits (Note 11) 5 Units (Limits) MHz (max) MHz (min) MHz (max) Hz (min) % (min) % (max) % (min) % (max) (max) µs (max) (max) µs (max) (min) (max) µs (min) µs (max) (min) (max) µs (min) µs (max) (min) (max) µs (min) µs (max) (min) (max) µs (min) µs (max) (max) µs (max) (max) µs (max) (min) (max) µs (min) µs (max) (max) µs (max) (max) µs (max) µs (max) www.national.com 8 AC Electrical Characteristics (Continued) The following specifications apply for V+ = VA+ = VD+ = +3.3 VDC, VREF+ = +2.500 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17) Symbol tSPU Parameter Software Power-Up Time, Time from Serial Data Clock Falling Edge to EOC Rising Edge tACC tSET-UP tDELAY t1H, t0H tHDI tSDI tHDO tDDO tRDO tFDO tCD tSD CIN COUT Access Time Delay from CS Falling Edge to DO Data Valid Set-Up Time of CS Falling Edge to Serial Data Clock Rising Edge Delay from SCLK Falling Edge to CS Falling Edge Delay from CS Rising Edge to DO TRI-STATE DI Hold Time from Serial Data Clock Rising Edge DI Set-Up Time from Serial Data Clock Rising Edge DO Hold Time from Serial Data Clock Falling Edge Delay from Serial Data Clock Falling Edge to DO Data Valid DO Rise Time, TRI-STATE to High DO Rise Time, Low to High DO Fall Time, TRI-STATE to Low DO Fall Time, High to Low Delay from CS Falling Edge to DOR Falling Edge Delay from Serial Data Clock Falling Edge to DOR Rising Edge Capacitance of Logic Inputs Capacitance of Logic Outputs 10 20 pF pF 45 80 ns (max) RL = 3k, CL = 100 pF RL = 3k, CL = 100 pF 10 10 15 15 50 40 40 40 40 80 ns (max) ns (max) ns (max) ns (max) ns (max) 50 RL = 3k, CL = 100 pF 35 65 5 90 ns (max) ns (min) ns (max) 5 10 ns (min) 5 15 ns (min) RL = 3k, CL = 100 pF 70 100 ns (max) 0 5 ns (min) 50 ns (min) 25 60 ns (max) 500 700 µs (max) Conditions Typical (Note 10) Limits (Note 11) Units (Limits) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be limited to 20 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJ max = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow: 9 www.national.com AC Electrical Characteristics (Continued) Thermal Part Number ADC12L030CIWM ADC12L032CIWM ADC12L034CIWM ADC12L038CIWM Resistance θJA 70˚C/W 64˚C/W 57˚C/W 50˚C/W Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05 VDC to ensure accurate conversions. DS011830-6 Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V+ pin. Note 9: With the test condition for VREF (VREF+ − VREF−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV. Note 10: Typicals are at TJ = TA = 25˚C and represent most likely parametric norm. Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3). Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions between 1 to 0 and 0 to +1 (see Figure 4). Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors. Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 16: Channel leakage current is measured after the channel selection. Note 17: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. Note 18: The ADC12L030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum repeatability uncertainty of 0.2 LSB. Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum. Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output data from these modes are not an indication of the accuracy of a conversion result. www.national.com 10 AC Electrical Characteristics (Continued) DS011830-7 FIGURE 1. Transfer Characteristic DS011830-8 FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles 11 www.national.com AC Electrical Characteristics (Continued) DS011830-9 FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle DS011830-10 FIGURE 4. Offset or Zero Error Voltage Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) Linearity Error Change vs Temperature Full-Scale Error Change vs Temperature Full-Scale Error Change vs Supply Voltage DS011830-51 DS011830-52 DS011830-53 www.national.com 12 Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) (Continued) Zero Error Change vs Temperature Zero Error Change vs Supply Voltage Analog Supply Current vs Temperature DS011830-54 DS011830-55 DS011830-56 Digital Supply Current vs Temperature DS011830-57 Test Circuits DO “TRI-STATE” (t1H, t0H) DO except “TRI-STATE” DS011830-15 DS011830-16 13 www.national.com Test Circuits (Continued) Leakage Current DS011830-17 Timing Diagrams DO Falling and Rising Edge DO “TRI-STATE” Falling and Rising Edge DS011830-18 DS011830-19 DI Data Input Timing DS011830-20 DO Data Output Timing Using CS DS011830-21 www.national.com 14 Timing Diagrams (Continued) DO Data Output Timing with CS Continuously Low DS011830-22 ADC12L038 Auto Cal or Auto Zero DS011830-23 Note: DO output data is not valid during this cycle. 15 www.national.com Timing Diagrams (Continued) ADC12L038 Read Data without Starting a Conversion Using CS DS011830-24 ADC12L038 Read Data without Starting a Conversion with CS Continuously Low DS011830-25 www.national.com 16 Timing Diagrams (Continued) ADC12L038 Conversion Using CS with 8-Bit Digital Output Format DS011830-26 ADC12L038 Conversion Using CS with 16-Bit Digital Output Format DS011830-27 17 www.national.com Timing Diagrams (Continued) ADC12L038 Conversion with CS Continuously Low and 8-Bit Digital Output Format DS011830-28 ADC12L038 Conversion with CS Continuously Low and 16-Bit Digital Output Format DS011830-29 www.national.com 18 Timing Diagrams (Continued) ADC12L038 Software Power Up/Down Using CS with 16-Bit Digital Output Format DS011830-30 ADC12L038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format DS011830-31 19 www.national.com Timing Diagrams (Continued) ADC12L038 Hardware Power Up/Down DS011830-32 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register. ADC12L038 Configuration Modification — Example of a Status Read DS011830-33 Note: In order for all 9 bits of status information to be accessible the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign, 12 bits, 12 bits plus sign, or greater. DS011830-34 FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins www.national.com 20 Timing Diagrams (Continued) DS011830-35 *Tantalum **Monolithic Ceramic or better FIGURE 6. Recommended Power Supply Bypassing and Grounding Tables TABLE 1. Data Out Formats DO Formats with Sign MSB First 17 Bits 13 Bits 9 Bits 17 Bits LSB First 13 Bits 9 Bits LSB 1 2 3 4 5 6 MSB Sign LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign X X X X Sign MSB 6 5 4 3 2 1 LSB Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB DB0 X DB1 X DB2 X DB3 X DB4 Sign DB5 MSB DB6 10 DB7 9 DB8 8 DB9 7 DB10 6 DB11 5 DB12 4 DB13 3 DB14 2 DB15 1 DB16 LSB 21 www.national.com Tables (Continued) TABLE 1. Data Out Formats (Continued) DO Formats without Sign MSB First 16 Bits 12 Bits 8 Bits 16 Bits LSB First 12 Bits 8 Bits DB0 0 DB1 0 DB2 0 DB3 0 DB4 MSB DB5 10 DB6 9 DB7 8 DB8 7 DB9 6 DB10 5 DB11 4 DB12 3 DB13 2 DB14 1 DB15 LSB DB16 MSB 10 9 8 7 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB LSB 1 2 3 4 5 6 7 8 9 10 MSB 0 0 0 0 LSB 1 2 3 4 5 6 7 8 9 10 MSB LSB 1 2 3 4 5 6 MSB X = High or Low state. TABLE 2. ADC12L038 Multiplexer Addressing Analog Channel Addressed MUX Address DI0 L L L L L L L L H H H H H H H H DI1 L L L L H H H H L L L L H H H H DI2 L L H H L L H H L L H H L L H H and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 L H L H L H L H L H L H L H L H + + + + + + + + − + − + − + − + − − − − − − − − + − + − + − + − COM A/DIN1 + + + + − − − − + + + + + + + + − − − − + + + + − − − − − − − − A/D Input Polarity Assignment Multiplexer Output Channel Assignment A/DIN2 MUXOUT1 MUXOUT2 CH0 CH2 CH4 CH6 CH0 CH2 CH4 CH6 CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 CH1 CH3 CH5 CH7 CH1 CH3 CH5 CH7 COM COM COM COM COM COM COM COM Single-Ended Differential Mode TABLE 3. ADC12L034 Multiplexer Addressing Analog Channel Addressed MUX Address DI0 L L L L H H H H DI1 L L H H L L H H DI2 L H L H L H L H + + + + − + − + − − − − and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 CH0 + CH1 − + − CH2 CH3 COM A/DIN1 + + − − + + + + A/DIN2 − − + + − − − − A/D Input Polarity Assignment Multiplexer Output Channel Assignment MUXOUT1 CH0 CH2 CH0 CH2 CH0 CH2 CH1 CH3 MUXOUT2 CH1 CH3 CH1 CH3 COM COM COM COM Single-Ended Differential Mode www.national.com 22 Tables (Continued) TABLE 4. ADC12L032 and ADC12L030 Multiplexer Addressing Analog Channel Addressed A/D Input Polarity Assignment A/DIN1 + − − + − + + A/DIN2 − + − − Multiplexer Output Channel Assignment MUXOUT1 CH0 CH0 CH0 CH1 MUXOUT2 CH1 CH1 COM COM Single-Ended Differential Mode MUX Address DI0 L L H H DI1 L H L H and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 CH0 + − + CH1 − + COM Note 21: ADC12L030 does not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins. TABLE 5. Mode Programming ADC12L038 ADC12L034 ADC12L030 and ADC12L032 See Tables 2, 3, 4 See Tables 2, 3, 4 See Tables 2, 3, 4 L L L L See Tables 2, 3, 4 See Tables 2, 3, 4 See Tables 2, 3, 4 L L L L L L L H L L H H L H L L L L L L L L L H L H L X L L L L L L L L L L L L L X L L L L L L L L L L L L L X L L L L L L L L H H H H H H H H H H H H H L L L L H H H H L L L L H H H H H H H H H L L H H L L H H L L H H L L L H H H H H H L H L H L H L H L H L H L H H L L L L H H 12 Bit Conversion 12 Bit Conversion 8 Bit Conversion 12 Bit Conversion of Full-Scale 12 Bit Conversion 12 Bit Conversion 8 Bit Conversion 12 Bit Conversion of Offset Auto Cal Auto Zero Power Up Power Down Read Status Register Data Out without Sign Data Out with Sign Acquisition Time — 6 CCLK Cycles Acquisition Time — 10 CCLK Cycles Acquisition Time — 18 CCLK Cycles Acquisition Time — 34 CCLK Cycles User Mode Test Mode (CH1–CH7 become Active Outputs) X = Don’t Care Note 22: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first and user mode. DI0 DI0 DI0 DI1 DI1 DI1 DI2 DI2 DI3 DI4 DI3 DI2 DI5 DI4 DI3 DI6 DI5 DI4 DI7 DI6 DI5 Mode Selected (Current) DO Format (next Conversion Cycle) 12 or 13 Bit MSB First 16 or 17 Bit MSB First 8 or 9 Bit MSB First 12 or 13 Bit MSB First 12 or 13 Bit LSB First 16 or 17 Bit LSB First 8 or 9 Bit LSB First 12 or 13 Bit LSB First No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change 23 www.national.com Tables (Continued) TABLE 6. Conversion/Read Data Only Mode Programming CS L L H X CONV L H X X PD L L L H Mode See Table 5 for Mode Read Only (Previous DO Format) No Conversion Idle Power Down X = Don’t Care TABLE 7. Status Register Status Bit Location Status Bit PU PD Device Status “High” indicates a Power Up Sequence is in progress “High” indicates a Power Down Sequence is in progress “High” indicates an Auto-Cal Sequence is in progress “High” indicates an 8 or 9 bit format Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test Mode DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DO Output Format Status “High” indicates a 12 or 13 bit format “High” indicates a 16 or 17 bit format “High” indicates that the sign bit is included. When “Low” the sign bit is not included. When “High” the conversion result will be output MSB first. When “Low” the result will be output LSB first. When “High” the device is in test mode. When “Low” the device is in user mode. Function Application Hints 1.0 DIGITAL INTERFACE 1.1 Interface Concepts The example in Figure 7 shows a typical sequence of events after the power is applied to the ADC12L030/2/4/8: EOC can be used to determine the end of a conversion or the A/D controller can keep track in software of when it would be appropriate to communicate to the A/D again. Once it has been determined that the A/D has completed a conversion another instruction can be transmitted to the A/D. The data from this conversion can be accessed when the next instruction is issued to the A/D. Note, when CS is low continuously it is important to transmit the exact number of SCLK cycles, as shown in the timing diagrams. Not doing so will desynchronize the serial communication to the A/D (see Section 1.3). 1.2 Changing Configuration The configuration of the ADC12L030/2/4/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10 CCLK acquisition time, user mode, no Auto Cal, no Auto Zero, and power up mode. Changing the acquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This instruction will not start a conversion. The instructions that select a multiplexer address and format the output data do start a conversion. Figure 8 describes an example of changing the configuration of the ADC12L030/2/4/8. During I/O sequence 1 the instruction on DI configures the ADC12L030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O sequences 2 and 3, a new conversion is not started. The data 24 DS011830-36 FIGURE 7. Typical Power Supply Power Up Sequence The first instruction input to the A/D via DI initiates Auto Cal. The data output on DO at that time is meaningless and is completely random. To determine whether the Auto Cal has been completed, a read status instruction is issued to the A/D. Again the data output at that time has no significance since the Auto Cal procedure modifies the data in the output shift register. To retrieve the status information, an additional read status instruction is issued to the A/D. At this time the status data is available on DO. If the Cal signal in the status word is low Auto Cal has been completed. Therefore, the next instruction issued can start a conversion. The data output at this time is again status information. To keep noise from corrupting the A/D conversion, the status can not be read during a conversion. If CS is strobed and is brought low during a conversion, that conversion is prematurely ended. www.national.com Application Hints (Continued) output during these instructions is from conversion N which was started during I/O sequence 1. The Configuration Modification timing diagram describes in detail the sequence of events necessary for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 5 describes the actual data necessary to be input to the ADC to accomplish this configuration modification. The next instruction, shown in Figure 8, issued to the A/D starts conversion N+1 with 8 bits of resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N. DS011830-37 FIGURE 8. Changing the ADC’s Conversion Configuration The number of SCLKs applied to the A/D during any conversion I/O sequence should vary in accord with the data out word format chosen during the previous conversion I/O sequence. The various formats and resolutions available are shown in Table 1. In Figure 8, since 8-bit without sign MSB first format was chosen during I/O sequence 4, the number of SCLKs required during I/O sequence 5 is 8. In the following I/O sequence the format changes to 12-bit without sine MSB first; therefore the number of SCLKs required during I/O sequence 6 changes accordingly to 12. 1.3 CS Low Continuously Considerations When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects. Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the ADC expects to see is the same as the digital output word length. The digital output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit is turned on or off. The table below details out the number of clock periods required for different DO formats: Number of DO Format 8-Bit MSB or LSB First 12-Bit MSB or LSB First 16-Bit MSB or LSB first SIGN OFF SIGN ON SIGN OFF SIGN ON SIGN OFF SIGN ON SCLKs Expected 8 9 12 13 16 17 detailed in Figure 7 (Typical Power Supply Sequence) as an example. The table below lists the number of SCLK pulses required for each instruction: Instruction Auto Cal Read Status Read Status 12-Bit + Sign Conv 1 12-Bit + Sign Conv 2 CS Low Continuously 13 SCLKs 13 SCLKs 13 SCLKs 13 SCLKs 13 SCLKs 8 SCLKs 8 SCLKs 8 SCLKs 8 SCLKs 13 SCLKs CS Strobed 1.4 Analog Input Channel Selection The data input on DI also selects the channel configuration for a particular A/D conversion (See Tables 2, 3, 4, 5). In Figure 8 the only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in Figure 8, to set CH1 as the positive input and CH0 as the negative input for the different versions of ADCs: Part Number ADC12L030 ADC12L032 ADC12L034 ADC12L038 DI Data DI0 L L L L DI1 H H H H DI2 L L L L DI3 L L L L DI4 H H L L DI5 L L H L DI6 X X L H DI7 X X X L Where X can be a logic high (H) or low (L). If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low continuously. The number of clock pulses required for an I/O exchange may be different for the case when CS is left low continuously vs. the case when CS is cycled. Take the I/O sequence 1.5 Power Up/Down The ADC may be powered down at any time by taking the PD pin HIGH or by the instruction input on DI (see Tables 5, 6, and the Power Up/Down timing diagrams). When the ADC is powered down in this way the circuitry necessary for an A/D conversion is deactivated. The circuitry necessary for digital I/O is kept active. Hardware power up/down is controlled by the state of the PD pin. Software power up/down is controlled by the instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power down is in effect (PD pin high) the device will remain 25 www.national.com Application Hints (Continued) in the power-down state. If a software power down instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down. When the device is powered down by software, it may be powered up by either issuing a software power up instruction or by taking PD pin high and then low. If the power down command is issued during an A/D conversion, that conversion is disrupted. Therefore, the data output after power up cannot be relied on. 1.6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CH0–CH7 become active outputs. If the device is inadvertently put into the test mode with CS low continuously, the serial communications may be desynchronized. Synchronization may be regained by cycling the power supply voltage to the device. Cycling the power supply voltage will also set the device into user mode. If CS is used in the serial interface, the ADC may be queried to see what mode it is in. This is done by issuing a “read STATUS register” instruction to the ADC. When bit 9 of the status register is high the ADC is in test mode; when bit 9 is low the ADC is in user mode. As an alternative to cycling the power supply, an instruction sequence may be used to return the device to user mode. This instruction sequence must be issued to the ADC using CS. The following table lists the instructions required to return the device to user mode: Instruction TEST MODE RESET TEST MODE INSTRUCTIONS USER MODE Power Up Set DO with or without Sign Set Acquisition Time Start a Conversion X = Don’t Care 1.7 Reading the Data Without Starting a Conversion The data from a particular conversion may be accessed without starting a new conversion by ensuring that the CONV line is taken high during the I/O sequence. See the Read Data timing diagrams. Table 6 describes the operation of the CONV pin. 2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER For the ADC12L038, the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels with the COM input as the zero reference or any combination thereof (see Figure 9 ). The difference between the voltages on the VREF+ and VREF− pins determines the input voltage span (VREF). The analog input voltage range is 0 to VA+. Negative digital output codes result when VIN− > VIN+. The actual voltage at VIN− or VIN+ cannot go below AGND. 4 Differential Channels DS011830-38 DI Data DI0 H L L L L L H or L H or L H or L H or L H or L H or L H or L L H or L H or L H or L L L H H H L L L L H H L H DI1 X L L L L L DI2 X L L L L L DI3 X L L L L L DI4 H H H H H H DI5 H H L L H L DI6 H H H H H H DI7 H L L H H L 8 Single-Ended Channels with COM as Zero Reference DS011830-39 FIGURE 9. CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3, CH5, and CH7 can be assigned to the MUXOUT2 pin. In the differential configuration, the analog inputs are paired as follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The A/DIN1 and A/DIN2 pins can be assigned positive or negative polarity. With the single-ended multiplexer configuration CH0 through CH7 can be assigned to the MUXOUT1 pin. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positive input; A/DIN2 is assigned as the negative input. (See Figure 10 ). The Multiplexer assignment tables for the ADC12L030,2,4,8 (Tables 2, 3, 4) summarize the aforementioned functions for the different versions of A/Ds. After returning to user mode with the user mode instruction the power up, data with or without sign, and acquisition time instructions need to be resent to ensure that the ADC is in the required state before a conversion is started. www.national.com 26 Application Hints (Continued) Single-Ended Configuration Differential Configuration DS011830-40 DS011830-41 A/DIN1 and A/DIN2 can be assigned as the + or − input A/DIN1 is + input A/DIN2 is − input FIGURE 10. DS011830-46 FIGURE 11. Single-Ended Biasing 2.1 Biasing for Various Multiplexer Configurations Figure 11 is an example of biasing the device for single-ended operation. The sign bit is always low. The digital output range is 0 0000 0000 0000 to 0 1111 1111 1111. One LSB is equal to 610 µV (2.5V/4096 LSBs). For pseudo-differential signed operation the biasing circuit shown in Figure 12 shows a signal AC coupled to the ADC. This gives a digital output range of −4096 to +4095. With a 1.25V reference, as shown, 1 LSB is equal to 305 µV. Although the ADC is not production tested with a 1.25V reference linearity error typically will not change more than 0.3 LSB. With the ADC set to an acquisition time of 10 clock periods the input biasing resistor needs to be 600Ω or less. Notice though that the input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600Ω to increase to 6k, which with a 1 µF coupling capacitor would set the high pass corner at 26 Hz. The value of R1 will depend on the value of R2. An alternative method for biasing pseudo-differential operation is to use the +1.25V from the LM4040 to bias any amplifier circuits driving the ADC as shown in Figure 13. The value of the resistor pull-up biasing the LM4040-2.5 will depend upon the current required by the op amp biasing circuitry. Fully differential operation is shown in Figure 14. One LSB for this case is equal to (2.5V/4096) = 610 mV. 27 www.national.com Application Hints (Continued) DS011830-47 FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC DS011830-48 FIGURE 13. Alternative Pseudo-Differential Biasing www.national.com 28 Application Hints (Continued) DS011830-50 FIGURE 14. Fully Differential Biasing 3.0 REFERENCE VOLTAGE The difference in the voltages applied to the VREF+ and VREF− defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage sources driving VREF+ or VREF− must have very low output impedance and noise. The ADC12L030/2/4/8 can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input voltage is proportional to the voltage used for the ADC’s reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA+ and VREF− is connected to ground. This technique relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage’s magnitude will require an initial adjustment to null reference voltage induced full-scale errors. Below are recommended references along with some key specifications. Output Part Number LM4041CIM3-Adj LM4040AIM3-2.5 Voltage Tolerance Temperature Coefficient (max) erence ladder should not go below 0.33V or above 1.98V. Figure 15 is a graphic representation of the voltage restrictions on VREF+ and VREF−. DS011830-43 FIGURE 15. VREF Operating Range ± 0.5% ± 0.1% ± 100ppm/˚C ± 100ppm/˚C The reference voltage inputs are not fully differential. The ADC12L030/2/4/8 will not generate correct conversions or comparisons if VREF+ is taken below VREF−. Correct conversions result when VREF+ and VREF− differ by 1V and remain, at all times, between ground and VA+. The VREF common mode range, (VREF+ + VREF−)/2, is restricted to (0.1 x VA+) to (0.6 x VA+). Therefore, with VA+ = 3.3V the center of the ref29 www.national.com Application Hints (Continued) 4.0 ANALOG INPUT VOLTAGE RANGE The ADC12L030/2/4/8’s fully differential ADC generate a two’s complement output that is found by using the equations shown below: for (12-bit) resolution the Output Code = also be extended to compensate for the settling or response time of external circuitry connected between the MUXOUT and A/DIN pins. The acquisition time (tA) is started by a falling edge of SCLK and ended by a rising edge of CCLK (see Timing Diagrams). If SCLK and CCLK are asynchronous one extra CCLK clock period may be inserted into the programmed acquisition time for synchronization. Therefore with asnychronous SCLK and CCLK the acquisition time will change from conversion to conversion. 7.0 INPUT BYPASS CAPACITANCE External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, CH0–CH7, and analog ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not degrade the conversion accuracy. 8.0 NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the noise sources. 9.0 POWER SUPPLIES Noise spikes on the VA+ and VD+ supply lines can cause conversion errors; the comparator will respond to the noise. The ADC is especially sensitive to any power supply spikes that occur during the auto-zero or linearity correction. The minimum power supply bypassing capacitors recommended are low inductance tantalum capacitors of 10 µF or greater paralleled with 0.1 µF monolithic ceramic capacitors. More or different bypassing may be necessary depending on the overall system requirements. Separate bypass capacitors should be used for the VA+ and VD+ supplies and placed as close as possible to these pins. 10.0 GROUNDING The ADC12L030/2/4/8’s performance can be maximized through proper grounding techniques. These include the use of separate analog and digital ground planes. The digital ground plane is placed under all components that handle digital signals, while the analog ground plane is placed under all components that handle analog signals. The digital and analog ground planes are connected together at only one point, either the power supply ground or at the pins of the ADC. This greatly reduces the occurence of ground loops and noise. Shown in Figure 16 is the ideal ground plane layout for the ADC12L038 along with ideal placement of the bypass capacitors. The circuit board layout shown in Figure 16 uses three bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) surface mount capacitors and 10 µF (C3) tantalum capacitor. 11.0 CLOCK SIGNAL LINE ISOLATION The ADC12L030/2/4/8’s performance is optimized by routing the analog input/output and reference signal conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins. Ground traces parallel to the clock signal traces can be used on printed circuit boards to reduce clock signal interference on the analog input/ output pins. for (8-bit) resolution the Output Code = Round off to the nearest integer value between −4096 to 4095 for 12-bit resolution and between −256 to 255 for 8-bit resolution if the result of the above equation is not a whole number. Examples are shown in the table below: Digital VREF+ +2.5V +2.500V +2.500V +2.500V VREF− +1V 0V 0V 0V VIN+ +1.5V +2V +2.499V 0V VIN− 0V 0V +2.500V +2.500V Output Code 0,1111,1111,1111 0,1100,1100,1101 1,1111,1111,1111 1,0000,0000,0000 5.0 INPUT CURRENT At the start of the acquisition window (tA) a charging current flows into or out of the analog input pins (A/DIN1 and A/DIN2) depending on the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1 is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend on the actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux on resistance is typically 750Ω. 6.0 INPUT SOURCE RESISTANCE For low impedance voltage sources ( < 600Ω), the input charging current will decay, before the end of the S/H’s acquisition time of 2 µs (10 CCLK periods with fC = 5 MHz), to a value that will not introduce any conversion errors. For high source impedances, the S/H’s acquisition time can be increased to 18 or 34 CCLK periods. For less ADC resolution and/or slower CCLK frequencies the S/H’s acquisition time may be decreased to 6 CCLK periods. To determine the number of clock periods (Nc) required for the acquisition time with a specific source impedance for the various resolutions the following equations can be used: 12 Bit + Sign NC = [RS + 2.3] x fC x 0.824 8 Bit + Sign NC = [RS + 2.3] x fC x 0.57 Where fC is the conversion clock (CCLK) frequency in MHz and RS is the external source resistance in kΩ. As an example, operating with a resolution of 12 Bits+sign, a 5 MHz clock frequency and maximum acquistion time of 34 conversion clock periods the ADC’s analog inputs can handle a source impedance as high as 6 kΩ. The acquisition time may www.national.com 30 Application Hints (Continued) DS011830-44 FIGURE 16. Ideal Ground Plane for the ADC12L038 12.0 THE CALIBRATION CYCLE A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to stabilize after initial turn on. During the calibration cycle, correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors down to the specified limits. Full-scale error typically changes ± 0.4 LSB over temperature and linearity error changes even less; therefore it should be necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient temperature do not change significantly (see the curves in the Typical Performance Characteristics). 13.0 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the A/D, the auto-zero cycle can be used. It may be necessary to do an auto-zero cycle whenever the ambient temperature or the power supply voltage change significantly. (See the curves titled “Zero Error Change vs Ambient Temperature” and “Zero Error Change vs Supply Voltage” in the Typical Performance Characteristics.) 14.0 DYNAMIC PERFORMANCE Many applications require the A/D converter to digitize AC signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with AC input signals. The important specifications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise (S/N), signal-to-noise + distortion ratio (S/(N + D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability. An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N + D) and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained. The A/D converter’s noise and distortion levels will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. This can be seen in the S/(N + D) versus frequency curves. These curves will also give an indication of the full power bandwidth (the frequency at which the S/(N + D) or S/N drops 3 dB). Effective number of bits can also be useful in describing the A/D’s noise performance. An ideal A/D converter will have some amount of quantization noise, determined by its resolution, which will yield an optimum S/N ratio given by the following equation: S/N = (6.02 x n + 1.76) dB where n is the A/D’s resolution in bits. The effective bits of a real A/D converter, therefore, can be found by: As an example, this device with a ± 2.5V, 10 kHz sine wave input signal will typically have a S/N of 78 dB, which is equivalent to 12.6 effective bits. 15.0 AN RS232 SERIAL INTERFACE Shown below is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR, RTS, and CTS RS232 signal lines are buffered via level translators and connected to the ADC12L038’s DI, SCLK, and DO pins, respectively. The D flip flop drive the CS control line. 31 www.national.com Application Hints (Continued) DS011830-45 Note: VA+, VD+, and VREF+ on the ADC12L038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF caps. The DS14C335 has an internal DC-DC converter that generates the necessary TIA/EIA-232-E output levels from a 3.3V supply. There are four 0.47 µF capacitors required for the DC-DC converter that are not shown in the above schematic. The assignment of the RS232 port is shown below B7 COM1 Input Address Output Address 3FE 3FC X X B6 X X B5 X X B4 CTS 0 B3 X X B2 X X B1 X RTS B0 X DTR A sample program, written in Microsoft™ QuickBasic, is shown on the next page. The program prompts for data mode select instruction to be sent to the A/D. This can be found from the Mode Programming table shown earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next the program prompts for the number of SCLKs required for the programmed mode select instruction. For instance, to send all “0”s to the A/D, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK periods since the output data format is 13 bits. The part powers up with No Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit conversion, data out with sign, 12- or 13-bit MSB First, power up, and user mode. Auto Cal, Auto Zero, Power UP and Power Down instructions do not change these default settings. The following power up sequence should be followed: 1. 2. 3. Run the program Prior to responding to the prompt apply the power to the ADC12L038 Respond to the program prompts It is recommended that the first instruction issued to the ADC12L038 be Auto Cal (see Section 1.1). www.national.com 32 Application Hints (Continued) DS011830-63 33 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Order Number ADC12L030CIWM NS Package Number M16B Order Number ADC12L032CIWM NS Package Number M20B www.national.com 34 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number ADC12L034CIWM NS Package Number M24B Order Number ADC12L038CIWM NS Package Number M28B 35 www.national.com ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.