ADC14155WRQV

ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter June 15, 2009 ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter General Description The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS. The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus singleended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14155 is available in a 48-lead thermally ehanced mult-layer ceramic quad package and operates over the military temperature range of -55°C to +125°C. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Total Ionizing Dose 100 krad(Si) Single Event Latch-up 120 MeV-cm2/mg 1.1 GHz Full Power Bandwidth Internal sample-and-hold circuit Low power consumption Internal precision 1.0V reference Single-ended or Differential clock modes Data Ready output clock Clock Duty Cycle Stabilizer Dual +3.3V and +1.8V supply operation (+/- 10%) Power-down mode Offset binary or 2's complement output data format 48-pin Cer Quad package, (11.5mm x 11.5mm, 0.635mm pin-pitch) Key Specifications ■ ■ ■ ■ ■ ■ ■ Resolution Conversion Rate SNR (fIN = 70 MHz) SFDR (fIN = 70 MHz) ENOB (fIN = 70 MHz) Full Power Bandwidth Power Consumption 14 Bits 155 MSPS 70.1 dBFS (typ) 82.3 dBFS (typ) 11.3 bits (typ) 1.1 GHz (typ) 967 mW (typ) Applications ■ ■ ■ ■ ■ ■ High IF Sampling Receivers Power Amplifier Linearization Multi-carrier, Multi-mode Receivers Test and Measurement Equipment Communications Instrumentation Radar Systems Ordering Information NS Part Number ADC14155W-MLS ADC14155WRQV (Note 15) TBD SMD Part Number NS Package Number EL48A EL48A Package Description 48L Cer Quad 48L Cer Quad © 2009 National Semiconductor Corporation 202107 www.national.com ADC14155QML Block Diagram 20210702 Connection Diagram 20210714 www.national.com 2 ADC14155QML Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 4 VIN− Differential analog input pins. The differential full-scale input signal level is two times the reference voltage with each input pin signal centered on a common mode voltage, VCM. Symbol Equivalent Circuit Description 5 VIN+ 42, 43 46, 47 VRP VRM These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 10 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VRM may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VRM to provide the common mode voltage, VCM, for the differential analog inputs, VIN+ and VIN−. This pin can be used as either the +1.0V internal reference voltage output (internal reference operation) or as the external reference voltage input (external reference operation). To use the internal reference, VREF should be decoupled to AGND with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In this mode, VREF defaults as the output for the internal 1.0V reference. To use an external reference, overdrive this pin with a low noise external reference voltage. The output impedance of the internal reference at this pin is 9kΩ. Therefore, to overdrive this pin, the impedance of the external reference source should be