ADC141S626CIMMX

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter November 30, 2007 ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter General Description The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA and a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage. The serial data output is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress. The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VA of 5V while communicating with a 3V controller on the digital side. Operating from a single 3V supply, the power consumption when operating at 200 kSPS is 2.0 mW. While operating from a single 5V supply, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications. Operation is guaranteed over the temperature range of −40° C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead MSOP package. Features ■ ■ ■ ■ ■ ■ ■ True Differential Inputs Guaranteed performance from 50 kSPS to 250 kSPS External Reference Zero-Power Track Mode Wide Input Common-Mode Voltage Range Operating Temperature Range of −40°C to +85°C SPI™/QSPI™/MICROWIRE™/DSP compatible Serial Interface Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ Conversion Rate INL DNL SNR THD ENOB Power Consumption — 200 kSPS, 3V — 250 kSPS, 5V — Power-Down, 3V — Power-Down, 5V 50 kSPS to 250 kSPS ± 0.95 LSB (max) ± 0.95 LSB (max) 82 LSB (max) − 90 dBc (typ) 13.3 bits (min) 2.0 mW (typ) 4.8 mW (typ) 4 µW (typ) 13 µW (typ) Applications ■ ■ ■ ■ ■ ■ Automotive Navigation Portable Systems Medical Instruments Instrumentation and Control Systems Motor Control Direct Sensor Interface Connection Diagram 30041305 TRI-STATE® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2007 National Semiconductor Corporation 300413 www.national.com ADC141S626 Ordering Information Order Code ADC141S626CIMM ADC141S626CIMMX ADC141S626EB Temperature Range −40°C to +85°C −40°C to +85°C Description 10-Lead MSOP Package, 1000 Units Tape & Reel 10-Lead MSOP Package, 3500 Units Tape & Reel Evaluation Board Top Mark X94C X94C Block Diagram 30041302 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 to 10 µF in parallel with the 0.1 µF capacitor is recommended for enhanced performance. Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the ADC141S626. Inverting Input. −IN is the negative analog input for the differential signal applied to the ADC141S626. Ground. GND is the ground reference point for all signals applied to the ADC141S626. Ground. GND is the ground reference point for all signals applied to the ADC141S626. Chip Select Bar. CS is active low. A conversion begins on the falling edge of CS. The ADC141S626 is in Acquisition Mode when CS is HIGH. Serial Data Output. The conversion result is provided on DOUT. The serial data output word is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion, the data is output on the falling edges of SCLK and is valid on the subsequent rising edges. Serial Clock. SCLK is used to control data transfer and serves as the conversion clock. Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to this input. VIO must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a bulk capacitor value of 1.0 to 10 µF. Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a bulk capacitor value of 1.0 to 10 µF. 1 VREF 2 3 4 5 6 +IN −IN GND GND CS 7 DOUT 8 9 SCLK VIO 10 VA www.national.com 2 ADC141S626 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage VA Digital I/O Supply Voltage VIO Voltage on Any Analog Input Pin to GND Voltage on Any Digital Input Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Charge Device Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to 6.5V −0.3V to (VA + 0.3V) −0.3V to (VIO + 0.3V) ±10 mA ±50 mA See (Note 4) 4000V 300V 1250V +150°C −65°C to +150°C Operating Ratings Operating Temperature Range (Notes 1, 2) −40°C ≤ TA ≤ +85°C Supply Voltage, VA +2.7V to +5.5V Supply Voltage, VIO +2.7V to +5.5V Reference Voltage, VREF 1.0V to VA Analog Input Pins Voltage Range 0 to VA Differential Analog Input Voltage −VREF to +VREF Input Common-Mode Voltage, VCM See Figure 10 (Sect 2.3) Digital Input Pins Voltage Range 0 to VIO Clock Frequency 0.9 MHz to 4.5 MHz Package Thermal Resistance Package 10-lead MSOP θJA 240°C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) ADC141S626 Converter Electrical Characteristics (Note 7) The following specifications apply for VA = VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA = VIO = VREF = +4.5V to 5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Resolution with No Missing Codes INL DNL OE FSE GE Integral Non-Linearity Differential Non-Linearity Offset Error Positive Full-Scale Error Negative Full-Scale Error Positive Gain Error Negative Gain Error VA = VIO = VREF = +3V, −0.1 dBFS VA = VIO = VREF = +5V, −0.1 dBFS VA = VIO = VREF = +3V, −0.1 dBFS VA = VIO = VREF = +5V, −0.1 dBFS VA = VIO = VREF = +3V, −0.1 dBFS VA = VIO = VREF = +5V, −0.1 dBFS VA = VIO = VREF = +3V, −0.1 dBFS VA = VIO = VREF = +5V, −0.1 dBFS VA = VIO = VREF = +3V, −0.1 dBFS VA = VIO = VREF = +5V, −0.1 dBFS Differential Output at 70.7%FS with Input FS Input Single-Ended Input ±0.5 ±0.5 −1 −3 0.5 −1.5 1.5 81.9 84.2 82 84.3 −102 −102 97 101 13.3 13.7 26 22 13.0 13.3 Conditions Typical Limits 14 ±0.95 ±0.95 ±5 ±7 ±4 ±6 ±6 80.1 82 80.2 82 Units Bits LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) dBc (min) dBc (min) dBc (min) dBc (min) dBc dBc dBc dBc bits (min) bits (min) MHz MHz STATIC CONVERTER CHARACTERISTICS DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR THD SFDR ENOB Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits FPBW −3 dB Full Power Bandwidth 3 www.national.com ADC141S626 Symbol Parameter Conditions Typical Limits −VREF +VREF Units V (min) V (max) µA (max) pF pF dB ANALOG INPUT CHARACTERISTICS VIN IDCL CINA CMRR Differential Input Range DC Leakage Current Input Capacitance Common Mode Rejection Ratio VIN = VREF or VIN = -VREF In Acquisition Mode In Conversion Mode See the Specification Definitions for the test condition VIO = +2.7V to 5.5V VIO = +2.7V to 5.5V VIN = 0V or VA 2 ISOURCE = 200 µA ISOURCE = 1 mA ISINK = 200 µA ISINK = 1 mA Force 0V or VA Force 0V or VA 2 VA − 0.05 VA − 0.16 0.01 0.05 ±1 4 0.4 30 3 76 ±1 DIGITAL INPUT CHARACTERISTICS VIH VIL IIN CIND Input High Voltage Input Low Voltage Input Current Input Capacitance 1.9 1.0 2.3 0.7 ±1 4 VA − 0.2 V (min) V (max) µA (max) pF (max) V (min) V V (max) V µA (max) pF (max) DIGITAL OUTPUT CHARACTERISTICS VOH VOL IOZH, IOZL COUT Output High Voltage Output Low Voltage TRI-STATE Leakage Current TRI-STATE Output Capacitance Output Coding POWER SUPPLY CHARACTERISTICS VA VIO VREF Analog Supply Voltage Range Digital Input/Output Supply Voltage Range Reference Voltage Range fSCLK = 3.6 MHz, VA = 3V, fS = 200 kSPS, fIN = 20 kHz fSCLK = 4.5 MHz, VA = 5V, fS = 250 kSPS, fIN = 20 kHz fSCLK = 3.6 MHz, VA = 3V, fS = 200 kSPS, fIN = 20 kHz fSCLK = 4.5 MHz, VA = 5V, fS = 250 kSPS, fIN = 20 kHz fSCLK = 3.6 MHz, VA = 3V, fS = 200 kSPS, fIN = 20 kHz fSCLK = 4.5 MHz, VA = 5V, fS = 250 kSPS, fIN = 20 kHz fSCLK = 4.5 MHz, VA = 5V fSCLK = 0 (Note 8) 540 740 90 170 25 45 8 2 3 0.1 0.1 0.1 0.2 0.3 3 (Note 9) 2.7 5.5 2.7 5.5 1.0 VA 760 970 190 260 60 80 V (min) V (max) V (min) V (max) V (min) V (max) µA (max) µA (max) µA (max) µA (max) µA (max) µA (max) µA µA (max) µA µA (max) µA µA (max) Binary 2'S Complement IVA (Conv) Analog Supply Current, Conversion Mode IVIO (Conv) Digital I/O Supply Current, Conversion Mode IVREF (Conv) Reference Current, Conversion Mode IVA (PD) IVIO (PD) IVREF (PD) Analog Supply Current, Power Down Mode (CS high) Digital I/O Supply Current, Power Down fSCLK = 4.5 MHz, VA = 5V Mode (CS high) fSCLK = 0 (Note 8) Reference Current, Power Down Mode (CS high) fSCLK = 4.5 MHz, VA = 5V fSCLK = 0 (Note 8) www.national.com 4 ADC141S626 Symbol PWR (Conv) Parameter Conditions fSCLK = 3.6 MHz, fS = 200 kSPS, fIN = 20 kHz, VA = VIO = VREF = 3.0V fSCLK = 4.5 MHz, fS = 250 kSPS, fIN = 20 kHz, VA = VIO = VREF = 5.0V Typical 2.0 4.8 3 13 −85 Limits 3.0 6.5 4 17 Units mW mW µW (max) µW (max) dB Power Consumption, Conversion Mode PWR (PD) fSCLK = 0, VA = VIO = VREF = 3.0V Power Consumption, Power Down Mode (Note 8) (CS high) fSCLK = 0, VA = VIO = VREF = 5.0V (Note 8) Power Supply Rejection Ratio See the Specification Definitions for the test condition VA = VIO = VREF = +2.7V to 5.5V PSRR AC ELECTRICAL CHARACTERISTICS fSCLK fSCLK fS tACQ tCONV tAD Maximum Clock Frequency Minimum Clock Frequency Maximum Sample Rate Acquisition/Track Time Conversion/Hold Time Aperture Delay See the Specification Definitions 6 4.8 4.5 0.9 250 667 15 MHz (min) MHz (max) kSPS (min) ns (min) SCLK cycles ns ADC141S626 Timing Specifications Symbol tCSS tDH tDA tDIS tCS tEN tCH tCL tr tf Parameter CS Setup Time prior to an SCLK rising edge DOUT Hold Time after an SCLK falling edge DOUT Access Time after an SCLK falling edge DOUT Disable Time after the rising edge of CS (Note 11) Minimum CS Pulse Width DOUT Enable Time after the falling edge of CS SCLK High Time SCLK Low Time DOUT Rise Time DOUT Fall Time (Note 7) The following specifications apply for VA = VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL = 25 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Conditions Typical 3 1/fSCLK - 3 10 28 10 5 32 67 67 7 7 Limits 6 1/fSCLK - 6 6 40 20 20 51 89 89 Units ns (min) ns (max) ns (min) ns (max) ns (max) ns (min) ns (max) ns (min) ns (min) ns ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC141S626 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 9: The value of VIO is independent of the value of VA. For example, VIO could be operating at 5V while VA is operating at 3V or VIO could be operating at 3V while VA is operating at 5V. Note 10: While the maximum sample rate is fSCLK/18, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/18. Note 11: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit. 5 www.national.com ADC141S626 Timing Diagrams 30041301 FIGURE 1. ADC141S626 Single Conversion Timing Diagram 30041310 FIGURE 5. Valid CS Assertion Times 30041308 FIGURE 2. Timing Test Circuit 30041312 30041306 FIGURE 3. DOUT Rise and Fall Times FIGURE 6. Voltage Waveform for tDIS 30041311 FIGURE 4. DOUT Hold and Access Times www.national.com 6 ADC141S626 Specification Definitions APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive FullScale Error and Negative Full-Scale Error and can be calculated as: Gain Error = Positive Full-Scale Error − Negative Full-Scale Error INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from ½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC141S626 is guaranteed not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale to the next code and −VREF + 1 LSB NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 0000h to 0001h and 1 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the ADC141S626, VA is changed from 4.5V to 5.5V. PSRR = 20 LOG (ΔOutput Offset / ΔVA) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below one-half the sampling frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. 7 www.national.com ADC141S626 Typical Performance Characteristics TA = +25°C, and fIN = 20 kHz unless otherwise stated. DNL - 250 kSPS VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, INL - 250 kSPS 30041321 30041322 DNL vs. VA INL vs. VA 30041323 30041324 DNL vs. VREF INL vs. VREF 30041318 30041319 www.national.com 8 ADC141S626 Typical Performance Characteristics TA = +25°C, and fIN = 20 kHz unless otherwise stated. DNL vs. SCLK FREQUENCY VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, INL vs. SCLK FREQUENCY 30041325 30041326 DNL vs. TEMPERATURE INL vs. TEMPERATURE 30041329 30041330 SINAD vs. VA THD vs. VA 30041333 30041332 9 www.national.com ADC141S626 Typical Performance Characteristics TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. VREF VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, THD vs. VREF 30041337 30041336 SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY 30041341 30041340 SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 30041349 30041348 www.national.com 10 ADC141S626 Typical Performance Characteristics TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. TEMPERATURE VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, THD vs. TEMPERATURE 30041372 30041371 VA CURRENT vs. VA VA CURRENT vs. SCLK FREQUENCY 30041335 30041355 VA CURRENT vs. TEMPERATURE VREF CURRENT vs. VREF 30041354 30041334 11 www.national.com ADC141S626 Typical Performance Characteristics TA = +25°C, and fIN = 20 kHz unless otherwise stated. VREF CURRENT vs. SCLK FREQUENCY VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, VREF CURRENT vs. TEMPERATURE 30041352 30041351 VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY 30041344 30041342 VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS 30041343 30041314 www.national.com 12 ADC141S626 Functional Description The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample/ hold function. The differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 operates from independent analog and digital supplies. The analog supply (VA) can range from 2.7V to 5.5V and the digital input/output supply (VIO) can range from 2.7V to 5.5V. The ADC141S626 utilizes an external reference. The external reference can be any voltage between 1V and VA. The value of the reference voltage determines the range of the analog input, while the reference input current depends upon the conversion rate. The analog input is presented to the two input pins: +IN and –IN. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry while a conversion is in progress. The ADC141S626 features a zeropower track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage. Zero-power track mode is exercised by bringing chip select bar (CS) high or when CS is held low after the conversion is complete (after the 16th falling edge of the serial clock). The external serial clock (SCLK) controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by internal capacitor leakage. Each conversion requires 18 SCLK cycles to complete. If less than 14 bits of conversion data are required, CS can be brought high at any point during the conversion. This procedure of terminating a conversion prior to completion is commonly referred to as short cycling. The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in progress and thus there is no pipe line delay. 1.0 REFERENCE INPUT The externally supplied reference voltage sets the analog input range. The ADC141S626 will operate with a reference voltage in the range of 1V to VA. Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the reference voltage (V REF) is reduced, the range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage, the differential peak-to-peak input range is limited to twice VREF. See Section 2.3 for more details. Reducing the value of VREF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 16,384. When the LSB size goes below the noise floor of the ADC141S626, the noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D converter will increase in terms of LSB size as the reference voltage is reduced. The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the ADC141S626. The reference current changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and “Reference Current vs. Temperature” in the Typical Performance Curves section for additional details. 2.0 ANALOG SIGNAL INPUTS The ADC141S626 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN). By using this differential input, small signals common to both inputs are rejected, as shown in Figure 7. As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. However, the ADC141S626 can be presented with a single-ended input. 30041375 FIGURE 7. Analog Input CMRR vs. Frequency The current required to recharge the input sampling capacitor will cause voltage spikes at +IN and −IN. Do not try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period. 13 www.national.com ADC141S626 2.1 Differential Input Operation With a fully differential input voltage or signal, a positive full scale output code (01 1111 1111 1111b or 1FFFh) will be obtained when (+IN) − (−IN) is greater than or equal to VREF − 1 LSB. A negative full scale code (10 0000 0000 0000b or 2000h) will be obtained when (+IN) − (−IN) is less than or equal to −VREF + 1 LSB. This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. Figure 8 shows the ADC141S626 being driven by a full-scale differential source. 2.3 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC141S626. The ranges of VCM are depicted in Figure 10 and Figure 11. Equations for calculating the minimum and maximum common mode voltages for differential and singleended operation are shown in Table 1. 30041380 FIGURE 8. Differential Input 2.2 Single-Ended Input Operation For single-ended operation, the non-inverting input (+IN) of the ADC141S626 can be driven with a signal that has a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting input (−IN) should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to utilize the entire dynamic range of the ADC141S626, the reference voltage is limited to VA / 2. This allows the non-inverting input a maximum swing range of ground to VA. Figure 9 shows the ADC141S626 being driven by a full-scale single-ended source. 30041361 FIGURE 10. VCM range for Differential Input operation 30041362 FIGURE 11. VCM range for single-ended operation TABLE 1. Allowable VCM Range Input Signal 30041381 Minimum VCM VREF / 2 VREF Maximum VCM VA − VREF / 2 VA − VREF Differential Single-Ended FIGURE 9. Single-Ended Input Since the design of the ADC141S626 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable. 3.0 SERIAL DIGITAL INTERFACE The ADC141S626 communicates via a synchronous 3-wire serial interface as shown in the Timing Diagram section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC141S626's D OUT pin is in 14 www.national.com ADC141S626 a high impedance state when CS is high and is active when CS is low; thus CS acts as an output enable. A timing diagram for a single conversion is shown in Figure 1. The ADC141S626 samples the differential input upon the assertion of CS. Assertion is defined as bringing the CS pin to a logic low state. For the first fifteen periods of the SCLK following the assertion of CS, the ADC141S626 is converting the analog input voltage. On the sixteenth falling edge of SCLK, the ADC141S626 enters acquisition/track mode. For the next three periods of SCLK, the ADC141S626 is operating in acquisition mode where the ADC input is tracking the analog input signal applied across +IN and -IN. During acquisition mode, the ADC141S626 is consuming a minimal amount of power. The ADC141S626 can enter conversion mode under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the ADC141S626 enters conversion mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the ADC141S626 automatically enters conversion mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC141S626 enters conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 5 for minimum and maximum setup time requirements for the falling edge of CS with respect to the rising edge of SCLK. 3.1 CS Input The CS (chip select bar) input is active low and is TTL and CMOS compatible. The ADC141S626 enters conversion mode when CS is asserted and the SCLK pin is in a logic low state. The ADC141S626 is always in acquisition mode and thus consuming the minimum amount of power when CS is high. Since CS must be asserted to begin a conversion, the sample rate of the ADC141S626 is equal to the assertion rate of CS. Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the 3rd falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the Timing Specification table. 3.2 SCLK Input The SCLK (serial clock) is used as the conversion clock and to shift out the conversion result. SCLK is TTL and CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC141S626 offers guaranteed performance with the clock rates indicated in the electrical table. The ADC141S626 enters acquisition mode on the 16th falling edge of SCLK during a conversion frame. Assuming that the LSB is clocked into a controller on the 16th rising edge of SCLK, there is a minimum acquisition time period that must be met before a new conversion frame can begin. Other than the 16th rising edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the controller. 3.3 Data Output The data output format of the ADC141S626 is two’s complement, as shown in Table 2. This table indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK. SCLK falling edges one and two clock out leading zeros while falling edges three through sixteen clock out the conversion result, MSB first. TABLE 2. Ideal Output Code vs. Input Voltage Analog Input (+IN) − (−IN) VREF − 1 LSB + 1 LSB 0V 0V − 1 LSB −VREF + 1 LSB 2's Complement Binary Code 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 10 0000 0000 0000 2's 2's Comp. Comp. Hex Code Dec Code 1FFF 0001 0000 3FFF 2000 8191 1 0 −1 −8192 While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of SCLK may be used to capture the conversion result if the minimum hold time (tDH) for DOUT is acceptable. See Figure 4 for DOUT hold and access times. DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new conversion will begin when CS is taken LOW. Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC141S626: −40°C ≤ TA ≤ +85°C +2.7V ≤ VA ≤ +5.5V +2.7V ≤ VIO ≤ +5.5V 1V ≤ VREF ≤ VA 0.9 MHz ≤ fSCLK ≤ 4.5 MHz VCM: See Section 2.3 4.0 POWER CONSUMPTION The architecture, design, and fabrication process allow the ADC141S626 to operate at conversion rates up to 250 kSPS while consuming very little power. The ADC141S626 consumes the least amount of power while operating in acquisition mode. For applications where power consumption is critical, the ADC141S626 should be operated in acquisition mode as often as the application will tolerate. To further reduce power consumption, stop the SCLK while CS is high. 4.1 Short Cycling Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can be used to lower the power consumption in those applications that do not need a full 14-bit resolution, or where an analog signal is being monitored until some condition occurs. In some circum15 www.national.com ADC141S626 stances, the conversion could be terminated after the first few bits. This will lower power consumption in the converter since the ADC141S626 spends more time in acquisition mode and less time in conversion mode. Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC141S626 output. This is possible because the ADC141S626 places the latest converted data bit on DOUT as it is generated. If only 10-bits of the conversion result are needed, for example, the conversion can be terminated by pulling CS high after the 10th bit has been clocked out. 4.2 Burst Mode Operation Normal operation of the ADC141S626 requires the SCLK frequency to be eighteen times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 250 kSPS, the ADC141S626 should be run with an SCLK frequency of 4.5 MHz and a CS rate as slow as the system requires. When this is accomplished, the ADC141S626 is operating in burst mode. The ADC141S626 enters into acquisition mode at the end of each conversion, minimizing power consumption. This causes the converter to spend the longest possible time in acquisition mode. Since power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. 5.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins. 5.1 Analog and Digital Power Supplies Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC141S626 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the ADC141S626 supply, with the 0.1 µF capacitor placed as close to the ADC141S626 package as possible. Since the ADC141S626 has both an analog and a digital input/output supply pin, the user has three options. The first option is to tie the analog and digital supply pins together and power them with the same power supply. This is the most cost effective way of powering the ADC141S626 but it is also the least ideal. As stated previously, noise from the digital supply pin can couple into the analog supply pin and adversely affect performance. The other two options involve the user powering the analog and digital supply pins with separate supply voltages. These supply voltages can have the same amplitude or they can be different. They may be set independent of each other to any value between 2.7V and 5.5V. Best performance will typically be achieved with the analog supply operating at 5V and the digital supply operating at 3V. Operating the analog supply at 5V offers the best linearity and dynamic performance when the reference voltage pin is also set to 5V; while operating the digital supply at 3V reduces the power consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the noise created by charging and discharging the capacitance of the digital interface pins. 5.2 Voltage Reference The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the ADC141S626 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference. The reference input of the ADC141S626, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are excellent choices for a reference source. 5.3 PCB Layout Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC141S626 due to supply noise, avoid using the same supply for the VA and VREF of the ADC141S626 that is used for digital circuity on the board. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. A single, uniform ground plane and the use of split power planes are recommended. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane. Furthermore, the GND pins on the ADC141S626 and all the components in the reference circuitry and input signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device. www.national.com 16 ADC141S626 6.0 APPLICATION CIRCUITS The following figures are examples of the ADC141S626 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. 6.1 Data Acquisition Figure 12 shows a typical connection diagram for the ADC141S626 operating at a supply voltage of +5V. The reference pin, VREF, is connected to a 4.1V shunt reference, the LM4040-4.1, to define the analog input range of the ADC141S626 independent of supply variation on the +5V supply line. The VREF pin should be de-coupled to the ground plane by a 0.1 µF ceramic capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close as possible to the VREF pin while the placement of the tantalum capacitor is less critical. It is also recommended that the analog and digital supply pins of the ADC141S626 be decoupled to ground by a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. 30041363 FIGURE 12. Low cost, low power Data Acquisition System 6.2 Bridge Sensor Application Figure 13 shows an example of interfacing a bridge sensor to the ADC141S626. The application assumes that the bridge sensor requires buffering and amplification to fully utilize the dynamic range of the ADC and thus optimize the performance of the entire signal path. The amplification stage consists of the LMP7702, a dual precision amplifier, and some gain setting passive components. The amplification stage offers the benefit of high input impedance and high amplification capability. On the other hand, it offers no common-mode rejection of common-mode noise or DC-voltage coming from the bridge sensor. The DAC081S101, a digital-to-analog converter (DAC), is used to bias the bridge sensor. The DAC provides a means for dynamically adjusting the gain of the bridge sensor relative to actual maximum and minimum output conditions. Another option for biasing the bridge sensor would be powering it from the same +5V power supply voltage as the analog supply pin on the ADC141S626. This option has the benefit of providing the ideal common-mode input voltage for the ADC141S626 while keeping design complexity and cost to a minimum. However, any fluctuation in the +5V supply will still be visible in the converted result. The LM4132-4.1, a 4.1V series reference, is used as the reference voltage in the application. The ADC141S626, DAC081S101, and the LM4132-4.1 are all powered from the same +5V voltage source. 30041366 FIGURE 13. Interfacing the ADC141S626 to a Bridge Sensor 17 www.national.com ADC141S626 6.3 Current Sensing Application Figure 14 shows an example of interfacing a current transducer to the ADC141S626. The current transducer converts an input current into a voltage that is converted by the ADC. Since the output voltage of the current transducer is singleended and centered around a common-mode voltage of 2.5V, the ADC141S626 is configured with the output of the transducer driving the non-inverting input and the common-mode output voltage of the transducer driving the inverting input. The output of the transducer has an output range of ±2V around the common-mode voltage of 2.5V. As a result, a series reference voltage of 2.0V is connected to the ADC141S626. This will allow all of the codes of the ADC141S626 to be available for the application. This configuration of the ADC141S626 is referred to as a single-ended application of a differential ADC. All of the elements in the application are conveniently powered by the same +5V power supply, keeping circuit complexity and cost to a minimum. 30041338 FIGURE 14. Interfacing the ADC141S626 to a Current Transducer www.national.com 18 ADC141S626 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Number ADC141S626CIMM NS Package Number MUB10A 19 www.national.com ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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