ADC14C105

ADC14C105 14-Bit, 95/105 MSPS A/D Converter August 2007 ADC14C105 14-Bit, 95/105 MSPS A/D Converter General Description The ADC14C105 is a high-performance CMOS analog-todigital converter capable of converting analog input signals into 14-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 1 GHz. The ADC14C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14C105 is available in a 32-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Features ■ ■ ■ ■ ■ ■ ■ ■ 1 GHz Full Power Bandwidth Internal reference and sample-and-hold circuit Low power consumption Data Ready output clock Clock Duty Cycle Stabilizer Single +3.0V or +3.3V supply operation Power-down mode 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch) Key Specifications ■ ■ ■ ■ ■ ■ ■ Resolution Conversion Rate SNR (fIN = 240 MHz) SFDR (fIN = 240 MHz) Full Power Bandwidth Power Consumption 14 Bits 105 MSPS 71 dBFS (typ) 82 dBFS (typ) 1 GHz (typ) 350 mW (typ, VA=3.0V) 400 mW (typ, VA=3.3V) Applications ■ ■ ■ ■ ■ High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation Connection Diagram 30017901 © 2007 National Semiconductor Corporation 300179 www.national.com ADC14C105 Block Diagram 30017902 Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) ADC14C105CISQ ADC14C105CISQE ADC14C105EB Package 32 Pin LLP 32 Pin LLP, 250-Piece Tape and Reel Evaluation Board www.national.com 2 ADC14C105 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 5 VIN+ Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. Symbol Equivalent Circuit Description 6 VIN- 2 32 VRP VCMO 1 VRN These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs, VIN+ and VIN−. Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1 µF low equivalent series inductance (ESL) capacitor . This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. The clock input pin. The analog input is sampled on the rising edge of the clock input. 31 VREF 12 OF/DCS DIGITAL I/O 11 CLK 30 PD This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. 3 www.national.com ADC14C105 Pin No. 13-19, 23-29 Symbol D0–D13 Equivalent Circuit Description Digital data output pins that make up the 14-bit conversion result. D0 (pin 13) is the LSB, while D13 (pin 29) is the MSB of the output word. Output levels are CMOS compatible. 21 DRDY Data Ready Strobe. The data output transition is synchronized with the falling edge of this signal. This signal switches at the same frequency as the CLK input. ANALOG POWER 3, 8, 10 VA Positive analog supply pins. These pins should be connected to a quiet voltage source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. The ground return for the analog supply. The exposed pad on back of package must be soldered to ground plane to ensure rated performance. Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. 4, 7, 9, Exposed Pad DIGITAL POWER 20 AGND VDR 22 DRGND www.national.com 4 ADC14C105 Absolute Maximum Ratings (Notes 1, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) Max Junction Temp (TJ) −0.3V to 4.2V −0.3V to (VA +0.3V) ±5 mA ±50 mA +150°C 30°C/W Operating Ratings Operating Temperature Supply Voltage (VA) Output Driver Supply (VDR) Clock Duty Cycle (DCS Enabled) (DCS disabled) VCM |AGND-DRGND| (Notes 1, 3) −40°C ≤ TA ≤ +85°C +2.7V to +3.6V +2.4V to VA 30/70 % 45/55 % 1.4V to 1.6V ≤100mV Thermal Resistance (θJA) ESD Rating Human Body Model (Note 6) 2500V Machine Model (Note 6) 250V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 7) Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) 14 ±1.8 ±0.5 -0.05 -0.54 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +85°C -8 -7 0.065 7.5 0 16383 0 16383 1.4 1.56 1.4 1.6 V (min) V (max) V (min) V (max) pF pF V ppm/°C 1.89 2.06 V (min) V (max) ±0.55 4 -4 1.3 -0.9 ±1.25 ±1.25 Units (Limits) Bits (min) LSB (max) LSB (min) LSB (max) LSB (min) %FS (max) %FS (max) ppm/°C ppm/°C %FS (max) ppm/°C STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL PGE NGE Integral Non Linearity Differential Non Linearity Positive Gain Error Negative Gain Error TC PGE Positive Gain Error Tempco TC NGE Negative Gain Error Tempco VOFF Offset Error (VIN+ = VIN-) Under Range Output Code Over Range Output Code TC VOFF Offset Error Tempco REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO VCM CIN VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc (Note 11) ± 0.5 V Internal Reference Voltage −40°C ≤ TA ≤ +85°C (Note 13) (CLK LOW) (CLK HIGH) 1.5 1.5 8.5 3.5 1.18 18 1.98 TC VREF Internal Reference Voltage Tempco VRP Internal Reference top 5 www.national.com ADC14C105 Symbol VRN Parameter Internal Reference bottom (Note 13) (Note 13) Conditions Typical Limits (Note 10) 0.98 1.20 0.89 1.06 1.176 1.224 Units (Limits) V (min) V (max) V (min) V (max) Ext VREF External Reference Voltage Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) GHz dBFS dBFS 69.4 dBFS dBFS dBFS 78 dBFS Bits Bits 11.1 Bits dBFS dBFS -74 dBFS dBFS dBFS -78 dBFS dBFS dBFS -78 dBFS dBFS dBFS 68.8 dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H3 Third Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 240 MHz IMD Intermodulation Distortion fIN = 19.5 MHz and 20.5MHz, each -7 dBFS 1.0 74 73.5 71 90 86 82 11.9 11.8 11.4 −86 −85 −79.3 −95 −90 −86 −90 −86 −82 73.5 73 70.4 -82 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA DIGITAL INPUT CHARACTERISTICS (CLK, PD) VIN(1) VIN(0) IIN(1) IIN(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V 6 2.0 0.8 10 −10 www.national.com ADC14C105 Symbol CIN VOUT(1) VOUT(0) +ISC −ISC COUT IA IDR Parameter Digital Input Capacitance Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance Analog Supply Current Digital Output Supply Current Power Consumption Power Down Power Consumption Full Operation Conditions Typical (Note 10) 5 Limits Units (Limits) pF DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY) IOUT = −0.5 mA , VDR = 2.4V IOUT = 1.6 mA, VDR = 2.4V VOUT = 0V VOUT = VDR −10 10 5 121 16 400 7.5 466 141 2.0 0.4 V (min) V (max) mA mA pF mA (max) mA mW (max) mW POWER SUPPLY CHARACTERISTICS Full Operation (Note 12) Excludes IDR (Note 12) Clock disabled Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Maximum Clock Frequency Minimum Clock Frequency tCH tCL tCONV tOD tSU tH tAD tAJ Clock High Time Clock Low Time Conversion Latency Output Delay of CLK to DATA Data Output Setup Time Data Output Hold Time Aperture Delay Aperture Jitter Relative to rising edge of CLK(Note 13) Relative to DRDY Relative to DRDY 5.76 4.5 4.5 0.6 0.1 4 4 7 3 7.3 3.7 3.8 Conditions Typical (Note 10) Limits 105 20 Units (Limits) MHz (max) MHz (min) ns ns Clock Cycles ns (min) ns (max) ns (min) ns (min) ns ps rms 7 www.national.com ADC14C105 Dynamic Converter Electrical Characteristics at 95MSPS Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 95 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) 74 73.5 71 90 86 82 11.9 11.8 11.4 −86 −85 −80 -95 −90 −85 −90 −86 −83 73.5 73 70.5 115 14.5 380 Limits Units (Limits) (Note 2) dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS mA (max) mA mW (max) DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS fIN = 10 MHz SNR Signal-to-Noise Ratio fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H3 Third Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 240 MHz POWER SUPPLY CHARACTERISTICS IA IDR Analog Supply Current Digital Output Supply Current Power Consumption Full Operation Full Operation (Note 12) Excludes IDR (Note 12) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal. Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10. Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. www.national.com 8 ADC14C105 30017911 Note 9: With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV. Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance. Note 12: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C13 x f13) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 13: This parameter is guaranteed by design and/or characterization and is not tested in production. 9 www.national.com ADC14C105 Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC14C105 is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition from code 8191 to 8192. OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the FullScale output of the ADC with the supply at the maximum DC supply limit, expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first six harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. www.national.com 10 ADC14C105 Timing Diagram 30017909 FIGURE 1. Output Timing Transfer Characteristic 30017910 FIGURE 2. Transfer Characteristic 11 www.national.com ADC14C105 Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. DNL INL Typical Performance Characteristics DNL, INL 30017941 30017942 DNL vs. fCLK INL vs. fCLK 30017943 30017944 DNL vs. Temperature INL vs. Temperature 30017947 30017948 www.national.com 12 ADC14C105 DNL vs. VA INL vs. VA 30017949 30017950 13 www.national.com ADC14C105 Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. SNR, SINAD, SFDR vs. VA Distortion vs. VA Typical Performance Characteristics 30017951 30017952 SNR, SINAD, SFDR vs. VDR Distortion vs. VDR 30017953 30017954 SNR, SINAD, SFDR vs. fCLK Distortion vs. fCLK 30017955 30017956 www.national.com 14 ADC14C105 SNR, SINAD, SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle 30017957 30017958 SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled Distortion vs. Clock Duty Cycle, DCS Enabled 30017959 30017960 SNR, SINAD, SFDR vs. fIN Distortion vs. fIN 30017963 30017964 15 www.national.com ADC14C105 SNR, SINAD, SFDR vs. Temperature Distortion vs. Temperature 30017965 30017966 Spectral Response @ 10 MHz Input Spectral Response @ 70 MHz Input 30017968 30017969 Spectral Response @ 240 MHz Input Intermodulation Distortion, fIN1= 19.5 MHz, fIN2 = 20.5 MHz 30017970 30017971 www.national.com 16 ADC14C105 Power vs. fCLK 30017972 17 www.national.com ADC14C105 Functional Description Operating on a single +3.3V supply, the ADC14C105 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 14 bits. The user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin. The output word rate is the same as the clock frequency. The analog input is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. The digital outputs are CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 21) at the same rate as the clock input. Duty cycle stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 12). The output data can be set for offset binary or two's complement. Power-down is selectable using the PD pin (pin 30). A logic high on the PD pin reduces the converter power consumption. For normal operation, the PD pin should be connected to the analog ground (AGND). maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and be centered around VCM.The peak-topeak voltage swing at each analog input pin should not exceed the 1V or the output data will be clipped. 30017915 FIGURE 3. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 16384 ( 1 - sin (90° + dev)) Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 4). For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Applications Information 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC14C105: 2.7V ≤ VA ≤ 3.6V 2.4V ≤ VDR ≤ VA 20 MHz ≤ fCLK ≤ 105 MHz 1.2V internal reference VREF = 1.2V (for an external reference) VCM = 1.5V (from VCMO) 2.0 ANALOG INPUTS 2.1 Signal Inputs 2.1.1 Differential Analog Input Pins The ADC14C105 has one pair of analog signal input pins, VIN+ and VIN−, which form a differential input pair. The input signal, VIN, is defined as VIN = (VIN+) – (VIN−) Figure 3 shows the expected input signal range. Note that the common mode input voltage, VCM, should be 1.5V. Using VCMO (pin 32) for VCM will ensure the proper input common mode level for the analog input signal. The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the differential pair should have a 30017916 FIGURE 4. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source impedance for the differential inputs will improve even ordered harmonic performance (particularly second harmonic). Table 1 indicates the input to output relationship of the ADC14C105. www.national.com 18 ADC14C105 TABLE 1. Input to Output Relationship VIN+ VCM − VREF/2 VCM − VREF/4 VCM VCM + VREF/4 VCM + VREF/2 VIN− VCM + VREF/2 VCM + VREF/4 VCM VCM − VREF/4 VCM − VREF/2 Binary Output 00 0000 0000 0000 01 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 11 1111 1111 1111 2’s Complement Output 10 0000 0000 0000 11 0000 0000 0000 00 0000 0000 0000 01 0000 0000 0000 01 1111 1111 1111 Positive Full-Scale Mid-Scale Negative Full-Scale 2.1.2 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC14C105 have an internal sample-and-hold circuit which consists of an analog switch followed by a switched-capacitor amplifier. Figure 5 and Figure 6 show examples of single-ended to differential conversion circuits. The circuit in Figure 5 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 6 works well above 70MHz. 30017920 FIGURE 5. Low Input Frequency Transformer Drive Circuit 30017921 FIGURE 6. High Input Frequency Transformer Drive Circuit One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed to the ADC core. The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown in Figure 7 should be used to isolate the charging glitches at the ADC input from the external driving circuit and to filter the wideband noise at the converter input. These components should be placed close to the ADC inputs because the analog input of the ADC is the most sensitive part of the system, and this is the last opportunity to filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling applica19 tions, the RC pole should be set at least 1.5 to 2 times the maximum input frequency to maintain a linear delay response. 2.1.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is recommended to use VCMO (pin 32) as the input common mode voltage. If the ADC14C105 is operated with VA=3.6V, a resistor of approximately 1KΩ should be used from the VCMO pin to AGND.This will help maintain stability over the entire temperature range when using a high supply voltage. 2.2 Reference Pins The ADC14C105 is designed to operate with an internal or external 1.2V reference. The internal 1.2 Volt reference is the default condition when no external reference input is applied to the VREF pin. If a voltage is applied to the VREF pin, then that voltage is used for the reference. The VREF pin should www.national.com ADC14C105 always be bypassed to ground with a 0.1 µF capacitor close to the reference input pin. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The Reference Bypass Pins (VRP, VCMO, and VRN) are made available for bypass purposes. These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is shown in Figure 7. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should not be loaded. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VCMO = 1.5 V VRP = 2.0 V VRN = 1.0 V 2.3 OF/DCS Pin Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate a stable internal clock, improving the performance of the part. With OF/DCS = VA the output data format is 2's complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*VA the output data format is 2's complement and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*VA the output data format is offset binary and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing this is not recommended as the output data could be erroneous for a few clock cycles after this change is made. 3.0 DIGITAL INPUTS Digital CMOS compatible inputs consist of CLK, and PD. 3.1 Clock Input The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock source through a high speed buffer gate. This configuration is shown in Figure 7 . The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. Figure 7 shows the recommended clock input circuit. The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC14C105 has a Duty Cycle Stabilizer. It is designed to maintain performance over a clock duty cycle range of 30% to 70%. 3.2 Power-Down (PD) The PD pin, when high, holds the ADC14C105 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 5 mW if the clock is stopped when PD is high. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on pins 1, 2, and 32 and is about 3 ms with the recommended components on the VRP, VCMO and VRN reference bypass pins. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. 4.0 DIGITAL OUTPUTS Digital outputs consist of the CMOS signals D0-D13, and DRDY. The ADC14C105 has 15 CMOS compatible data output pins corresponding to the converted input value and a data ready (DRDY) signal that should be used to capture the output data. Valid data is present at these outputs while the PD pin is low. Data should be captured and latched with the rising edge of the DRDY signal. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. The result could be an apparent reduction in dynamic performance. www.national.com 20 ADC14C105 30017919 FIGURE 7. Application Circuit 5.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor close to each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC14C105 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VA. This enables lower power operation, reduces the noise coupling effects from the digital outputs to the analog circuitry and simplifies interfacing to lower voltage devices and systems. 6.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC14C105 between these areas, is required to achieve specified performance. The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the ADC14C105's other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. The effects of the noise generated from the ADC output switching can be minimized through the use of 22Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane area. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors and transformers. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog input and the clock input at 90° to one another to avoid magnetic coupling. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The ADC14C105 should be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short 21 www.national.com ADC14C105 traces and enter the ground plane at a single, quiet point. All ground connections should have a low inductance path to ground. 7.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 8. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. As mentioned in Section 6.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line. 30017917 FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree www.national.com 22 ADC14C105 Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead LLP Package Ordering Number: ADC14C105CISQ NS Package Number SQA32A 23 www.national.com ADC14C105 14-Bit, 95/105 MSPS A/D Converter Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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