ADC14DS095CISQ

ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Dual 14-Bit A/D Converter ADVANCE INFORMATION February 2007 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Dual 14-Bit, 65/80/95/105 MSPS A/D Converter with Serial LVDS Outputs General Description NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change. The ADC14DS065, ADC14DS080, ADC14DS095, and ADC14DS105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 14-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14DS065/080/095/105 may be operated from a single +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DS065/080/095/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14DS065/080/095/105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Features ■ ■ ■ ■ ■ ■ ■ ■ 1 GHz Full Power Bandwidth Internal sample-and-hold circuit and precision reference Low power consumption Clock Duty Cycle Stabilizer Single +3.3V supply operation Offset binary or 2's complement output data format Serial LVDS Outputs 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications ■ ■ ■ ■ ■ ■ ■ For ADC14DS105 Resolution Conversion Rate SNR (fIN = 240 MHz) SFDR (fIN = 240 MHz) Full Power Bandwidth Power Consumption 14 Bits 105 MSPS 72 dBFS (typ) 83 dBFS (typ) 1 GHz (typ) 1060 mW (typ) Applications ■ ■ ■ ■ ■ High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation Connection Diagram 20211201 © 2007 National Semiconductor Corporation 202112 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Block Diagram 20211202 Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) ADC14DS065CISQ ADC14DS080CISQ ADC14DS095CISQ ADC14DS105CISQ Package 60 Pin LLP 60 Pin LLP 60 Pin LLP 60 Pin LLP www.national.com 2 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 3 13 VINA+ VINB+ Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. Symbol Equivalent Circuit Description 2 14 VINAVINB- 5 11 7 9 VRPA VRPB VCMOA VCMOB VRNA VRNB 6 10 These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs. Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series inductance (ESL) capacitor. This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. LVDS Driver Bias Resistor is applied from this pin to Analog Ground. The nominal value is 3.6KΩ The clock input pin. The analog inputs are sampled on the rising edge of the clock input. 59 VREF 29 DIGITAL I/O 18 LVDS_Bias CLK 28 Reset_DLL Reset_DLL input. This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds after Reset_DLL is asserted. 19 OF/DCS This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. 3 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin No. 57 20 Symbol PD_A PD_B Equivalent Circuit Description This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Test Mode. When this signal is asserted high, a fixed test pattern (10100110001110 msb->lsb) is sourced at the data outputs With this signal deasserted low, the device is in normal operation mode. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Word Alignment Mode. In single-lane mode this pin must be set to logic-0. In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this signal at logic-1 the serial data words are aligned with each other. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Dual-Lane Configuration. The dual-lane mode is selected when this signal is at logic-0. With this signal at logic-1, all data is sourced on a single lane (SD1_x) for each channel. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Serial Clock. This pair of differential LVDS signals provides the serial clock that is synchronous with the Serial Data outputs. A bit of serial data is provided on each of the active serial data outputs with each falling and rising edge of this clock. The user has the ability to set the position of the clock edges at either the data-bitcell boundries (0-degree phase) or at the center of the data-bit-cell boundries (180-degree phase). This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Frame. This pair of differential LVDS signals transitions at the serial data word boundries. The SD1_A+/- and SD1_B+/output words always begin with the rising edge of the Frame signal. The falling edge of the Frame signal defines the start of the serial data word presented on the SD0_A+/- and SD0_B+/- signal pairs in the Dual-Lane mode. This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. 27 TEST 47 WAM 48 DLC 45 44 OUTCLK+ OUTCLK- 43 42 FRAME+ FRAME- www.national.com 4 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin No. Symbol Equivalent Circuit Description Serial Data Output 1 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 1 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always enabled while the device is powered up. In powerdown mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always enabled while the device is powered up. In powerdown mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. SPI Enable: The SPI interface is enabled when this signal is asserted high. In this case the direct control pins have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are enabled. Serial Chip Select: While this signal is asserted SCLK is used to accept serial data present on the SDI input and to source serial data on the SDO output. When this signal is deasserted, the SDI input is ignored and the SDO output is in TRI-STATE mode. Serial Clock: Serial data are shifted into and out of the device synchronous with this clock signal. Serial Data-In: Serial data are shifted into the device on this pin while SCSb signal is asserted. 38 37 SD1_A+ SD1_A- 34 33 SD1_B+ SD1_B- 36 35 SD0_A+ SD0_A- 32 31 SD0_B+ SD0_B- 56 SPI_EN 55 SCSb 52 54 SCLK SDI 5 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin No. 53 Symbol SDO Equivalent Circuit Description Serial Data-Out: Serial data are shifted out of the device on this pin while SCSb signal is asserted. This output is in TRI-STATE mode when SCSb is deasserted. Overrange. These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in either high or low direction. DLL_Lock Output. When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to the input CLK. Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. The ground return for the analog supply. 46 30 ORA ORB 24 DLL_Lock ANALOG POWER 8, 16, 17, 58, 60 1, 4, 12, 15, Exposed Pad DIGITAL POWER 26, 40, 50 VDR Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. VA AGND 25, 39, 51 DRGND www.national.com 6 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Absolute Maximum Ratings (Notes 1, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) Max Junction Temp (TJ) −0.3V to 4.2V −0.3V to (VA +0.3V) ±5 mA ±50 mA +150°C 30°C/W Operating Ratings Operating Temperature (Notes 1, 3) −40°C ≤ TA ≤ +85°C +2.7V to +3.6V +3.0V to +3.6V 30/70 % 45/55 % 1.4V to 1.6V Supply Voltage (VA=VDR) (ADC14DS065,ADC14DS080) (ADC14DS095,ADC14DS105) Clock Duty Cycle (DCS Enabled) (DCS disabled) VCM |AGND-DRGND| ≤100mV Thermal Resistance (θJA) ESD Rating Human Body Model (Note 6) 2500V Machine Model (Note 6) 250V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 7) ADC14DS065 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) 14 ±1.5 ±0.5 0 16383 0 16383 1.45 1.55 1.4 1.6 V (min) V (max) V (min) V (max) pF pF 1.176 1.224 V (min) V (max) Units (Limits) Bits (min) LSB (max) LSB (min) LSB (max) LSB (min) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL Integral Non Linearity (Note 11) Differential Non Linearity Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO VCM CIN VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc (Note 12) ± 0.5 V External Reference Voltage (CLK LOW) (CLK HIGH) 1.5 1.5 8.5 3.5 1.20 7 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS065 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) GHz dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz H3 Third Harmonic Distortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 170 MHz 1.0 74.3 72 72 90 88 83 12 11.6 11.6 −88 −85 −80 −100 −95 −85 −90 −88 −83 74.1 71.8 71.4 www.national.com 8 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS065 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA pF 1.2 0.4 −10 10 5 Full Operation Full Operation 180 53 700 30 V (min) V (max) mA mA pF mA (max) mA mW (max) mW DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC) VIN(1) VIN(0) IIN(1) IIN(0) CIN VOUT(1) VOUT(0) +ISC −ISC COUT IA IDR Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance Analog Supply Current Digital Output Supply Current Power Consumption Power Down Power Consumption IOUT = −0.5 mA , VDR = 1.8V IOUT = 1.6 mA, VDR = 1.8V VOUT = 0V VOUT = VDR VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V 10 −10 5 2.0 0.8 DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO) POWER SUPPLY CHARACTERISTICS ADC14DS065 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Maximum Clock Frequency Minimum Clock Frequency Conditions In Single-Lane Mode In Dual-Lane Mode In Single-Lane Mode In Dual-Lane Mode Single-Lane Mode Dual-Lane, Offset Mode Dual-Lane, Word Aligned Mode 0.6 0.1 Typical (Note 10) Limits 65 25 52.5 7.5 8 9 Units (Limits) MHz (max) MHz (min) tCONV tAD tAJ Conversion Latency Aperture Delay Aperture Jitter Clock Cycles ns ps rms 9 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS065 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) mV (min) mV (max) mV (max) V (min) V (max) mV (max) mA (max) LVDS DC CHARACTERISTICS VOD delta VOD VOS Output Differential Voltage (SDO+) - (SDO-) Output Differential Voltage Unbalance Offset Voltage RL = 100Ω RL = 100Ω RL = 100Ω RL = 100Ω DO = 0V, VIN = 1.1V, Single-Lane Mode Dual-Lane Mode -10 1.1 2.2 350 900 350 900 15.4 30.8 50 50% to 50% CL=5pF to GND, ROUT=100Ω From rising edge of CLKL to ORA/ORB valid RL=100Ω TBD TBD 4 TBD TBD 45 55 1.25 350 250 450 ±25 1.125 1.375 ±25 delta VOS Offset Voltage Unbalance IOS Output Short Circuit Current LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS tDP tHO tSUO tFP tFDC tDFS tR, tF tODOR tDLD tSD Output Data Bit Period ns ps ps ns % (min) % (max) ps (max) ps (max) ns µs ns Output Data Edge to Output Clock Edge Single-Lane Mode Hold Time (Note 13) Dual-Lane Mode Output Data Edge to Output Clock Edge Single-Lane Mode Set-Up Time (Note 13) Dual-Lane Mode Frame Period Frame Clock Duty Cycle (Note 13) Data Edge to Frame Edge Skew LVDS Rise/Fall Time Output Delay of OR output Serializer DLL Lock Time Serializer Delay Single-Lane Mode Dual-Lane Mode www.national.com 10 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS080 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) Bits (min) LSB (max) LSB (min) LSB (max) LSB (min) 0 16383 1.45 1.55 1.4 1.6 V (min) V (max) V (min) V (max) pF pF 1.176 1.224 V (min) V (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL Integral Non Linearity (Note 11) Differential Non Linearity Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO VCM CIN VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to GND) (Note 12) External Reference Voltage VIN = 1.5 Vdc ± 0.5 V (CLK LOW) (CLK HIGH) 1.5 1.5 8.5 3.5 1.20 ±1.5 ±0.5 0 16383 14 11 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS080 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) GHz dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz H3 Third Harmonic Distortion fIN = 70 MHz fIN = 170 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 170 MHz 1.0 74.2 72 72 90 88 83 12 11.6 11.6 −88 −85 −80 −100 −95 −85 −90 −88 −83 74 71.8 71.4 www.national.com 12 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS080 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA pF 1.2 0.4 −10 10 5 Full Operation Full Operation 200 56 845 30 V (min) V (max) mA mA pF mA (max) mA mW (max) mW DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC) VIN(1) VIN(0) IIN(1) IIN(0) CIN VOUT(1) VOUT(0) +ISC −ISC COUT IA IDR Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance Analog Supply Current Digital Output Supply Current Power Consumption Power Down Power Consumption IOUT = −0.5 mA , VDR = 1.8V IOUT = 1.6 mA, VDR = 1.8V VOUT = 0V VOUT = VDR VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V 10 −10 5 2.0 0.8 DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO) POWER SUPPLY CHARACTERISTICS ADC14DS080 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Maximum Clock Frequency Minimum Clock Frequency Conditions In Single-Lane Mode In Dual-Lane Mode In Single-Lane Mode In Dual-Lane Mode Single-Lane Mode Dual-Lane, Offset Mode Dual-Lane, Word Aligned Mode 0.6 0.1 Typical (Note 10) Limits 65 80 25 52.5 7.5 8 9 Units (Limits) MHz (max) MHz (min) tCONV tAD tAJ Conversion Latency Aperture Delay Aperture Jitter Clock Cycles ns ps rms 13 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS080 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) mV (min) mV (max) mV (max) V (min) V (max) mV (max) mA (max) LVDS DC CHARACTERISTICS VOD delta VOD VOS Output Differential Voltage (SDO+) - (SDO-) Output Differential Voltage Unbalance Offset Voltage RL = 100Ω RL = 100Ω RL = 100Ω RL = 100Ω DO = 0V, VIN = 1.1V, Single-Lane Mode Dual-Lane Mode -10 0.89 1.79 245 690 245 690 12.5 25 50 50% to 50% CL=5pF to GND, ROUT=100Ω From rising edge of CLKL to ORA/ORB valid RL=100Ω TBD TBD 4 TBD TBD 45 55 1.25 350 250 450 ±25 1.125 1.375 ±25 delta VOS Offset Voltage Unbalance IOS Output Short Circuit Current LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS tDP tHO tSUO tFP tFDC tDFS tR, tF tODOR tDLD tSD Output Data Bit Period ns ps ps ns % (min) % (max) ps (max) ps (max) ns µs ns Output Data Edge to Output Clock Edge Single-Lane Mode Hold Time (Note 13) Dual-Lane Mode Output Data Edge to Output Clock Edge Single-Lane Mode Set-Up Time (Note 13) Dual-Lane Mode Frame Period Frame Clock Duty Cycle (Note 13) Data Edge to Frame Edge Skew LVDS Rise/Fall Time Output Delay of OR output Serializer DLL Lock Time Serializer Delay Single-Lane Mode Dual-Lane Mode www.national.com 14 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS095 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) 14 ±1.5 ±0.5 0 16383 0 16383 1.45 1.55 1.4 1.6 V (min) V (max) V (min) V (max) pF pF 1.176 1.224 V (min) V (max) Units (Limits) Bits (min) LSB (max) LSB (min) LSB (max) LSB (min) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL Integral Non Linearity (Note 11) Differential Non Linearity Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO VCM CIN VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc (Note 12) ± 0.5 V External Reference Voltage (CLK LOW) (CLK HIGH) 1.5 1.5 8.5 3.5 1.20 ADC14DS095 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) GHz dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 240 MHz 1.0 73.7 72 72 90 88 83 11.9 11.6 11.6 −88 −85 −80 -95 −90 −85 15 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Symbol Parameter Conditions fIN = 10 MHz Typical Limits (Note 10) −90 −88 −83 73.5 71.7 71.6 Units (Limits) (Note 2) dBFS dBFS dBFS dBFS dBFS dBFS H3 Third Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 240 MHz ADC14DS095 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA pF 1.2 0.4 −10 10 5 Full Operation Full Operation 235 68 1000 33 V (min) V (max) mA mA pF mA (max) mA mW (max) mW DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC) VIN(1) VIN(0) IIN(1) IIN(0) CIN VOUT(1) VOUT(0) +ISC −ISC COUT IA IDR Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance Analog Supply Current Digital Output Supply Current Power Consumption Power Down Power Consumption IOUT = −0.5 mA , VDR = 1.8V IOUT = 1.6 mA, VDR = 1.8V VOUT = 0V VOUT = VDR VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V 10 −10 5 2.0 0.8 DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO) POWER SUPPLY CHARACTERISTICS ADC14DS095 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Maximum Clock Frequency Minimum Clock Frequency Conditions In Single-Lane Mode In Dual-Lane Mode In Single-Lane Mode In Dual-Lane Mode Single-Lane Mode Dual-Lane, Offset Mode Dual-Lane, Word Aligned Mode 0.6 0.1 Typical (Note 10) Limits 65 95 25 52.5 7.5 8 9 Units (Limits) MHz (max) MHz (min) tCONV tAD tAJ Conversion Latency Aperture Delay Aperture Jitter Clock Cycles ns ps rms www.national.com 16 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS095 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) mV (min) mV (max) mV (max) V (min) V (max) mV (max) mA (max) LVDS DC CHARACTERISTICS VOD delta VOD VOS Output Differential Voltage (SDO+) - (SDO-) Output Differential Voltage Unbalance Offset Voltage RL = 100Ω RL = 100Ω RL = 100Ω RL = 100Ω DO = 0V, VIN = 1.1V, Single-Lane Mode Dual-Lane Mode -10 0.75 1.5 175 550 175 550 10.53 21.05 50 50% to 50% CL=5pF to GND, ROUT=100Ω From rising edge of CLKL to ORA/ORB valid RL=100Ω TBD TBD 4 TBD TBD 45 55 1.25 350 250 450 ±25 1.125 1.375 ±25 delta VOS Offset Voltage Unbalance IOS Output Short Circuit Current LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS tDP tHO tSUO tFP tFDC tDFS tR, tF tODOR tDLD tSD Output Data Bit Period ns ps ps ns % (min) % (max) ps (max) ps (max) ns µs ns Output Data Edge to Output Clock Edge Single-Lane Mode Hold Time (Note 13) Dual-Lane Mode Output Data Edge to Output Clock Edge Single-Lane Mode Set-Up Time (Note 13) Dual-Lane Mode Frame Period Frame Clock Duty Cycle (Note 13) Data Edge to Frame Edge Skew LVDS Rise/Fall Time Output Delay of OR output Serializer DLL Lock Time Serializer Delay Single-Lane Mode Dual-Lane Mode 17 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS105 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) 14 ±1.5 ±0.5 0 16383 0 16383 1.45 1.55 1.4 1.6 V (min) V (max) V (min) V (max) pF pF 1.176 1.224 V (min) V (max) Units (Limits) Bits (min) LSB (max) LSB (min) LSB (max) LSB (min) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL Integral Non Linearity (Note 11) Differential Non Linearity Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO VCM CIN VREF Common Mode Output Voltage Analog Input Common Mode Voltage VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc (Note 12) ± 0.5 V External Reference Voltage (CLK LOW) (CLK HIGH) 1.5 1.5 8.5 3.5 1.20 ADC14DS105 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) GHz dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio -1 dBFS Input, −3 dB Corner fIN = 10 MHz fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz ENOB Effective Number of Bits fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz THD Total Harmonic Disortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz H2 Second Harmonic Distortion fIN = 70 MHz fIN = 240 MHz 1.0 73 72.5 72 88 85 83 11.8 11.7 11.6 −86 −85 −80 −95 −90 −85 www.national.com 18 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Symbol Parameter Conditions fIN = 10 MHz Typical Limits (Note 10) −88 −85 −83 72.8 72.3 71.4 Units (Limits) (Note 2) dBFS dBFS dBFS dBFS dBFS dBFS H3 Third Harmonic Distortion fIN = 70 MHz fIN = 240 MHz fIN = 10 MHz SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz fIN = 240 MHz ADC14DS105 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) V (min) V (max) µA µA pF 1.2 0.4 −10 10 5 Full Operation Full Operation Clock disabled 250 71 1060 33 V (min) V (max) mA mA pF mA (max) mA mW (max) mW DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC) VIN(1) VIN(0) IIN(1) IIN(0) CIN VOUT(1) VOUT(0) +ISC −ISC COUT IA IDR Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Digital Input Capacitance Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Source Current Output Short Circuit Sink Current Digital Output Capacitance Analog Supply Current Digital Output Supply Current Power Consumption Power Down Power Consumption IOUT = −0.5 mA , VDR = 1.8V IOUT = 1.6 mA, VDR = 1.8V VOUT = 0V VOUT = VDR VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V 10 −10 5 2.0 0.8 DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO) POWER SUPPLY CHARACTERISTICS ADC14DS105 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Maximum Clock Frequency Minimum Clock Frequency Conditions In Single-Lane Mode In Dual-Lane Mode In Single-Lane Mode In Dual-Lane Mode Single-Lane Mode Dual-Lane, Offset Mode Dual-Lane, Word Aligned Mode 0.6 0.1 Typical (Note 10) Limits 65 105 25 52.5 7.5 8 9 Units (Limits) MHz (max) MHz (min) tCONV tAD tAJ Conversion Latency Aperture Delay Aperture Jitter Clock Cycles ns ps rms 19 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 ADC14DS105 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.3V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) mV (min) mV (max) mV (max) V (min) V (max) mV (max) mA (max) LVDS DC CHARACTERISTICS VOD delta VOD VOS Output Differential Voltage (SDO+) - (SDO-) Output Differential Voltage Unbalance Offset Voltage RL = 100Ω RL = 100Ω RL = 100Ω RL = 100Ω DO = 0V, VIN = 1.1V, Single-Lane Mode Dual-Lane Mode -10 0.68 1.36 140 480 140 480 9.52 19.05 50 50% to 50% CL=5pF to GND, ROUT=100Ω From rising edge of CLKL to ORA/ORB valid RL=100Ω TBD TBD 4 TBD TBD 45 55 1.25 350 250 450 ±25 1.125 1.375 ±25 delta VOS Offset Voltage Unbalance IOS Output Short Circuit Current LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS tDP tHO tSUO tFP tFDC tDFS tR, tF tODOR tDLD tSD Output Data Bit Period ns ps ps ns % (min) % (max) ps (max) ps (max) ns µs ns Output Data Edge to Output Clock Edge Single-Lane Mode Hold Time (Note 13) Dual-Lane Mode Output Data Edge to Output Clock Edge Single-Lane Mode Set-Up Time (Note 13) Dual-Lane Mode Frame Period Frame Clock Duty Cycle (Note 13) Data Edge to Frame Edge Skew LVDS Rise/Fall Time Output Delay of OR output Serializer DLL Lock Time Serializer Delay Single-Lane Mode Dual-Lane Mode Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal. Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10. Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. 20211211 Note 9: With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV. www.national.com 20 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance. Note 13: This parameter is guaranteed by design and/or characterization and is not tested in production. 21 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. LVDS Differential Output Voltage (VOD) is the absolute value of the difference between the differential output pair voltages (VD+ and VD-), each measured with respect to ground. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC14DS065 is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition from code 8191 to 8192. OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the FullScale output of the ADC with the supply at the maximum DC supply limit, expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input www.national.com 22 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. Timing Diagrams 20211214 FIGURE 1. Serial Output Data Timing 20211217 FIGURE 2. Serial Output Data Format in Single-Lane Mode 23 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 20211218 FIGURE 3. Serial Output Data Format in Dual-Lane Mode www.national.com 24 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Transfer Characteristic 20211210 FIGURE 4. Transfer Characteristic 25 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Functional Description Operating on a single +3.3V supply, the ADC14DS065/080/095/105 digitizes two differential analog input signals to 14 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. Serial Output Data Format : The digital data for each channel is provided in a serial format. Two modes of operation are available for the serial data format. Single-lane serial format (shown in Figure 2) uses one set of differential data signals per channel. Dual-lane serial format (shown in Figure 3) uses two sets of differential data signals per channel in order to slow down the data and clock frequency by a factor of 2. At slower rates of operation (typically below 65 MSPS) the single-lane mode may the most efficient to use. At higher rates the user may want to employ the dual-lane scheme. In either case DDR-type clocking is used. For each data channel, an overrange indication is also provided. The OR signal is updated with each frame of data. Serial Control Interface The ADC14DS065/080/095/105 has a serial interface that allows access to the control registers. The serial interface is a generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers and DSP controllers. Each serial interface access cycle is exactly 16 bits long. A register-write can be accomplished in one cycle - with the data field returning the contents of the register addressed in the command field of the same cycle. A random access register-read requires 2 cycles - one to load the address and the second to read the register addressed in the previous cycle. Register space supported by this interface is 16, although only a subset is implemented in this device. Figure 5 shows the access protocol used by this interface. Each signal's function is described below. 20211219 FIGURE 5. Serial Interface Protocol Signal Descriptions: SCLK: Used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. User may disable clock and hold it in the low-state, as long as clock pulse-width min spec is not violated when clock is enabled or disabled. SCSb: Serial Interface Chip Select. Each assertion starts a new register access - i.e., the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the case of a write operawww.national.com 26 tion, writes the addressed register. There is a minimum pulsewidth requirement for the deasserted pulse - which is specified in the Electrical Specifications section. SDI: Serial Data. Must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long. ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 R/Wb: A value of '1' indicates a read operation, while a value of '0' indicates a write operation. Reserved: Reserved for future use. Must be set to 0. ADDR: Up to 16 registers can be addressed. DATA: In a write operation the value in this field will be written to the register addressed in this cycle when SCSb is deasserted. In a read operation this field is ignored. SDO: This output is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h. Device Control Register, Address 0h 76 5 4 3 2 1 0 OM DLE DCS DF WAM PD_A PD_B Bits (7:6) Operational Mode 0 0 Normal Operation. 0 1 Test Output mode. A fixed test pattern (10100110001110 msb->lsb) is sourced at the data outputs. 1 0 Test Output mode. Data pattern defined by user in registers 01h and 02h is sourced at data outputs. 1 1 Reserved. Bit 5 Data Lane Configuration. When this bit is set to '0', the serial data interface is configured for dual-lane mode where the data words are output on two data outputs (SD1 and SD0) at half the rate of the single-lane interface. When this bit is set to ‘1’, serial data is output on the SD1 output only and the SD0 outputs are held in a high-impedance state Duty Cycle Stabilizer. When this bit is set to '0' the DCS is off. When this bit is set to ‘1’, the DCS is on. Data Format. When this bit is set to ‘1’ the data output is in the “twos complement” form. When this bit is set to ‘0’ the data output is in the “offset binary” form. Bit 2 Word Alignment Mode. This bit must be set to '0' in the single-lane mode of operation. In dual-lane mode, when this bit is set to '0' the serial data words are offset by half-word. This gives the least latency through the device. When this bit is set to '1' the serial data words are in word-aligned mode. In this mode the serial data on the SD1 lane is additionally delayed by one CLK cycle. (Refer to Figure 3). Power-Down Channel A. When this bit is set to '1', Channel A is in power-down state and Normal operation is suspended. Power-Down Channel B. When this bit is set to '1', Channel B is in power-down state and Normal operation is suspended. Bit 1 Bit 0 Reset State : 08h User Test Pattern Register 0, Address 1h 7 6 5 4 3 2 1 0 Reserved User Test Pattern (13:8) Bits (7:6) Reserved. Must be set to '0'. Bits (5:0) User Test Pattern. Most-significant 6 bits of the 14-bit pattern that will be sourced out of the data outputs in Test Output Mode. Reset State : 00h User Test Pattern Register 1, Address 2h 76543210 User Test Pattern (7:0) Bits (7:0) User Test Pattern. Least-significant 8 bits of the 14-bit pattern that will be sourced out of the data outputs in Test Output Mode. Reset State : 00h Bit 4 Bit 3 27 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Physical Dimensions inches (millimeters) unless otherwise noted TOP View...............................SIDE View...............................BOTTOM View 60-Lead LLP Package Ordering Numbers: ADC14DS065CISQ / ADC14DS080CISQ / ADC14DS095CISQ / ADC14DS105CISQ NS Package Number SQA60A www.national.com 28 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Notes 29 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Dual 14-Bit A/D Converter Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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