CD40174BC

CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop February 1988 CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop General Description The CD40174B consists of six positive-edge triggered D-type flip-flops the true outputs from each flip-flop are externally available The CD40175B consists of four positiveedge triggered D-type flip-flops both the true and complement outputs from each flip-flop are externally available All flip-flops are controlled by a common clock and a common clear Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse The clearing operation enabled by a negative pulse at Clear input clears all Q outputs to logical ‘‘0’’ and Qs (CD40175B only) to logical ‘‘1’’ All inputs are protected from static discharge by diode clamps to VDD and VSS Features Y Y Y Y Y Wide supply voltage range 3V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74 LS Equivalent to MC14174B MC14175B Equivalent to MM74C174 MM74C175 Connection Diagrams CD40174B Dual-In-Line Package CD40175B Dual-In-Line Package TL F 5987 – 1 TL F 5987 – 2 Top View Order Number CD40174B or CD40175B Top View Truth Table Inputs Clear L H H H H H L X NC e e e e e e Outputs D X H L X X Q L H L NC NC Q H L H NC NC Clock X u u H L u High level Low level Irrelevant Transition from low to high level No change Q for CD40175B only C1995 National Semiconductor Corporation TL F 5987 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5V to a 18V b 0 5V to VDD a 0 5VDC b 65 C to a 150 C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD40XXXBM CD40XXXBC 3V to 15 VDC 0V to VDD VDC b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 260 C CD40175BM (Note 2) b 55 C a 25 C a 125 C DC Electrical Characteristics CD40174BM Symbol IDD Parameter Quiescent Device Current Conditions Units mA mA mA V V V V V V Min VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS Max 10 20 40 0 05 0 05 0 05 Min Typ Max 10 20 40 0 05 0 05 0 05 Min Max 30 60 120 0 05 0 05 0 05 VOL Low Level Output Voltage l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V 35 70 11 0 0 64 16 42 b 0 64 b1 6 b4 2 VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 4 95 9 95 14 95 5 10 15 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 VIL Low Level Input Voltage V V V V V V mA mA mA mA mA mA VIH High Level Input Voltage 35 70 11 0 0 51 13 34 0 88 2 25 88 IOL Low Level Output Current (Note 3) 0 36 09 24 b 0 36 b0 9 b2 4 b1 0 IOH High Level Output Current VDD e 5V VO e 4 6V (Note 3) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V b 0 51 b 0 8 8 b 1 3 b 2 25 b3 4 b8 8 b0 1 b 10 b 5 b 0 1 IIN 01 CD40175BC (Note 2) b 40 C 10b5 01 10 mA mA DC Electrical Characteristics CD40174BC Symbol IDD Parameter Quiescent Device Current Conditions a 25 C a 85 C Units mA mA mA Min VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS Max 4 8 16 Min Typ Max 4 8 16 Min Max 30 60 120 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 2 DC Electrical Characteristics CD40174BC Symbol VOL Parameter Conditions CD40175BC (Note 2) (Continued) b 40 C a 25 C a 85 C Units V V V V V V Min Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V Low Level Input Voltage VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V 35 70 11 0 0 52 13 36 b 0 52 b1 3 b3 6 Max 0 05 0 05 0 05 Min Typ Max 0 05 0 05 0 05 Min Max 0 05 0 05 0 05 VOH 4 95 9 95 14 95 15 30 40 4 95 9 95 14 95 5 10 15 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 VIL V V V V V V mA mA mA mA mA mA VIH High Level Input Voltage 35 70 11 0 0 44 11 30 0 88 2 25 88 IOL Low Level Output Current VDD e 5V VO e 0 4V (Note 3) VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V High Level Output Current VDD e 5V VO e 4 6V (Note 3) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V 0 36 09 24 b 0 36 b0 9 b2 4 b1 0 IOH b 0 44 b 0 88 b 1 1 b 2 25 b3 0 b8 8 b 0 30 b 10 b 5 b 0 30 IIN 0 30 10b5 0 30 10 mA mA AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k and tr e tf e 20 ns unless otherwise specified Symbol tPHL tPLH Parameter Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q (CD40175 Only) Propagation Delay Time to a Logical ‘‘0’’ from Clear to Q Propagation Delay Time to a Logical ‘‘1’’ from Clear to Q (CD40175 Only) Time Prior to Clock Pulse that Data must be Present Time after Clock Pulse that Data Must be Held Transition Time Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Min Typ 190 75 60 180 70 60 230 90 75 45 15 13 b 11 b4 b3 Max 300 110 90 300 110 90 400 150 120 100 40 35 0 0 0 200 100 80 250 100 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tPHL tPLH tSU tH tTHL tTLH 100 50 40 130 45 40 tWH tWL Minimum Clock Pulse Width 3 AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k and tr e tf e 20 ns unless otherwise specified (Continued) Symbol tWL Parameter Minimum Clear Pulse Width Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Clear Input Other Input Per Package (Note 4) 15 50 50 15 50 50 20 50 60 50 50 50 35 10 12 10 50 130 15 75 Min Typ 120 45 40 Max 250 100 80 Units ns ns ns ms ms ms ms ms ms MHz MHz MHz pF pF pF tRCL Maximum Clock Rise Time tfCL Maximum Clock Fall Time fCL Maximum Clock Frequency CIN CPD Input Capacitance Power Dissipation AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time Note 4 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN-90 Switching Time Waveforms TL F 5987 – 3 tr e tf e 20 ns 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD40174BMJ CD40174BCJ CD40175BMJ or CD40175BCJ NS Package Number J16A 5 CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD40174BMN CD40174BCN CD40174BMN or CD40175BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications