CD4019BM

CD4019BM CD4019BC Quad AND-OR Select Gate February 1988 CD4019BM CD4019BC Quad AND-OR Select Gate General Description The CD4019BM CD4019BC is a complementary MOS quad AND-OR select gate Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors These complementary MOS (CMOS) transistors provide the building blocks for the 4 ‘‘AND-OR select’’ gate configurations each consisting of two 2-input AND gates driving a single 2-input OR gate Selection is accomplished by control bits KA and KB All inputs are protected against static discharge damage Features Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility 3 0V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS Applications Y Y Y Y AND-OR select gating Shift-right shift-left registers True complement selection AND OR EXCLUSIVE-OR selection Connection and Schematic Diagrams Dual-In-Line Package Order Number CD4019B TL F 5952 – 1 Top View Schematic diagram for 1 of 4 identical stages C1995 National Semiconductor Corporation TL F 5952 TL F 5952 – 2 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C Recommended Operation Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4019BM CD4019BC a 3V to a 15V 0V to VDD V b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 260 C DC Electrical Characteristics CD4019BM (Note 2) Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage Conditions VDD e 5V VDD e 10V VDD e 15V b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Max 0 25 05 10 0 05 0 05 0 05 Min Typ 0 03 0 05 0 07 0 0 0 Max 0 25 05 10 0 05 0 05 0 05 Min Max 75 15 30 0 05 0 05 0 05 VOL l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V 35 70 11 0 0 64 16 42 b 0 25 b 0 62 b1 8 VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 4 95 9 95 14 95 5 10 15 2 4 6 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 14 b 0 35 b1 1 b 0 10 b1 0 VIL Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) V V V V V V mA mA mA mA mA mA VIH 35 70 11 0 0 51 13 34 b0 2 b0 5 b1 5 b 0 10 3 6 9 1 25 10 b0 4 b1 0 b3 0 b 10 b 5 IOL IOH High Level Output VDD e 5V VO e 4 6V Current (Note 3) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V IIN 0 10 10b5 0 10 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 2 DC Electrical Characteristics CD4019BC (Note 2) Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage Conditions VDD e 5V VDD e 10V VDD e 15V b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Max 1 2 4 0 05 0 05 0 05 Min Typ 0 03 0 05 0 07 0 0 0 Max 1 2 4 0 05 0 05 0 05 Min Max 75 15 30 0 05 0 05 0 05 VOL l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V 35 70 11 0 0 52 13 36 b0 2 b0 5 b1 4 VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 4 95 9 95 14 95 5 10 15 2 4 6 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 12 b0 3 b1 0 b 0 30 b1 0 VIL Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) V V V V V V mA mA mA mA mA mA VIH 35 70 11 0 0 44 11 30 b 0 16 b0 4 b1 2 b 0 30 3 6 9 1 25 10 b0 4 b1 0 b3 0 b 10 b 5 IOL IOH High Level Output VDD e 5V VO e 4 6V Current (Note 3) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V IIN 0 30 10b5 0 30 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time AC Electrical Characteristics Symbol tPHL tPLH tTHL Parameter Propagation Delay Input to Output High-to-Low Level Transition Time Low-to-High Level Transition Time Input Capacitance TA e 25 C CL e 50 pF RL e 200k unless otherwise specified Conditions Min Typ 100 50 45 100 50 40 150 70 50 5 10 Max 300 120 100 200 100 80 300 140 100 75 15 Units ns ns ns ns ns ns ns ns ns pF pF VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V All A and B Inputs KA and KB Inputs tTLH CIN AC Parameters are guaranteed by DC correlated testing 3 CD4019BM CD4019BC Quad AND-OR Select Gate Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (J) Order Number CD4019BMJ or CD4019BCJ NS Package Number J16A Molded Dual-In-Line Package (N) Order Number CD4019BMN or CD4019BCN NS Package Number N16E LIFE SUPPORT POLICY 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