CD4027BC

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset February 1988 CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has independent J K set reset and clock inputs and buffered Q and Q outputs These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses Set or reset is independent of the clock and is accomplished by a high level on the respective input All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS Features Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Low power Medium speed operation 3 0V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS 50 nW (typ ) 12 MHz (typ ) with 10V supply Schematic and Connection Diagrams TL F 5958 – 1 Dual-In-Line Package Order Number CD4027B TL F 5958 – 2 Top View C1995 National Semiconductor Corporation TL F 5958 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 VDC to a 18 VDC DC Supply Voltage (VDD) b 0 5V to VDD a 0 5 VDC Input Voltage (VIN) b 65 C to a 150 C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4027BM CD4027BC 3V to 15 VDC 0V to VDD VDC b 55 C to a 125 C b 40 C to a 85 C DC Electrical Characteristics CD4027BM (Note 2) Symbol IDD Parameter Conditions b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Quiescent Device Current VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS Low Level Output Voltage Max 1 2 4 0 05 0 05 0 05 Min Typ Max 1 2 4 Min Max 30 60 120 0 05 0 05 0 05 VOL l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 64 16 42 b 0 64 b1 6 b4 2 0 0 0 4 95 9 95 14 95 5 10 15 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 VIL Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current 15 30 40 35 70 11 0 V V V V V V mA mA mA mA mA mA VIH 35 70 11 0 0 51 13 34 b 0 51 b1 3 b3 4 b0 1 IOL 0 88 2 25 88 b 0 88 b 2 25 b8 8 b 10 b 5 b 0 1 0 36 09 24 b 0 36 b0 9 b2 4 b1 0 IOH IIN 01 10b5 01 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 2 DC Electrical Characteristics CD4027BC (Note 2) Symbol IDD Parameter Conditions b 40 C a 25 C a 85 C Units mA mA mA V V V V V V Min Quiescent Device Current VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS Low Level Output Voltage Max 4 8 16 0 05 0 05 0 05 Min Typ Max 4 8 16 Min Max 30 60 120 0 05 0 05 0 05 VOL l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 52 13 36 b 0 52 b1 3 b3 6 0 0 0 4 95 9 95 14 95 5 10 15 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 VIL Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current 15 30 40 35 70 11 0 V V V V V V mA mA mA mA mA mA VIH 35 70 11 0 0 44 11 30 b 0 44 b1 1 b3 0 b0 3 IOL 0 88 2 25 88 b 0 88 b 2 25 b8 8 b 10 b 5 b 0 3 0 36 09 24 b 0 36 b0 9 b2 4 b1 0 IOH IIN 03 10b5 03 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 3 AC Electrical Characteristics Symbol tPHL or tPLH Parameter Propagation Delay Time from Clock to Q or Q Propagation Delay Time from Set to Q or Reset to Q Propagation Delay Time from Set to Q or Reset to Q Minimum Data Setup Time TA e 25 C CL e 50 pF trCL e tfCL e 20 ns unless otherwise specified Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Any Input Per Flip-Flop (Note 4) 25 62 76 15 10 5 100 40 32 80 30 25 5 35 200 80 65 160 60 50 75 Min Typ 200 80 65 170 70 55 110 50 40 135 55 45 100 50 40 5 12 5 15 5 Max 400 160 130 340 140 110 220 100 80 270 110 90 200 100 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ms ms ms ns ns ns ns ns ns pF pF tPHL or tPLH tPHL or tPLH tS tTHL or tTLH Transition Time fCL Maximum Clock Frequency (Toggle Mode) Maximum Clock Rise and Fall Time Minimum Clock Pulse Width (tWH e tWL) Minimum Set and Reset Pulse Width Average Input Capacitance Power Dissipation Capacity trCL or tfCL tW tWH CIN CPD AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time Note 4 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN-90 4 Typical Applications Ripple Binary Counters TL F 5958 – 3 Shift Registers TL F 5958 – 4 Truth Table  tnb1 Inputs CL U L L L L K X X X Where X t Outputs n J I X O X X X X X K X O X I X X X X S O O O O O I O I R O O O O O O I I Q O I O I X X X X Q I I O O I O I Q O O I I (No Change) O I I I e High Level O e Low Level U e Level Change X e Don’t Care  e tnb1 refers to the time interval prior to the positive clock pulse transition X e tn refers to the time intervals after the positive clock pulse transition 5 CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4027BMJ or CD4027BCJ NS Package Number J16A Molded Dual-In-Line Package (N) Order Number CD4027BMN or CD4027BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications