CD4031BC

CD4031BM CD4031BC 64-Stage Static Shift Register February 1988 CD4031BM CD4031BC 64-Stage Static Shift Register General Description The CD4031BM CD4031BC is an integrated complementary MOS (CMOS) 64-stage fully static shift register Two data inputs DATA IN and RECIRCULATE IN and a MODE CONTROL input are provided Data at the DATA input (when MODE CONTROL is low) or data at the RECIRCULATE input (when MODE CONTROL is high) which meets the setup and hold time requirements is entered into the first stage of the register and is shifted one stage at each positive transition of the CLOCK Data output is available in both true and complement forms from the 64th stage Both the DATA OUT (Q) AND DATA OUT (Q) outputs are fully buffered The CLOCK input of the CD4031BM CD4031BC is fully buffered and present only a standard input load capacitance However a DELAYED CLOCK OUTPUT (CLD) has been provided to allow reduced clock drive fan-out and transition time requirements when cascading packages Features Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Fully static operation Y Y Y Y Y Y 3 0V to 15V 0 45 VDD (typ ) fan out of 2 driving 74L or 1 driving 74LS DC to 8 MHz VDD e 10V (typ ) Fully buffered clock input 5 pF (typ ) input capacitance Single phase clocking requirements Delayed clock output for reduced clock drive requirements Fully buffered outputs High current sinking capability 1 6 mA Q output VDD e 5V and 25 C Logic and Connection Diagrams TL F 5962 – 1 Dual-In-Line Package Order Number CD4031B Top View C1995 National Semiconductor Corporation TL F 5962 TL F 5962 – 2 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to a 18V Supply Voltage (VDD) b 0 5V to VDD a 0 5V Input Voltage (VIN) b 65 C to a 150 C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temp (TL) (Soldering 10 sec ) 260 C Recommended Operating Conditions (Note 2) Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4031BM CD4031BC 3V to 15V 0V to VDD b 55 C to a 125 C b 40 C to a 85 C DC Electrical Characteristics (Note 2) CD4031BM Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current Q Output (Note 3) Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Max 5 10 20 0 05 0 05 0 05 Min Typ 0 01 0 01 0 02 0 0 0 Max 5 10 20 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL VOH VIL VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V ( ( VIH e VDD VIL e 0V lIOl k 1 mA 4 95 VIH e VDD VIL e 0V lIOl k 1 mA 9 95 14 95 4 95 9 95 14 95 15 30 40 5 10 15 2 25 45 6 75 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 13 28 61 0 36 09 24 b 0 36 b0 9 b2 4 VIH IOL IOL Low Level Output VDD e 5V VO e 0 4V Current Q and CLD VDD e 10V VO e 0 5V Outputs (Note 3) VD e 15V VO e 1 5V High Level Output Current All Outputs (Note 3) Input Current IOH VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V IIN ( ( ( ( (l l l IO l k 1 m A IO k 1 m A 35 70 11 0 23 51 10 5 0 64 16 42 b 0 64 b1 6 b4 2 V V V V V V mA mA mA mA mA mA mA mA mA 35 70 11 0 19 42 88 0 51 13 34 2 75 55 8 25 38 84 17 0 88 2 25 88 VIH e VDD VIL e 0V VIH e VDD VIL e 0V VIH e VDD VIL e 0V b 0 51 b 0 88 b 1 3 b 2 25 b3 4 b8 8 b0 1 b 10 b 5 b 0 1 b 1 0 mA 01 10b5 01 10 mA Truth Tables Mode Control (Data Selection) Mode Control 0 0 1 1 X e irrelevant Each Stage Data Into First Stage 0 1 0 1 K e High to Low level transition Data In 0 1 X X Recirculate In X X 0 1 Dn 0 1 X CL L L K Qn 0 1 NC NC e no change L e Low to High level transition 2 DC Electrical Characteristics (Note 2) CD4031BC Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current Q Output (Note 3) Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V b 40 C a 25 C a 85 C Units mA mA mA V V V V V V Min Max 20 40 80 0 05 0 05 0 05 Min Typ 0 01 0 01 0 02 0 0 0 Max 20 40 80 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL VOH VIL VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V ( ( VIH e VDD VIL e 0V lIOl k 1 mA 4 95 VIH e VDD VIL e 0V lIOl k 1 mA 9 95 14 95 4 95 9 95 14 95 15 30 40 5 10 15 2 25 45 6 75 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 13 28 61 0 36 09 24 b 0 36 b0 9 b2 4 VIH IOL IOL Low Level Output VDD e 5V VO e 0 4V Current Q and CLD VDD e 10V VO e 0 5V Outputs VDD e 15V VO e 1 5V (Note 3) ( ( ( (l l IO l k 1 m A IO l k 1 m A 35 70 11 0 18 40 87 0 52 13 36 b 0 52 b1 3 b3 0 V V V V V V mA mA mA mA mA mA mA mA mA 35 70 11 0 16 35 75 0 44 11 30 2 75 55 8 25 38 84 17 0 88 2 25 88 VIH e VDD VIL e 0V VIH e VDD VIL e 0V IOH High Level Output VDD e 5V VO e 4 6V Current All Outputs VDD e 10V VO e 9 5V (Note 3) VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V IIN ( VIH e VDD VIL e 0V b 0 44 b 0 88 b 1 1 b 2 25 b3 0 b8 8 b0 3 b 10 b 5 b 0 3 b 1 0 mA 03 10b5 03 10 mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time Switching Time Waveforms TL F 5962 – 3 3 AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k Input tr e tf e 20 ns unless otherwise specified Symbol tPHL tPLH Parameter Propagation Delay Time Clock to Q and Q Conditions VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V Any Input 16 40 50 15 10 5 5 75 Min Typ 300 125 100 125 60 50 100 50 40 100 50 40 100 50 40 150 60 50 32 80 10 Max 600 250 200 250 125 100 200 100 80 200 100 80 200 100 80 30 125 100 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ms ms ms pF tPHL tPLH Propagation Delay Time Clock to CLD tTHL tTLH Output Transition Time All Outputs tSU0 tSU1 tH0 tH1 tWL tWH Minimum Data Setup Time DATA IN or RECIRCULATE IN to Clock Minimum Data Hold Time Clock to DATA IN or RECIRCULATE IN Minimum Clock Pulse Width fCL Maximum Clock Frequency tRCL tFCL Maximum Clock Input Rise and Fall Times (Note 4) Input Capacitance CIN AC Parameters are guaranteed by DC correlated testing Note 4 When clocking cascaded packages in parallel one should insure that tr CL s 2 (tPD b tH) where tPD e the propagation delay of the driving stage and tH e the hold time of the driven stage Block Diagram cascading packages using DELAYED CLOCK (CLD) output TL F 5962 – 4 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4031BMJ or CD4031BCJ NS Package Number J16A 5 CD4031BM CD4031BC 64-Stage Static Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD4031BMN or CD4031BCN NS Package Number N16E LIFE SUPPORT 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0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications