CD4035BC

CD4035BM CD4035BC 4-Bit Parallel-In Parallel-Out Shift Register February 1988 CD4035BM CD4035BC 4-Bit Parallel-In Parallel-Out Shift Register General Description The CD4035B 4-bit parallel-in parallel-out shift register is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors This shift register is a 4-stage clocked serial register having provisions for synchronous parallel inputs to each stage and serial inputs to the first stage via JK logic Register stages 2 3 and 4 are coupled in a serial ‘‘D’’ flipflop configuration when the register is in the serial mode (parallel serial control low) Parallel entry via the ‘‘D’’ line of each register stage is permitted only when the parallel serial control is ‘‘high’’ In the parallel or serial mode information is transferred on positive clock transitions When the true complement control is ‘‘high’’ the true contents of the register are available at the output terminals When the true complement control is ‘‘low’’ the outputs are the complements of the data in the register The true complement control functions asynchronously with respect to the clock signal JK input logic is provided on the first stage serial input to minimize logic requirements particularly in counting and sequence-generation applications With JK inputs connected together the first stage becomes a ‘‘D’’ flip-flop An asynchronous common reset is also provided Features Y Y Y Y Y Y Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 4-stage clocked operation Synchronous parallel entry on all 4 stages JK inputs on first stage Asynchronous true complement control on all outputs Reset control Static flip-flop operation master slave configuration Buffered outputs Low power dissipation 5 mW (typ ) (ceramic) High speed to 5 MHz Applications Y Y Y Y Automotive Data terminals Instrumentation Medical electronics Y Y Y Y Alarm systems Industrial controls Remote metering Computers Logic Diagram TL F 5964 – 1 P S e 0 e serial mode T C e 1 e true outputs TG e transmission gate Input to output is a) A bidirectional low impedance when control input 1 is low and control input 2 is high b) An open circuit when control input 1 is high and control input 2 is low TL F 5964– 2 C1995 National Semiconductor Corporation TL F 5964 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C Lead Temperature (TL) (Soldering 10 seconds) 260 C Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4035BM CD4035BC 3V to 15V 0V to VDDV b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW DC Electrical Characteristics CD4035BM (Note 2) Symbol IDD Parameter Conditions b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Quiescent Device Current VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS Low Level Output Voltage Max 5 10 20 0 05 0 05 0 05 Min Typ 03 05 10 0 0 0 Max 5 10 20 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL l IO l k 1 0 m A VDD e 5V VDD e 10V VDD e 15V 4 95 9 95 14 95 VOH High Level Output Voltage lIOl k 1 0 mA VDD e 5V VDD e 10V VDD e 15V Low Level Input Voltage 4 95 9 95 14 95 15 30 40 5 10 15 15 30 40 4 95 9 95 14 95 15 30 40 35 70 11 0 VIL l IO l k 1 0 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V l IO l k 1 0 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VO e 0 4V VO e 0 5V VO e 1 5V VO e 4 6V VO e 9 5V VO e 13 5V VIN e 0V VIN e 15V 35 70 11 0 0 64 16 42 b 0 25 b 0 62 b1 8 V V V V V V mA mA mA mA mA mA VIH High Level Input Voltage 35 70 11 0 0 51 13 34 b0 2 b0 5 b1 5 b0 1 IOL Low Level Output Current VDD e 5V (Note 3) VDD e 10V VDD e 15V High Level Output Current VDD e 5V (Note 3) VDD e 10V VDD e 15V Input Current VDD e 15V VDD e 15V 0 88 2 25 88 0 36 09 b3 5 b 10 b 5 b 0 1 0 36 09 24 b 0 14 b 0 35 b1 1 b1 0 IOH IIN 01 10b5 01 10 mA mA DC Electrical Characteristics CD4035BC (Note 2) Symbol IDD Parameter Quiescent Device Current Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS b 40 C a 25 C a 85 C Units mA mA mA V V V V V V Min Max 20 40 80 0 05 0 05 0 05 Min Typ 05 10 50 0 0 0 Max 20 40 80 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL Low Level Output Voltage l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V 2 4 95 9 95 14 95 VOH High Level Output Voltage 4 95 9 95 14 95 5 10 15 4 95 9 95 14 95 DC Electrical Characteristics CD4035BC (Note 2) (Continued) Symbol VIL Parameter Low Level Input Voltage Conditions b 40 C 25 C Min Typ Max 15 30 40 35 70 11 0 0 44 11 30 b 0 16 b0 4 b1 2 85 C Min Max 15 30 40 35 70 11 0 Units Min Max 15 30 40 l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V l IO l k 1 m A VDD e 5V VDD e 10V VDD e 15V VO e 0 5V or 4 5V VO e 1 0V or 9 0V VO e 1 5V or 13 5V VO e 0 5V or 4 5V 3 5 VO e 1 0V or 9 0V 7 0 VO e 1 5V or 13 5V 11 0 VO e 0 4V VO e 0 5V VO e 1 5V VO e 4 6V VO e 9 5V VO e 13 5V VIN e 0V VIN e 15V 0 52 13 36 b0 2 b0 5 b1 4 V V V V V V mA mA mA mA mA mA VIH High Level Input Voltage IOL Low Level Output Current VDD e 5V (Note 3) VDD e 10V VDD e 15V High Level Output Current VDD e 5V (Note 3) VDD e 10V VDD e 15V Input Current VDD e 15V VDD e 15V 0 88 2 25 88 0 36 09 b3 5 b 10 b 5 b 0 3 0 36 09 24 b 0 12 b0 3 b1 0 b1 0 IOH IIN b0 3 03 10b5 03 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k tr and tf e 20 ns unless otherwise specified Symbol CLOCKED OPERATION tPHL tPLH Propagation Delay Time VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V 3 15 3 5 250 100 80 250 100 80 100 40 35 25 6 9 335 165 100 250 100 75 90 50 40 135 70 60 135 50 40 15 10 5 500 200 160 500 200 160 200 80 60 500 200 150 175 75 60 270 140 120 ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns ns ns ns ns ns ns ns ns MHz MHz MHz Parameter Conditions Min Typ Max Units tTHL Transition Time High Low to High Transition Time Low to High Minimum Clock Pulse Width tTLH tWL tWH trCL tfCL Clock Rise and Fall Time tS Minimum Set-up Time J K Lines tS Parallel-In Lines tS P S Control fMAX Maximum Clock Frequency AC Electrical Characteristics TA e 25 C CL e 50 pF RL e 200k tr and tf e 20 ns unless otherwise specified (Continued) Symbol Parameter Conditions Min Typ Max Units CLOCKED OPERATION (Continued) CIN tPHL tPLH Input Capacitance Propagation Delay Time Any Input VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V 5 300 150 85 75 30 25 75 500 200 150 250 110 80 pF ns ns ns ns ns ns RESET OPERATION tWH Minimum Reset Pulse Width AC Parameters are guaranteed by DC correlated testing Truth Table CL J L L L L L K X 0 I X I X X X K X X 0 0 I X X tn b 1 (Inputs) R 0 0 0 0 0 0 I Qnb1 0 0 I Qnb1 I Qnb1 X tn (Outputs) Qn 0 I 0 Qnb1 TOGGLE MODE I Qn b 1 0 Switching Time Waveforms TL F 5964 – 3 T C Input Low Reset Input Low 4 Connection Diagram Dual-In-Line Package TL F 5964 – 4 Top View Order Number CD4035B Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4035BMJ or CD4035BCJ NS Package Number J16A 5 CD4035BM CD4035BC 4-Bit Parallel-In Parallel-Out Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD4035BMN or CD4035BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications