CD4046BC

CD4046BM CD4046BC Micropower Phase-Locked Loop November 1995 CD4046BM CD4046BC Micropower Phase-Locked Loop General Description The CD4046B micropower phase-locked loop (PLL) consists of a low power linear voltage-controlled oscillator (VCO) a source follower a zener diode and two phase comparators The two phase comparators have a common signal input and a common comparator input The signal input can be directly coupled for a large voltage signal or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal Phase comparator I an exclusive OR gate provides a digital error signal (phase comp I Out) and maintains 90 phase shifts at the VCO center frequency Between signal input and comparator input (both at 50% duty cycle) it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency Phase comparator II is an edge-controlled digital memory network It provides a digital error signal (phase comp II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0 phase shift between signal input and comparator input The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input and the capacitor and resistors connected to pin C1A C1B R1 and R2 The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kX or more The INHIBIT input when high disables the VCO and source follower to minimize standby power consumption The zener diode is provided for power supply regulation if necessary Features Y Y Y Y Y Wide supply voltage range 3 0V to 18V Low dynamic 70 mW (typ ) at power consumption fo e 10 kHz VDD e 5V VCO frequency 1 3 MHz (typ ) at VDD e 10V Low frequency drift 0 06% C at VDD e 10V with temperature High VCO linearity 1% (typ ) Applications Y Y Y Y Y Y Y Y FM demodulator and modulator Frequency synthesis and multiplication Frequency discrimination Data synchronization and conditioning Voltage-to-frequency conversion Tone decoding FSK modulation Motor speed control Block Connection Diagrams Dual-In-Line Package TL F 5968 – 2 Top View Order Number CD4046B TL F 5968 – 1 FIGURE 1 C1995 National Semiconductor Corporation TL F 5968 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5 to a 18 VDC b 0 5 to VDD a 0 5 VDC b 65 C to a 150 C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4046BM CD4046BC 3 to 15 VDC 0 to VDD VDC b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 260 C DC Electrical Characteristics CD4046BM (Note 2) Symbol IDD Parameter Conditions b 55 C a 25 C a 125 C Units Min Quiescent Device Current Pin 5 e VDD Pin 14 e VDD Pin 3 9 e VSS VDD e 5V VDD e 10V VDD e 15V Pin 5 e VDD Pin 14 e Open Pin 3 2 e VSS VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V Low Level Input Voltage Comparator and Signal In High Level Input Voltage Comparator and Signal In VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V 35 70 11 0 0 64 16 42 b 0 64 b1 6 b4 2 Max Min Typ Max Min Max 5 10 20 0 005 0 01 0 015 5 10 20 150 300 600 mA mA mA 45 450 1200 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34 b 0 51 b1 3 b3 4 b0 1 5 20 50 0 0 0 4 95 9 95 14 95 5 10 15 2 25 45 6 25 2 75 55 8 25 0 88 2 25 88 b 0 88 b 2 25 b8 8 35 350 900 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 36 b0 9 b2 4 185 650 1500 0 05 0 05 0 05 mA mA mA V V V V V V VOH VIL 15 30 40 V V V V V V mA mA mA mA mA mA VIH IOL Low Level Output Current VDD e 5V VO e 0 4V (Note 4) VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V High Level Output Current VDD e 5V VO e 4 6V (Note 4) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current All Inputs Except Signal Input VDD e 14V VIN e 0V VDD e 15V VIN e 15V Any Input (Note 3) fo e 10 kHz R1 e 1 MX R2 e % VCOIN e VDD 2 VDD e 5V VDD e 10V VDD e 15V IOH IIN b 10 b 5 b 0 1 b1 0 01 10b5 01 10 75 mA mA pF CIN PT Input Capacitance Total Power Dissipation 0 07 06 24 mW mW mW 2 DC Electrical Characteristics CD4046BC (Note 2) Symbol IDD Parameter Conditions b 40 C a 25 C a 85 C Units Min Quiescent Device Current Pin 5 e VDD Pin 14 e VDD Pin 3 9 e VSS VDD e 5V VDD e 10V VDD e 15V Pin 5 e VDD Pin 14 e Open Pin 3 9 e VSS VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V Low Level Input Voltage Comparator and Signal In High Level Input Voltage Comparator and Signal In VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V 35 70 11 0 0 52 13 36 b 0 52 b1 3 b3 6 Max Min Typ Max Min Max 20 40 80 0 005 0 01 0 015 20 40 80 150 300 600 mA mA mA 70 530 1500 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 44 11 30 b 0 44 b1 1 b3 0 b0 3 5 20 50 0 0 0 4 95 9 95 14 95 5 10 15 2 25 45 6 25 2 75 55 8 25 0 88 2 25 88 b 0 88 b 2 25 b8 8 55 410 1200 0 05 0 05 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 36 b0 9 b2 4 205 710 1800 0 05 0 05 0 05 mA mA mA V V V V V V VOH VIL 15 30 40 V V V V V V mA mA mA mA mA mA VIH IOL Low Level Output Current VDD e 5V VO e 0 4V (Note 4) VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V High Level Output Current VDD e 5V VO e 4 6V (Note 4) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current All Inputs Except Signal Input VDD e 15V VIN e 0V VDD e 15V VIN e 15V Any Input (Note 3) fo e 10 kHz R1 e 1 MX R2 e % VCOIN e VDD 2 VDD e 5V VDD e 10V VDD e 15V IOH IIN b 10 b 5 b 0 3 b1 0 03 10b5 03 75 10 mA mA pF CIN PT Input Capacitance Total Power Dissipation 0 07 06 24 mW mW mW Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 Capacitance is guaranteed by periodic testing Note 4 IOH and IOL are tested one output at a time 3 AC Electrical Characteristics Symbol VCO SECTION IDD Operating Current Parameter CD4046BM CD4046BC TA e 25 C CL e 50 pF Conditions Min Typ Max Units fo e 10 kHz R1 e 1 MX R2 e % VCOIN e VDD 2 VDD e 5V VDD e 10V VDD e 15V C1 e 50 pF R1 e 10 kX R2 e % VCOIN e VDD VDD e 5V VDD e 10V VDD e 15V VCOIN e 2 5V g 0 3V R1 t 10 kX VDD e 5V VCOIN e 5V g 2 5V R1 t 400 kX VDD e 10V VCOIN e 7 5V g 5V R1 t 1 MX VDD e 15V % C*1 f VDD R2 e % VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V 20 90 200 mA mA mA fMAX Maximum Operating Frequency 04 06 10 08 12 16 1 1 1 MHz MHz MHz % % % Linearity Temperature-Frequency Stability No Frequency Offset fMIN e 0 0 12 – 0 24 0 04 – 0 08 0 015 – 0 03 0 06 – 0 12 0 05 – 0 1 0 03 – 0 06 106 106 106 50 50 50 90 50 45 200 100 80 %C %C %C %C %C %C MX MX MX % % % ns ns ns Frequency Offset fMIN i 0 VCOIN Input Resistance VCO Output Duty Cycle tTHL tTHL VCO Output Transition Time AC Parameters are guaranteed by DC correlated testing 4 AC Electrical Characteristics Symbol Parameter PHASE COMPARATORS SECTION RIN Input Resistance Signal Input CD4046BM CD4046BC TA e 25 C CL e 50 pF (Continued) Conditions Min Typ Max Units Comparator Input VDD VDD VDD VDD VDD VDD e e e e e e 5V 10V 15V 5V 10V 15V 1 02 01 3 07 03 106 106 106 MX MX MX MX MX MX AC-Coupled Signal Input Voltage Sensitivity CSERIES e 1000 pF f e 50 kHz VDD e 5V VDD e 10V VDD e 15V 200 400 700 400 800 1400 mV mV mV DEMODULATOR OUTPUT VCOINb VDEM Offset Voltage RS t 10 kX VDD e 5V RS t 10 kX VDD e 10V RS t 50 kX VDD e 15V RS t 50 kX VCOIN e 2 5V g 0 3V VDD e 5V VCOIN e 5V g 2 5V VDD e 10V VCOIN e 7 5V g 5V VDD e 15V 1 50 1 50 1 50 01 06 08 22 22 22 V V V % % % Linearity ZENER DIODE VZ RZ Zener Diode Voltage Zener Dynamic Resistance IZ e 50 mA IZ e 1 mA 63 70 100 77 V X AC Parameters are guaranteed by DC correlated testing 5 Phase Comparator State Diagrams TL F 5968 – 3 FIGURE 2 Typical Waveforms TL F 5968–4 FIGURE 3 Typical Waveform Employing Phase Comparator I in Locked Condition TL F 5968 – 5 FIGURE 4 Typical Waveform Employing Phase Comparator II in Locked Condition 6 Typical Performance Characteristics Typical Center Frequency vs C1 for R1 e 10 kX 100 kX and 1 MX TL F 5968 – 6 FIGURE 5a Typical Frequency vs C1 for R2 e 10 kX 100 kX and 1 MX TL F 5968 – 13 FIGURE 5b Note To obtain approximate total power dissipation of PLL system for no-signal input Phase Comparator I PD (Total) e PD (fo) a PD (fMIN) a PD (RS) Phase Comparator II PD (Total) e PD (fMIN) 7 Typical Performance Characteristics (Continued) Typical fMAX fMIN vs R2 R1 TL F 5968 – 14 FIGURE 5C Typical VCO Power Dissipation at Center Frequency vs R1 TL F 5968 – 15 FIGURE 6a Note To obtain approximate total power dissipation of PLL system for no-signal input Phase Comparator I PD (Total) e PD (fo) a PD (fMIN) a PD (RS) Phase Comparator II PD (Total) e PD (fMIN) 8 Typical Performance Characteristics (Continued) Typical VCO Power Dissipation at fMIN vs R2 TL F 5968 – 16 FIGURE 6b Typical Source Follower Power Dissipation vs RS TL F 5968 – 17 FIGURE 6c Note To obtain approximate total power dissipation of PLL system for no-signal input Phase Comparator I PD (Total) e PD (fo) a PD (fMIN) a PD (RS) Phase Comparator II PD (Total) e PD (fMIN) 9 Typical Performance Characteristics (Continued) TL F 5968 – 18 TL F 5968 – 19 FIGURE 7 Typical VCO Linearity vs R1 and C1 Note To obtain approximate total power dissipation of PLL system for no-signal input Phase Comparator I PD (Total) e PD (fo) a PD (fMIN) a PD (RS) Phase Comparator II PD (Total) e PD (fMIN) 10 Design Information This information is a guide for approximating the value of external components for the CD4046B in a phase-lockedloop system The selected external components must be within the following ranges R1 R2 t 10 kX RS t 10 kX C1 t 50 pF Using Phase Comparator I Characteristics VCO Frequency VCO Without Offset R2 e % VCO With Offset In addition to the given design information refer to Figure 5 for R1 R2 and C1 component selections Using Phase Comparator II VCO Without Offset R2 e % VCO With Offset TL F 5968–7 TL F 5968 – 8 TL F 5968 – 9 TL F 5968 – 10 For No Signal Input Frequency Lock Range 2 fL Frequency Capture Range 2 fC VCO in PLL system will adjust to center frequency fo VCO in PLL system will adjust to lowest operating frequency fmin 2 fL e full VCO frequency range 2 fL e fmax b fmin 2 fC TL F 5968–11 1 q 0 2 q fL u1 Loop Filter Component Selection fC e fL For 2 fC see Ref TL F 5968–12 Phase Angle Between Single and Comparator Locks on Harmonics of Center Frequency Signal Input Noise Rejection VCO Component Selection 90 at center frequency (fo) approximating 0 and 180 at ends of lock range (2 fL) Yes High Given fo Use fo with Figure 5a to determine R1 and C1 Given fo and fL Calculate fmin from the equation fmin e fo b fL Use fmin with Figure 5b to determine R2 and C1 fmax Calculate fmin from the equation fmax f a fL eo fmin fo b fL fmax Use with Figure 5c fmin to determine ratio R2 R1 to obtain R1 Given fmax Always 0 in lock No Low Given fmin and fmax Use fmin with Figure 5b to determine R2 and C1 fmax Calculate fmin fmax Use with Figure 5c fmin to determine ratio R2 R1 to obtain R1 Calculate fo from the equation fmax fo e 2 Use fo with Figure 5a to determine R1 and C1 References G S Moschytz ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’ BSTJ May 1965 Floyd Gardner ‘‘Phaselock Techniques’’ John Wiley Sons 1966 11 12 Physical Dimensions inches (millimeters) Order Number CD4046BMJ or CD4046BCJ NS Package Number J16A 13 CD4046BM CD4046BC Micropower Phase-Locked Loop Physical Dimensions inches (millimeters) (Continued) Order Number CD4046BMN or CD4046BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications