CD4512BM CD4512BC 8-Channel Buffered Data Selector
February 1988
CD4512BM CD4512BC 8-Channel Buffered Data Selector
General Description
The CD4512BM CD4512BC buffered 8-channel data selector is a complementary MOS (CMOS) circuit constructed with N- and P-channel enhancement mode transistors This data selector is primarily used as a digital signal multiplexer selecting 1 of 8 inputs and routing the signal to a TRISTATE output A high level at the Inhibit input forces a low level at the output A high level at the Output Enable (OE) input forces the output into the TRI-STATE condition Low levels at both the Inhibit and (OE) inputs allow normal operation
Features
Y Y Y Y
Wide supply voltage range High noise immunity TRI-STATE output Low quiescent power dissipation
3 0V to 15V 0 45 VDD (typ )
Y
0 25 mW package (typ ) VCC e 5 0V Plug-in replacement for Motorola MC14512
Connection Diagram and Truth Table
Dual-In-Line Package
Order Number CD4512B
TL F 5993 – 1
Top View Address Inputs C 0 0 0 0 1 1 1 1
j j
j e Don’t care
Control Inputs A 0 1 0 1 0 1 0 1
j j
Output OE 0 0 0 0 0 0 0 0 0 1 Z X0 X1 X2 X3 X4 X5 X6 X7 0 Hi-Z
B 0 0 1 1 0 0 1 1
j j
Inhibit 0 0 0 0 0 0 0 0 1
j
Hi-Z e TRI-STATE condition Xn e Data at input n
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 5993 RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Notes 1
2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)
b 0 5 to a 18 VDC b 0 5 to VDD a 0 5 VDC b 65 C to a 150 C
Recommended Operating Conditions (Note 2)
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4512BM CD4512BC 3 0 to 15 VDC 0 to VDD VDC
b 55 C to a 125 C b 40 C to a 85 C
700 mW 500 mW 260 C
DC Electrical Characteristics CD4512BM (Note 2)
Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current TRI-STATE Output Current Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V
b 55 C a 25 C a 125 C
Units mA mA mA V V V V V V
Min
Max 50 10 20 0 05 0 05 0 05
Min
Typ 0 005 0 010 0 015 0 0 0
Max 50 10 20 0 05 0 05 0 05
Min
Max 150 300 600 0 05 0 05 0 05
VOL
VOH
VIL
VDD e 5V VO e 0 5V VDD e 10V VO e 1 0V VDD e 15V VO e 1 5V VDD e 5V VO e 4 5V VDD e 10V VO e 9 0V VDD e 15V VO e 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V VDD e 15V VO e 0V VDD e 15V VO e 15V 35 70 11 0 0 64 16 42
b 0 25 b 0 62 b1 8
( (l
lIOLl k 1 mA
IOHl k 1 mA 4 95 9 95 14 95
4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34
b0 2 b0 5 b1 5 b0 1
50 10 0 15 0 2 25 4 50 6 75 2 75 5 50 8 25 0 78 20 78 15 30 40
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 14 b 0 35 b1 1
V V V V V V mA mA mA mA mA mA
VIH
IOL
IOH
IIN IOZ
b 10 b 5
b0 1
b1 0
01
g0 1
10b5
b 10 b 5
01
g0 1
10
g3 0
mA mA mA
DC Electrical Characteristics CD4512BC (Note 2)
Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V
b 40 C a 25 C a 85 C
Units mA mA mA V V V V V V
Min
Max 20 40 80 0 05 0 05 0 05
Min
Typ 0 005 0 010 0 015 0 0 0
Max 20 40 80 0 05 0 05 0 05
Min
Max 150 300 600 0 05 0 05 0 05
VOL
VOH
VIL
VDD e 5V VO e 0 5V VDD e 10V VO e 1 0V VDD e 15V VO e 1 5V
( (l
lIOLl k 1 mA
IOHl k 1 mA 4 95 9 95 14 95
4 95 9 95 14 95 15 30 40
50 10 0 15 0 2 25 4 50 6 75 15 30 40
4 95 9 95 14 95 15 30 40
V V V
2
DC Electrical Characteristics CD4512BC (Note 2) (Continued)
Symbol VIH Parameter High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current TRI-STATE Output Current Conditions VDD e 5V VO e 4 5V VDD e 10V VO e 9 0V VDD e 15V VO e 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5 VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V VDD e 15V VO e 0V VDD e 15V VO e 15V
b 40 C a 25 C a 85 C
Units V V V mA mA mA mA mA mA
Min 35 70 11 0 0 52 13 36
b0 2 b0 5 b1 4
Max
Min 35 70 11 0 0 44 11 34
b 0 16 b0 4 b1 2
Typ 2 75 5 50 8 25 0 78 20 78
Max
Min 35 70 11 0 0 36 09 24
b 0 12 b0 3 b1 0
Max
IOL
IOH
IIN IOZ
b0 3
b 10 b 5
b0 3
b1 0
03
g1 0
10b5
g 10 b 5
03
g1 0
10
g7 5
mA mA mA
AC Electrical Characteristics
Symbol tPHL Parameter Propagation Delay High-to-Low Level Propagation Delay Low-to-High Level Transition Time
TA e 25 C tr e tf e 20 ns CL e 50 pF Conditions Min VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V (Note 4) (Note 4) (Note 5) CD4512BM Typ 225 75 57 225 75 57 70 35 25 50 25 19 50 25 19 75 75 150 Max 500 175 130 500 175 130 200 100 80 125 75 60 125 75 60 15 15 Min CD4512BC Typ 225 75 57 225 75 57 70 35 25 50 25 19 50 25 19 75 75 150 Max 750 200 150 750 200 150 200 100 80 125 75 60 125 75 60 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF Units
tPLH
tTHL tTLH
tPHZ tPLZ
Propagation Delay into TRI-STATE from Logic Level Propagation Delay to Logic Level from TRI-STATE Input Capacitance TRI-STATE Output Capacitance Power Dissipation Capacity
tPZH tPZL
CIN COUT CPD
AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time Note 4 Capacitance guaranteed by periodic testing Note 5 CPD determines the no load AC power of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90
3
Logic Diagram
TL F 5993 – 2
Typical Application
Serial Data Routing Interface
TL F 5993 – 3
4
AC Test Circuit and Switching Time Waveforms
TL F 5993 – 5
TL F 5993 – 4
Input Connections for tr tf tPLH tPHL
Test 1 2 3 Inhibit PG GND GND A GND PG GND X0 VDD VDD PG
TRI-STATE AC Test Circuit and Switching Time Waveforms
TL F 5993 – 7
TL F 5993 – 6
Switch Positions for TRI-STATE Test
Test S1 S2 S3 S4
tPHZ Open Closed Closed Open tPLZ Closed Open Open Closed tPZL Closed Open Open Closed tPZH Open Closed Closed Open
5
CD4512BM CD4512BC 8-Channel Buffered Data Selector
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J) Order Number CD4512BMJ or CD4512BCJ NS Package Number J16A
Molded Dual-In-Line Package (N) Order Number CD4512BMN or CD4512BCN NS Package Number N16E
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