CD4538

CD4538BM CD4538BC Dual Precision Monostable February 1988 CD4538BM CD4538BC Dual Precision Monostable General Description The CD4538B is a dual precision monostable multivibrator with independent trigger and reset controls The device is retriggerable and resettable and the control inputs are internally latched Two trigger inputs are provided to allow either rising or falling edge triggering The reset inputs are active low and prevent triggering while active Precise control of output pulse-width has been achieved using linear CMOS techniques The pulse duration and accuracy are determined by external components RX and CX The device does not allow the timing capacitor to discharge through the timing pin on power-down condition For this reason no external protection resistor is required in series with the timing pin Input protection from static discharge is provided on all pins Features Y Y Y Y Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VCC (typ ) Low power Fan out of 2 driving 74L TTL compatibility or 1 driving 74LS New formula PWOUT e RC (PW in seconds R in Ohms C in Farads) g 1 0% pulse-width variation from part to part (typ ) Wide pulse-width range 1 ms to % Separate latched reset inputs Symmetrical output sink and source capability Low standby current 5 nA (typ ) 5 VDC Pin compatible to CD4528B Block and Connection Diagrams Dual-In-Line Package CD4538BM CD4538BC TL F 6000 – 2 Top View Order Number CD4538B TL F 6000 – 1 RX and CX are External Components VDD e Pin 16 VSS e Pin 8 Truth Table Inputs Clear L X X H H A X H X L B X X L Outputs Q L L L Q H H H H L u v X e e e e e e e High Level Low Level Transition from Low to High Transition from High to Low One High Level Pulse One Low Level Pulse Irrelevant v H u C1995 National Semiconductor Corporation TL F 6000 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 18 VDC DC Supply Voltage (VDD) b 0 5V to VDD a 0 5 VDC Input Voltage (VIN) b 65 C to a 150 C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4538BM CD4538BC 3 to 15 VDC 0 to VDD VDC b 55 C to a 125 C b 40 C to a 85 C DC Electrical Characteristics CD4538BM (Note 2) Symbol IDD Parameter Quiescent VDD e 5V Device Current VDD e 10V VDD e 15V Low Level VDD e 5V Output Voltage VDD e 10V VDD e 15V High Level VDD e 5V Output Voltage VDD e 10V VDD e 15V Low Level Input Voltage Conditions b 55 C a 25 C a 125 C Units mA mA mA V V V V V V Min Max 5 10 20 0 05 0 05 0 05 Min Typ 0 005 0 010 0 015 0 0 0 Max 5 10 20 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL VOH VIL l IO l k 1 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V l IO l k 1 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V 35 70 11 0 0 64 16 42 b 0 64 b1 6 b4 2 ( ll ( ll ( VIH e VDD VIL e VSS All Outputs Open IO k 1 m A VIH e VDD VIL e VSS IO k 1 m A VIH e VDD VIL e VSS 4 95 9 95 14 95 4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34 b 0 51 b1 3 b3 4 g 0 02 5 10 15 2 25 4 50 6 75 2 75 5 50 8 25 0 88 2 25 88 b 0 88 b 2 25 b8 8 g 10 b 5 g 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 36 b0 9 b2 4 g0 5 15 30 40 V V V V V V mA mA mA mA mA mA mA mA VIH High Level Input Voltage IOL Low Level VDD e 5V VO e 0 4V Output Current VDD e 10V VO e 0 5V (Note 3) VD e 15V VO e 1 5V High Level VDD e 5V VO e 4 6V Output Current VDD e 10V VO e 9 5V (Note 3) VD e 15V VO e 13 5V Input Current Pin 2 or 14 Input Current Other Inputs IOH IIN IIN VDD e 15V VIN e 0V or 15V VDD e 15V VIN e 0V or 15V ( ( VIH e VDD VIL e VSS VIH e VDD VIL e VSS g0 1 g 10 b 5 g0 1 g1 0 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for acutal device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 2 DC Electrical Characteristics CD4538BC (Note 2) Symbol IDD Parameter Quiescent VDD e 5V Device Current VDD e 10V VDD e 15V Low Level VDD e 5V Output Voltage VDD e 10V VDD e 15V High Level VDD e 5V Output Voltage VDD e 10V VDD e 15V Low Level Input Voltage Conditions b 40 C a 25 C a 85 C Units mA mA mA V V V V V V Min Max 20 40 80 0 05 0 05 0 05 Min Typ 0 005 0 010 0 015 0 0 0 Max 20 40 80 0 05 0 05 0 05 Min Max 150 300 600 0 05 0 05 0 05 VOL VOH VIL l IO l k 1 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V l IO l k 1 m A VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V 35 70 11 0 0 52 13 36 b 0 52 b1 3 b3 6 ( ll ( ll ( VIH e VDD VIL e VSS All Outputs Open IO k 1 m A VIH e VDD VIL e VSS IO k 1 m A VIH e VDD VIL e VSS 4 95 9 95 14 95 4 95 9 95 14 95 15 30 40 35 70 11 0 0 44 11 30 b 0 44 b1 1 b3 0 g 0 02 5 10 15 2 25 4 50 6 75 2 75 5 50 8 25 0 88 2 25 88 b 0 88 b 2 25 b8 8 g 10 b 5 g 0 05 4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24 b 0 36 b0 9 b2 4 g0 5 15 30 40 V V V V V V mA mA mA mA mA mA mA mA VIH High Level Input Voltage IOL Low Level VDD e 5V VO e 0 4V Output Current VDD e 10V VO e 0 5V (Note 3) VD e 15V VO e 1 5V High Level Output Current (Note 3) Input Current Pin 2 or 14 Input Current Other Inputs VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VD e 15V VO e 13 5V IOH IIN IIN VDD e 15V VIN e 0V or 15V VDD e 15V VIN e 0V or 15V ( ( VIH e VDD VIL e VSS VIL e VSS g0 3 g 10 b 5 g0 3 g1 0 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for acutal device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time 3 AC Electrical Characteristics Symbol tTLH tTHL Parameter Output Transition Time TA e 25 C CL e 50 pF and tr e tf e 20 ns unless otherwise specified Conditions VDD e 5V VDD e 10V VDD e 15V Trigger Operation A or B to Q or Q VDD e 5V VDD e 10V VDD e 15V Reset Operation CD to Q or Q VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Pin 2 or 14 Other Inputs RX e 100 kX CX e 0 002 mF RX e 100 kX CX e 0 1 m F RX e 100 kX CX e 10 0 mF VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V 50 0 208 211 216 8 83 9 02 9 20 0 87 0 89 0 91 Min Typ 100 50 40 Max 200 100 80 Units ns ns ns tPLH tPHL Propagation Delay Time 300 150 100 250 125 95 35 30 25 0 10 5 226 230 235 9 60 9 80 10 00 0 95 0 97 0 99 g1 g1 g1 600 300 220 500 250 190 70 60 50 0 0 0 75 244 248 254 10 37 10 59 10 80 1 03 1 05 1 07 ns ns ns ns ns ns ns ns ns ns ns ns pF pF ms ms ms ms ms ms s s s % % % kX pF tWL tWH Minimum Input Pulse Width A B or CD Minimum Retrigger Time tRR CIN PWOUT Input Capacitance Output Pulse Width (Q or Q) (Note For Typical Distribution see Figure 9 ) Pulse Width Match between Circuits in the Same Package CX e 0 1 mF RX e 100 kX Operating Conditions RX CX External Timing Resistance External Timing Capacitance RX e 100 kX CX e 0 1 mF No Limit AC parameters are guaranteed by DC correlated testing The maximum usable resistance RX is a function of the leakage of the Capacitor CX leakage of the CD4538B and leakage due to board layout surface resistance etc Logic Diagram TL F 6000 – 3 FIGURE 1 4 Theory of Operation TL F 6000 – 4 FIGURE 2 Trigger Operation The block diagram of the CD4538B is shown in Figure 1 with circuit operation following As shown in Figures 1 and 2 before an input trigger occurs the monostable is in the quiescent state with the Q output low and the timing capacitor CX completely charged to VDD When the trigger input A goes from VSS to VDD (while inputs B and CD are held to VDD) a valid trigger is recognized which turns on comparator C1 and N-Channel transistor N1 j At the same time the output latch is set With transistor N1 on the capacitor CX rapidly discharges toward VSS until VREF1 is reached At this point the output of comparator C1 changes state and transistor N1 turns off Comparator C1 then turns off while at the same time comparator C2 turns on With transistor N1 off the capacitor CX begins to charge through the timing resistor RX toward VDD When the voltage across CX equals VREF2 comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 This ends the timing cycle with the monostable in the quiescent state waiting for the next trigger A valid trigger is also recognized when trigger input B goes from VDD to VSS (while input A is at VSS and input CD is at VDD) k It should be noted that in the quiescent state CX is fully charged to VDD causing the current through resistor RX to be zero Both comparators are ‘‘off’’ with the total device current due only to reverse junction leakages An added feature of the CD4538B is that the output latch is set via the input trigger without regard to the capacitor voltage Thus propagation delay from trigger to Q is independent of the value of CX RX or the duty cycle of the input waveform Retrigger Operation The CD4538B is retriggered if a valid trigger occurs l followed by another valid trigger m before the Q output has returned to the quiescent (zero) state Any retrigger after the timing node voltage at pin 2 or 14 has begun to rise from VREF1 but has not yet reached VREF2 will cause an increase in output pulse width T When a valid retrigger is initiated m the voltage at T2 will again drop to VREF1 before progressing along the RC charging curve toward VDD The Q output will remain high until time T after the last valid retrigger Reset Operation The CD4538B may be reset during the generation of the output pulse In the reset mode of operation an input pulse on CD sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor Q1 n When the voltage on the capacitor reaches VREF2 the reset latch will clear and then be ready to accept another pulse If the CD input is held low any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the CD input the output pulse T can be made significantly shorter than the minimum pulse width specification 5 Typical Applications TL F 6000–5 TL F 6000 – 6 TL F 6000–7 TL F 6000 – 8 FIGURE 3 Retriggerable Monostables Circuitry FIGURE 4 Non-Retriggerable Monostables Circuitry TL F 6000 – 9 FIGURE 5 Connection of Unused Sections 6 Typical Applications (Continued) TL F 6000 – 10 FIGURE 6 Switching Test Waveforms RX e RX e 100 kX CX e CX e 100 pF C1 e C2 e 0 1 mF CL e 50 pF TL F 6000 – 11 TL F 6000 – 12 Input Connections Characteristics tPLH tPHL tTLH tTHL PWOUT tWH tWL tPLH tPHL tTLH tTHL PWOUT tWH tWL tPLH(R) tPHL(R) tWH tWL CD VDD VDD PG3 A PG1 VSS PG1 B VDD PG2 Duty Cycle e 50% TL F 6000 – 14 PG2 FIGURE 8 Power Dissipation Test Circuit and Waveforms Includes capacitance of probes wiring and fixture parasitic Note Switching test waveforms for PG1 PG2 PG3 are shown in Figure 6 TL F 6000 – 13 FIGURE 7 Switching Test Circuit 7 Typical Applications (Continued) TL F 6000 – 15 TL F 6000 – 16 FIGURE 9 Typical Normalized Distribution of Units for Output Pulse Width FIGURE 12 Typical Pulse Width Error Versus Temperature TL F 6000 – 17 TL F 6000 – 18 FIGURE 10 Typical Pulse Width Variation as a Function of Supply Voltage VDD FIGURE 13 Typical Pulse Width Error Versus Temperature TL F 6000 – 19 TL F 6000 – 20 FIGURE 11 Typical Total Supply Current Versus Output Duty Cycle RX e 100 kX CL e 50 pF CX e 100 pF One Monostable Switching Only FIGURE 14 Typical Pulse Width Versus Timing RC Product 8 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4538BMJ or CD4538BCJ NS Package Number J16A 9 CD4538BM CD4538BC Dual Precision Monostable Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number CD4538BMN or CD4538BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications