CGS702V

CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI September 1995 CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI General Description The CGS702 is an off-the-shelf clock driver specifically designed for today’s high speed processors It provides low skew outputs which are produced at different frequencies from three fixed input references The CGS702 is a reduced EMI version of the CGS700 The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz 33 MHz or 40 MHz The PLL using a charge pump and an internal loop filter multiplies this input frequency to create a maximum output frequency of four times the input The device includes a TRI-STATE control pin to disable the outputs while the PLL is still in lock This function allows testing the board without having to wait to acquire the lock once the testing is complete (Continued) Y Y Y Y Y Y Y Y Y Y Y Y Y Features Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL and TOSLH) on 1x outputs PentiumTM and PowerPCTM compatible Output buffer of nine drivers for large fanout 25 MHz – 160 MHz output frequency range Outputs operating at 4x 2x 1x of the reference frequency for multi-frequency bus applications Selectable output frequency Internal loop filter to reduce noise and jitter Separate Analog and digital VCC and Ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output current drive a 30 mA b 30 mA IOL IOH 28-pin PCC for optimum skew performance Guaranteed 2 kV ESD protection Reduced EMI compared to CGS700 (refer to EMI characteristics) Pin Description Connection Diagram PLCC Package Pin 1 2 3 Name VCC SKWSEL CLK4 VCC XTALIN GND CLK1 VCC CLK1 GND CLK1 2 1 0 Description Digital VCC Skew Test Selector Pin 4x Clock Output Digital VCC Crystal Oscillator Input Digital Ground 1x Clock Output Digital VCC 1x Clock Output Digital Ground 1x Clock Output Output TRI-STATE Control Skew Testing Pin 1x Clock Output Digital Ground 4 1x Clock Output Digital VCC External Test Clock Analog Ground Analog VCC External Clock MUX Selector Digital Ground 5 1x Clock Output Digital VCC 6 1x Clock Output CLK1 Multiplier Selector Digital Ground 2x Clock Output RRD-B30M105 Printed in U S A Pin Assignment for PLCC 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TL F 12386 – 1 TRI-STATE SKWTST CLK1 GND CLK1 VCC EXTCLK GNDA VCCA EXTSEL GND CLK1 VCC CLK1 CLK1SEL GND CLK2 3 20 21 22 23 24 25 26 TRI-STATE is a registered trademark of National Semiconductor Corporation PentiumTM is a trademark of Intel Corporation PowerPCTM is a trademark of International Business Machines Corporation 27 28 C1995 National Semiconductor Corporation TL F 12386 General Description (Continued) Also included are two EXTSEL and EXTCLK pins to allow testing the chip via an external source The EXTSEL pin once set to high causes the External-Clock Mux to change its input from the output of the VCO and Counter to the external clock signal provided via EXTCLK input pin CLK1SEL pin changes the output frequency of the CLK1 0 6 outputs During normal operation when CLK1SEL pin is high these outputs are at the same frequency as the input crystal oscillator while CLK2 and CLK4 outputs are at twice and four times the input frequency respectively Once CLK1SEL pin is set to a low logic level the CLK1 outputs will be at twice the input frequency the same as the CLK2 output with CLK4 output still being at four times the input frequency In addition two other pins are added for increasing the test capability SKWSEL and SKWTST pins allow testing of the counter’s output and skew of the output drivers by bypassing the VCO In this test mode CLK4 frequency is the same as SKWTST input frequency while CLK2 is and CLK1 frequencies are respectively (refer to the truth table) In addition CLK1SEL functionality is also true under this test condition Block Diagram TL F 12386 – 2 2 Truth Table Input CLK1 SEL H L X H L X EXT SEL L L H L L X EXT CLK X X X X X SKW SEL L L X H H X SKW TST X X X TRISTATE H H H H H L CLK4 4x fIN 4x fIN 1x fTST 1x fTST Z Output CLK2 2x fIN 2x fIN x fTST x fTST Z CLK1 fIN 2x fIN x fTST x fTST Z X Steady state phase frequency lock Typical Application TL F 12386 – 3 3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to 7 0V Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) b 20 mA V e b0 5V a 20 mA V e VCC a 0 5V b 0 5V to VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IO) b 20 mA V e b0 5V a 20 mA V e VCC a 0 5V b 0 5V to VCC a 0 5V DC Output Voltage (VO) DC Output Source g 60 mA or Sink Current (IO) DC VCC or Ground Current g 60 mA per Output Pin (ICO or IGND) b 65 C to a 150 C Storage Temperature (TSTG) Junction Temperature 150 C Power Dissipation (Static and Dynamic) (Note 2) 1400 mW Note 1 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings The Recommended Operating Conditions will define the conditions for actual device operation Note 2 Power dissipation is calculated using 49 W as the thermal coefficient for the PCC package at 225 LFM airflow The input frequency is assumed at 33 MHz with CLK4 at 132 MHz and CLK2 and CLK1’s being at 66 MHz In addition the ambient temperature is assumed 70 with power supply at 5 0V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Input Crystal Frequency Operating Temperature (TA) External Clock Frequency (EXTCLK Pin) XTALIN Duty Cycle Range Input Rise and Fall Times (0 8V to 2 0V) Crystal Input All Other Inputs Typical iJA LFM CW 0 54 225 45 500 38 900 34 4 5V to 5 5V 0V to VCC 0V to VCC 25 MHz – 40 MHz 0 C to a 70 C 1 MHz – 10 MHz 25 75 (75 25)% 5 ns max 10 ns max DC Electrical Characteristics over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C VCC e 4 5V to 5 5V T e 0 C to 70 C Min VIH VIL VOH Minimum Input High Level Voltage Maximum Input Low LeveI Voltage Minimum Output High Level Voltage IOH e b50 mA IOH e b30 mA VOL Maximum Output Low Level Voltage IOL e 50 mA IOL e 30 mA IOH IOL IIN IOZL H CIN ICC ICCT High Level Output Current Low Level Output Current Leakage Current Output Leakage Current Input Capacitance Quiescent Analog a Digital Current (No Load) ICC per TTL Input VIN e VCC or GND VIN e VCC b 2 1 or GND VOH e VCC b 1 0V VOL e 1 0V VIN e 0 4V or 4 6V VIN e GND VOUT e VCC or GND 45 55 45 55 45 55 45 55 45 55 45 55 45 45 45 55 55 45 50 55 55 3 50 50 b 50 b5 0 Symbol Parameter Conditions VCC Units Typ Max V 08 08 V 20 20 44 54 VCC b 0 6 VCC b 0 6 44 54 V 01 01 06 06 110 110 170 170 50 0 a5 0 V mA mA mA mA pF mA 10 0 50 25 4 CGS702 AC Electrical Characteristics over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C VCC e 4 5V to 5 5V fIN e 25 MHz to 40 MHz T e 0 C to 70 C CL e Circuit 1 and 2 RL e Circuit 1 and 2 Min tRISE Output Rise CLK4 CLK2 CLK1 CLK4 CLK2 CLK1 0 8V to 2 6V 1 0V to VCC b 1 0V 1 0V to VCC b 1 0V 2 6V to 0 8V VCC b 1 0V to 1 0V VCC b 1 0V to 1 0V CLK1 CLK1 CLK2 CLK1 CLK4 CLK4 Typ Max 20 ns (Note 1) Symbol Parameter Units Notes tFALL Output Fall 20 500 1000 1500 100 49 49 35 51 51 65 300 b 75 g 250 g 250 ns (Note 1) tSKEW Maximum Edge-to-Edge Output Skew a to a Edges a to a Edges a to a Edges ps ms % ps ps ps ps (Note 2) tLOCK tCYCLE Time to Lock the Output to the XTALIN Input Output Duty Cycle CLK1 Outputs CLK2 Output CLK4 Output (Note 3) (Notes 4 5) (Notes 4 5 6) (Notes 4 5 7) (Notes 4 5 7) JLT JCC Output Jitter (Long Term) Output Jitter (Cycle to Cycle) CLK1 CLK2 CLK4 a 75 FMIN FMAX Minimum XTALIN Frequency Maximum XTALIN Frequency 15 43 MHz MHz Note 1 tRISE and tFALL parameters are measured at the pin of the device Note 2 Skew is measured at 50% of VCC for CLK1 and CLK2 While it is measured at 1 4V for CLK4 Note 3 Output duty cycle is measured at VDD 2 for CLK1 and CLK2 While it is measured at 1 4V for CLK4 Note 4 Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles It is also measured at output levels of VCC 2 Refer to Figure 2 for further explanation Note 5 The GNDA pins of the 702 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin Note 6 Cycle to Cycle Jitter is measured at VCC 2 Note 7 Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25 C 5V measured VCC 2 TL F 12386 – 5 TL F 12386 – 4 Circuit 2 Test Circuit for CLK4 Circuit 1 Test Circuit for CLK1 and CLK2 5 CGS702 AC Electrical Characteristics (Continued) TL F 12386 – 6 FIGURE 1 Waveforms TL F 12386 – 7 Jitter e l Period(1) b Period(n a 1) l for either the rising or falling edge where n is 1 to 1000 cycles FIGURE 2 Jitter Application References and Bibiliography Information relating to EMI as well as general application hints are in the following application notes AN-988 (EMI App Note) AN-640 AN-991 6 EMI Characteristics and Measurements for CGS702 MEASURING THE SPECTRAL CONTENT OF A LOGIC IC In order to analyze the frequency or spectral content of logic ICs two measurement techniques have been developed One method The Radiated Measurement Method is based on the system-level FCC certification test methodology FCC Open Site Test (OST) 55 The radiated method utilizes a multilayer PCB with the IC-under-test is mounted on a grounded adjustable table placed 3 meters from an antenna mast (see Figure 3 ) The IC’s input is stimulated by a known periodic waveform and its output drives a typical PCB microstrip The 75X microstrip is properly terminated to prevent reflections from affecting the IC’s spectral content results The FCC certification test method is an open field measurement procedure Therefore the spectral content of the device-under-test (in this case an IC) cannot be detected below the ambient level of radiation The test-site is permanent and the average ambient noise level remains relatively constant The CGS700 and CGS702 were tested for EMI using the above method A comparison of the EMI results in the form of spectral content is shown in Figures 4 and 5 For more details on EMI see Application Note AN-831 Screen Room with 120 dB Shielding TL F 12386 – 9 FIGURE 3 Radiated EMI Measurement Method 7 EMI Characteristics and Measurements (Continued) TL F 12386 – 8 XTALIN e 40 MHz VCC e 5V T e 25 C ANTENNA e HORIZONTAL FIGURE 4 CGS700 TL F 12386 – 12 XTALIN e 40 MHz VCC e 5V T e 25 C ANTENNA e HORIZONTAL FIGURE 5 CGS702 8 Ordering Information (Contact NSC Marketing for Specific Date of Availability) TL F 12386 – 11 9 CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI Physical Dimensions inches (millimeters) 28-Lead Molded Plated Leaded Chip Carrier Order Number CGS702V NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications