CLC001AJE

CLC001 Serial Digital Cable Driver with Adjustable Outputs February 2006 CLC001 Serial Digital Cable Driver with Adjustable Outputs General Description The CLC001 is a monolithic, high-speed cable driver designed for use in SMPTE 259M serial digital video and ITU-T G.703 serial digital data transmission applications. The CLC001 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to 622 Mbps. Controlled output rise and fall times (400 ps typical) minimize transitioninduced jitter. The output voltage swing is adjustable from 800 mVp-p to 1.0 Vp-p using an external resistor. The CLC001’s output stage consumes less power than other designs. The differential inputs accept LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. All these make the CLC001 an excellent general purpose high speed driver for high-speed, long distance data transmission applications. The CLC001 is powered from a single +3.3V supply and comes in a small 8-pin SOIC package. Applications Digital routers and distribution amplifiers Coaxial cable driver for digital transmission lines Twisted pair driver Serial digital video interfaces for the commercial and broadcast industry n SMPTE, Sonet/SDH, and ATM compatible driver n Buffer applications n n n n Key Specifications n n n n 400 ps rise and fall times Data rates to 622 Mbps 100 mV differential input threshold Low residual jitter 10132910 622 Mbps Eye Pattern with STM-4 Signal Mask Features n n n n n Adjustable output amplitude Differential input and output Accepts LVPECL or LVDS input swings Low power dissipation Single +3.3V supply Connection Diagram (8-Pin SOIC) 10132902 Order Number CLC001AJE See NS Package Number M08A © 2006 National Semiconductor Corporation DS101329 www.national.com CLC001 Typical Application 10132901 www.national.com 2 CLC001 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Output Current Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering 10 seconds) ESD Rating (HBM) ESD Rating (MM) Package Thermal Resistance θJA Surface Mount AJE +300˚C ≥ 7 kV ≥ 500V 125˚C/W 4V 27 mA +125˚C −65˚C to +150˚C θJC Surface Mount AJE Reliability Information Transistor count 105˚C/W 291 Recommended Operating Conditions Supply Voltage Range (VDD - VSS) Operating Free Air Temperature (TA) RBB Range (applied to VBB input) (Note 6) +3.0V to +3.6V -40˚C to +85˚C 1.3kΩ to 11.5kΩ Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (Notes 2 and 3) Symbol VSDO Parameter Serial Driver Output Voltage Conditions RL = 75Ω 1%,RREF = 1.91 kΩ 1% (for 800 mVp-p),Figure 1 RL = 75Ω 1%,RREF = 1.5 kΩ 1% (for 1.0 Vp-p),Figure 1 INPUT DC SPECIFICATIONS VTH VTL VCMR IIN IINB Differential Input High Threshold Differential Input Low Threshold Common Mode Voltage Range Input Current Input Current Balance VCM = +0.05V or +1.2V or +3.25V, VDD = 3.3V VID = 100mV, VDD = 3.3V VIN = 0V or +3.0V, VDD = 3.6V or 0V VIN = 0V or +3.0V, VDD = 3.6V or 0V, (Note 8) RL = 75Ω,RREF = 1.91 kΩ 1%(VSDO = 800 mVp-p @ 270 Mbps) RL = 75Ω,RREF = 1.5 kΩ 1%(VSDO = 1.0 Vp-p @ 622 Mbps) MISCELLANEOUS PARAMETERS LGEN RGEN IBB Output Inductance Output Resistance VBB Current RREF = 1.91 kΩ 1%, (Note 6) RREF = 1.5 kΩ 1%, (Note 6) 6 25 250 315 nH kΩ µA µA −100 0.05 0 0 3.25 +100 mV mV V µA µA Min 720 900 Typ 800 1000 Max 880 1100 Units mV mV OUTPUT DC SPECIFICATIONS ±1 0.23 ± 10 SUPPLY CURRENT IDD Total Dynamic Power Supply Current (includes load current) 70 85 115 130 mA mA 3 www.national.com CLC001 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (Note 3) Symbol tr, tf tos tjit tpd Parameter Rise time, Fall time Output overshoot Output jitter Propagation delay (Note 7) (Note 5) Conditions 20%–80%, (Notes 4, 5) Min Typ 400 5 25 1.9 Max 800 Units ps % ps ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS = 0V. Note 3: Typical values are at 25˚C and 3.3V. Note 4: This parameter is Guaranteed by Design. Note 5: RL = 75Ω, AC-coupled at 270 Mbps, RREF = 1.91 kΩ 1% (for VSDO = 800 mVp-p ± 10%), CL not greater than 5pF (See Figure 1) Note 6: The VBB output is intended as a bias supply pin for the inputs of this device only. It is not designed as a power supply output and should not be used to power other devices. Note 7: RL = 75Ω, AC-coupled at 622 Mbps, RREF = 1.5 kΩ 1% (for VSDO = 1.0 Vp-p ± 10%), clock pattern input. Note 8: Input Current Balance (IINB) is the difference between the Input Current (IIN) on VIN+ and VIN− for the same bias condition. Test Loads 10132904 FIGURE 1. Test Loads www.national.com 4 CLC001 Test Loads (Continued) 10132903 FIGURE 2. Test Circuit Pin Descriptions Pin # 1 2 3 4 5 6 7 8 Name VBB VIN+ VINRREF VSS SDO SDO VDD Description Optional, bias voltage (may be used to bias inputs) - see device operation section for details. If unused leave as no connect (NC). Positive input pin Negative input pin Output driver level control. Connect a resistor to ground to set output voltage swing. Negative power supply Serial data true output Serial data complement output Positive power supply 5 www.national.com CLC001 Device Operation INPUT INTERFACING Numerous input configurations exist for applying PECL, LVPECL, and LVDS signals to the input of the CLC001. Inputs may be single-ended or differential, AC or DC coupled. The VBB pin may be used to provide a DC bias voltage to the inputs. Leave this pin as a no connect when no bias is needed. Note that DC-coupled inputs such as direct LVDS and LVPECL connections are self-biasing and do not require use of the VBB pin. IBB, the current produced by the VBB pin, depends on RREF. For a given RREF, the IBB current will remain constant, and the bias voltage is determined by the value of resistance, RBB, between the VBB pin and ground. Figure 3 and Figure 4 show how RBB corresponds to some common VBB values with RREF held at 1.91 kΩ and 1.5 kΩ, respectively. Some common input configurations are shown in Figure 5 through Figure 9. 10132912 FIGURE 4. RBB vs. VBB for RREF = 1.5 kΩ 10132911 FIGURE 3. RBB vs. VBB for RREF = 1.91 kΩ www.national.com 6 CLC001 Device Operation (Continued) 825Ω gives the equivalent termination resistance of 75Ω. RBB set at 5kΩ provides 1.25V of DC bias to the input. Figure 5 shows the CLC001 with an AC-coupled, single ended input connection. The 82.5Ω resister in parallel with 10132905 FIGURE 5. Single Ended 75Ω Coaxial Cable, AC-coupled A typical DC-coupled, twisted pair cable connection is shown in Figure 6. The CLC001 is driven differentially. The line is terminated with a termination resistor equal to the impedance of the line being driven. The actual resistor value is media specific, but typically is between 100 and 120Ω depending upon the cable. This resistor should be located close to the CLC001 inputs pins to minimize the resulting stub length between the resistor and device pads. 10132906 FIGURE 6. Twisted Pair Cable, DC-coupled 7 www.national.com CLC001 Device Operation (Continued) Figure 7 shows an AC-coupled, twisted pair cable application. It implements a center tap capacitance termination used in conjunction with two 50Ω resistors to filter common mode noise. RBB set at 5kΩ provides 1.25V of DC bias to each input. 10132907 FIGURE 7. Twisted Pair Cable, AC-coupled PECL or LVPECL drivers may be interfaced to the CLC001 as shown in Figure 8. The voltage divider network will reduce the PECL output to the proper levels. For LVPECL, the 100Ω series resistors should be removed, since the common mode range inputs of the CLC001 are wide enough to accept LVPECL levels directly. No external DC biasing is required for PECL/LVPECL connections. 10132908 FIGURE 8. PECL, DC-coupled www.national.com 8 CLC001 Device Operation (Continued) A typical LVDS input connection is shown in Figure 9. The media is driven differentially by an LVDS driver. The line is terminated with a termination resistor equal to the impedance of the line being driven. The actual resistor value is media specific, but typically is between 100 and 120Ω. This resistor should be located close to the CLC001 inputs pins to minimize the resulting stub length between the resistor and device pads. The CLC001 supports ± 100mV thresholds across the entire LVDS common mode range of 0.1V to 2.3V for a 200mV differential signal. 10132909 FIGURE 9. LVDS, DC-coupled 9 www.national.com CLC001 Device Operation OUTPUT INTERFACING (Continued) vices. The evaluation boards can be ordered through National’s Distributors. Supplies are limited, please check for current availability. The SD001EVK evaluation kit for the CLC001, Serial Digital Cable Driver with Adjustable Outputs, provides an operating environment in which the cable driver can be evaluated by system / hardware designers. The evaluation board has all the needed circuitry and connectors for easy connection and checkout of the device circuit options as discussed in the CLC001 datasheet. A schematic, parts list and pictorial drawing are provided with the board. From the WWW, the following information may be viewed / downloaded for most evaluation boards: www.national.com/ appinfo/interface • Device Datasheet and / or EVK User Manual • View a picture of the EVK • View the EVK Schematic • View the top assembly drawing and BOM • View the bottom assembly drawing and BOM PCB Layout Recommendations Printed circuit board layout affects the performance of the CLC001. The following guidelines will aid in achieving satisfactory device performance. • Use a ground plane or power/ground plane sandwich design for optimum performance. • Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum electrolytic capacitor located no more than 0.1" (2.5 mm) from the device power pins. • Provide short, symmetrical ground return paths for: — inputs, — supply bypass capacitors and — the output load. • Provide short, grounded guard traces located — under the centerline of the package, — 0.1" (2.5 mm) from the package pins — on both top and bottom of the board with connecting vias. The CLC001 has two complementary, ground referenced outputs designed to drive AC-coupled and terminated 75Ω coaxial cables. The outputs are single ended; however, they could be treated as a single differential output as long as current paths from each output go to ground. The output of the CLC001 is a high impedance current source. It expects to see a 75Ω shunt resistor before driving cable to convert the current output to a voltage and provide proper back-matching. No series back-matching resistors should be used. Refer to Section Typical Application for an illustration. Output levels range from 800 mVp-p to 1.0 Vp-p ± 10% into 75Ω AC-coupled, back-matched loads. Output level is controlled by the value of RREF connected to pin 4. RREF is 1.91 kΩ ± 1% for 800 mVp-p, and 1.5 kΩ ± 1% for 1.0 Vp-p. Refer to Figure 10 for the output level’s sensitivity to RREF. 10132913 FIGURE 10. Output level’s sensitivity to RREF Evaluation Board Evaluation boards are available for a nominal charge that demonstrate the basic operation of the SDI/SDV/SDH de- www.national.com 10 CLC001 Serial Digital Cable Driver with Adjustable Outputs Physical Dimensions inches (millimeters) unless otherwise noted Order Number CLC001AJE NS Package Number M08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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