CLC012AJE

CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery August 1998 CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery General Description National’s CLC012 adaptive cable equalizer is a low-cost monolithic solution for equalizing data transmitted over cable (or any media with similar dispersive loss characteristics). The CLC012 simplifies the task of high-speed data recovery with a one-chip solution and a minimal number of external components. The equalizer automatically adapts to equalize any cable length from zero meters to lengths that attenuate the signal by 40 dB at 200 MHz. This corresponds to 300 meters of Belden 8281 or 120 meters of Category 5 UTP (unshielded twisted pair). The CLC012 provides superior jitter performance: 180pspp for 270 Mbps data that has passed through 200 meters of Belden 8281 cable. This exceptional performance provides wide error margin in digital data links. The equalizer operates on a single supply with a power consumption of only 290 mW. The small 14-pin SOIC package allows for high-density placement of components for multi-channel applications such as routers. The equalizer operates over a wide range of data rates from less than 50 Mbps to rates in excess of 650 Mbps. The equalizer is flexible in allowing either single-ended or differential input drive. Its high common mode rejection provides excellent immunity to interference from noise sources. On-chip quantized feedback eliminates baseline wander. Additional features include a Loss of Signal output and an output mute pin which, when tied together, mute the output when no signal is present. A buffered eye monitor output is provided, for viewing the equalized signal prior to the comparator. Differential AEC pins allow the user to set the internal adaptive loop time constant with one external capacitor. Features n n n n n n Automatic equalization of coaxial and twisted pair cables Loss of Signal detect and output mute Output eye monitor Single supply operation: +5V or −5.2V Single-ended or differential input Low cost Applications n n n n ITU-T G.703 serial data recovery Serial digital data routing and distribution Serial digital data equalization and reception Data recovery equalization: ATM, CAD networks, medical, set top terminals, industrial video networks Key Specifications n Low jitter: 180pspp @ 270 Mbps through 200 meters of Belden 8281 coaxial cable n High data rates: < 50 Mbps to > 650 Mbps n Excellent input return loss: 19 dB @ 270 MHz n Low supply current: 68 mA n Equalizes up to 300+ meters of Belden 8281 or 120 meters of Cat 5 UTP cable Typical Application DS100145-4 © 1998 National Semiconductor Corporation DS100145 www.national.com Typical Application (Continued) DS100145-2 DS100145-3 Connection Diagram Pinout SOIC DS100145-1 14-Pin SOIC Order Number CLC012AJE See NS Package Number M14A www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC–VEE) Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering 4 sec.) ESD Rating (Note 14) θJA 14-Pin SOIC (AJE) MTTF (based on limited life test data) −0.3V, +6.5V +150˚C −65˚C to +150˚C +260˚C ≥500V 95˚C/W 4.8 x 107 hours Recommended Operating Conditions Supply Voltage (VCC–VEE) Operating Temperature Range Series Input Resistance (In Series w/DI & DI) Input Coupling Capacitance AEC Capacitor (Connected between AEC+ & AEC−) Cable Input Voltage Swing (Note 4) DO/DO Minimum Voltage (Note 15) 4.5V to 5.5V −40˚C to +85˚C 100Ω 0.1 µF 50 pF to 1 µF 720 to 880 mVpp VCC–1.6V Electrical Characteristics (VCC = +5V, VEE = 0V, signal source swing = 0.8 Vpp(Note 4), CAEC = 100 pF) Parameter DYNAMIC PERFORMANCE Residual Jitter 10 meters Belden 8281 300 meters Belden 8281 Equalization Time Constant 100 meters Belden 8281 200 meters Belden 8281 300 meters Belden 8281 output rise and fall time (20%–80%) output duty cycle distortion minimum average transition density maximum average data rate VCC Jitter Sensitivity 27 MHz 270 MHz VEE Jitter Sensitivity 27 MHz 270 MHz STATIC PERFORMANCE Supply Current (Includes Output Current) VAEC = 0V VAEC = 0.4V Input and Output Parameters DO/DO output current DO/DO output voltage swing DI/DI common mode voltage AEC differential voltage AEC+/AEC− common mode output eye monitor (OEM) bias potential Loss of Signal (LOS) current output-HIGH Loss of Signal (LOS) current output-LOW MUTE voltage input-HIGH MUTE voltage input-LOW LOS VOH = 4.5V LOS VOL = 0.5V (Note 3) (Note 3) Belden 8281 Rcollector = 75Ω (Note 3) 10 750 3.4 1.5 3.6 3.2 −400 600 1.8 1.2 8.7/11.3 650/850 _ _ _ _ _ _ 2.0 0.8 8.0/12 600/900 _ _ _ _ _ _ 2.0 0.8 mA mV V mV/meter V V µA µA V V (Note 3) (Note 3) 68 53 48/75 43/64 40/80 37/70 mA mA 0.55 1.45 _ _ _ _ ns/V ns/V 0.85 1.90 _ _ _ _ ns/V ns/V 150m Belden 8281 (Note 7) CAEC = 100 pF (Note 6) CAEC = 100 pF (Note 6) CAEC = 100 pF (Note 6) Rcollector = 75Ω 1.5 2.0 3.2 750 30 1/50 650 _ _ _ _ _ _ _ _ _ _ _ _ _ _ µs µs µs ps ps trans/ns Mbps 311 Mbps PRN (Note 5) 311 Mbps PRN (Notes 3, 5) 150 350 250 500 400 750 pspp pspp Conditions Typ +25˚C Min/Max +25˚C Min/Max −40˚C to +85˚C Units 3 www.national.com Electrical Characteristics Parameter Input and Output Parameters MUTE current input-HIGH MUTE current input-LOW TIMING PERFORMANCE LOS Response Time carrier applied carrier removed MUTE response time MISCELLANEOUS PERFORMANCE input resistance input capacitance input return loss @ 270 MHz maximum cable attenuation (Continued) (VCC = +5V, VEE = 0V, signal source swing = 0.8 Vpp(Note 4), CAEC = 100 pF) Conditions Typ +25˚C Min/Max +25˚C Min/Max −40˚C to +85˚C Units VIH = 5V (Note 3) VIL = 0V (Note 3) 5.0 0.2 ± 100 ± 100 ± 500 ± 500 nA nA (Note 8) (Note 9) (Note 10) single-ended single-ended (Note 11) Zo = 75Ω (Note 12) 200 MHz (Note 13) 150 150 2.0 7.3 1.0 19 40 1000 1000 _ _ _ _ _ 1000 1000 _ _ _ _ _ ns ns ns kΩ pF dB dB Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: J-level: spec. is 100% tested at +25˚C. Note 4: These specifications assume an 800 mVpp signal at the cable input. Levels above and below 800 mV are allowable, but performance may vary. The cable will attenuate the signal prior to entering the equalizer. Note 5: Peak-to-peak jitter is defined as 6 times the rms jitter. Note 6: For more information, see “CLC012 Operation” and “Design Guidelines”. Note 7: 50% eye opening. Note 8: Time from application of a valid signal to when the LOS output asserts high. Note 9: Time from the removal of a valid signal to when the LOS output asserts low. Note 10: Time from assertion of MUTE to when the output responds. Note 11: Device only. Does not include typical pc board parasitics. Note 12: Includes typical pc board parasitics. Note 13: This sets the maximum cable length for the equalizer. Note 14: Human body model, 1.5 kΩ in series with 100 pF; based on limited test data. Note 15: To maintain specified performance, do not reduce DO/DO below this level. www.national.com 4 Typical Performance Characteristics DS100145-5 DS100145-9 DS100145-6 DS100145-10 DS100145-7 DS100145-11 5 www.national.com Typical Performance Characteristics (Continued) DS100145-8 DS100145-12 DS100145-13 DS100145-16 DS100145-14 DS100145-39 www.national.com 6 Typical Performance Characteristics (Continued) DS100145-15 DS100145-40 DS100145-18 DS100145-17 DS100145-38 DS100145-19 7 www.national.com Pin Definitions Name DI, DI DO, DO AEC+, AEC− Pin # 8, 9 13, 14 6, 7 Description Differential data inputs. Differential collector data outputs (ECL compatible). AEC loop filter pins. A capacitor connected between these pins governs the loop response for the adaptive equalization loop. 3 Eye monitor output. The output of the equalization filter. Loss of Signal. (Low when no signal is present). Output MUTE. (Active low.) Loss of Signal (LOS) may be tied to this pin to inhibit the output when no signal is present. VCC VEE 1, 2, 4 10, 11 Positive supply pins (ground or +5V). Negative supply pins (−5.2V or ground). BLOCK DESCRIPTION The CLC012 is an adaptive equalizer that reconstructs serial digital data received from transmission lines such as coaxial cable or twisted pair. Its transfer function approximates the reciprocal of the cable loss characteristic. The block diagram in Figure 2 depicts the main signal conditioning blocks for equalizing digital data at the receiving end of a cable. The CLC012 receives baseband differential or single-ended digital signals at its inputs DI and DI. The Equalizer block is a two-stage adaptive filter. This filter is capable of equalizing cable lengths from zero meters to lengths that require 40 dB of boost at 200 MHz. The Quantized Feedback Comparator block receives the differential signals from the equalizer filter block. This block includes two comparators. The first comparator incorporates a self-biasing DC restore circuit. This is followed by a second high-speed comparator with output mute capability. The second comparator receives and slices the DC-restored data. Its outputs DO and DO are taken from the collectors of the output transistors. MUTE latches DO and DO when a TTL logic low level is applied. The Adaptive Servo Control block produces the signal for controlling the filter block, and outputs a voltage proportional to cable length. It receives differential signals from the output of the filter block and from the quantized-feedback comparator (QFBC) to develop the control signal. The servo loop response is controlled by an external capacitor placed across the AEC+ and AEC− pins. Its output voltage, as measured differentially across AEC+ and AEC−, is roughly proportional to the length of the transmission line. For Belden 8281 coaxial cable this differential voltage is about 1.5 mV/meter. Once this voltage exceeds 500 mV, no additional equalization is provided. The Loss of Signal (LOS) block monitors the signal power out of the equalizing filter and compares it to an internal reference to determine if a valid signal is present. A CMOS high output indicates that data is present. The output of LOS can be connected to the MUTE input to automatically latch the outputs (DO and DO), preventing random transitions when no data is present. The Output Eye Monitor (OEM) provides a single-ended buffered output for observing the equalized eye pattern. The OEM output is a low impedance high-speed voltage driver capable of driving an AC-coupled 100Ω load. OEM LOS MUTE 5 12 Operation The CLC012 Adaptive Cable Equalizer provides a complete solution for equalizing high-bit-rate digital data transmitted over long transmission lines. The following sections furnish design and application information to assist in completing a successful design: • • Block diagram explanation of the CLC012 Recommended standard input and output interface connections • Common applications for the CLC012 • Measurement, PC layout, and cable emulation boxes For applications assistance in the U.S., call 800-272-9959 to contact a technical staff member. DS100145-20 FIGURE 1. CLC012 Equalizer Application Circuit DS100145-21 FIGURE 2. CLC012 Block Diagram www.national.com 8 Input Interfacing The CLC012 accepts either differential or single-ended input voltage specified in Static Performance. The following sections show several suggestions for interfaces for the inputs and outputs of the CLC012. SINGLE-ENDED INPUT INTERFACE: 75Ω Coaxial Cable The input is connected single-ended to either DI or DI as shown in Figure 3. Balancing unused inputs helps to lessen the effects of noise. Use the equivalent termination of 37.4Ω to balance the input impedance seen by each pin. It also helps to terminate grounds at a common point. Resistors Rx and R y are recommended for optimum performance. The equalizer inputs are self-biasing. Signals should be AC coupled to the inputs as shown in Figure 3. the interface threshold levels required by ECL families. Recommended interfaces for standard ECL families are shown in the following circuits. DIFFERENTIAL LOAD-TERMINATED OUTPUT INTERFACE Figure 5 shows a recommended circuit for implementing a differential output that is terminated at the load. A diode or 75Ω resistor provides a voltage drop from the positive supply (+5V for PECL or Ground for ECL operation) to establish proper ECL levels. The resistors terminate the cable to the characteristic impedance. The output voltage swing is determined by the CLC012 output current (10 mA) times the termination resistor. For the circuit in Figure 5, the nominal output voltage swing is 750 mV. DS100145-22 FIGURE 3. Single-Ended 75Ω Cable Input Interface DIFFERENTIAL INPUT INTERFACE: Twisted Pair A recommended differential input interface is shown in Figure 4. Proper voltage levels must be furnished to the input pins and the proper cable terminating impedance must be provided. For Category 5 UTP this is approximately 100Ω. Figure 4 shows a generalized network which may be used to receive data over a twisted pair. Resistors R1 and R2 provide the proper terminating impedance and signal level adjustment. The blocking capacitors provide AC coupling of the attenuated signal levels. The plots in the Typical Performance Characteristics section demonstrate various equalized data rates using Category 5 UTP at 100 meter lengths. A full schematic of a recommended driver and receiver circuit for 100Ω Category 5 UTP is provided in the Typical Applications section with further explanation. DS100145-25 FIGURE 5. Differential Load Terminated Output Interface DIFFERENTIAL SOURCE-TERMINATED OUTPUT INTERFACE Figure 6 is similar to Figure 5 except that the termination is provided at the source. This configuration may also be used for single-ended applications. However, the unused output must still be terminated as shown. DS100145-24 FIGURE 4. Twisted Pair Input Interface Output Interfacing The outputs DO and DO produce ECL logic levels when the recommended output termination networks are used. The DO and DO pins are not complementary emitter coupled logic outputs. Instead, the outputs are taken off of the collectors of the transistors. Therefore, care must be taken to meet 9 DS100145-26 FIGURE 6. Differential Source Terminated Output Interface www.national.com Output Interfacing (Continued) TERMINATING PHYSICALLY SEPARATED OUTPUTS When the two outputs must be routed to physically separate locations, the circuit in Figure 6 may be applied. Alternatively, if load termination is desired, the circuit in Figure 7 may be used. The resistive divider network provides 75Ω termination and establishes proper ECL levels. This circuit consumes slightly more power than the previous circuits. OUTPUT EYE MONITOR OEM CONNECTIONS The OEM is a high-speed, buffered output for monitoring the equalized eye pattern prior to the output comparator. Its output is designed to drive an AC-coupled 50Ω coaxial cable with a series 50Ω backmatch resistor. The cable should be terminated with 50Ω at the oscilloscope. Figure 1 shows a schematic with a typical connection. MINIMUM DATA TRANSITIONS The CLC012 specifies a minimum transition rate. For the CLC012 this sets the minimum data rate for transmitting data through any cable medium. The CLC012 minimum average transition density is found in the Electrical Characteristics section of the datasheet. POWER SUPPLY OPERATION AND THERMAL CONSIDERATIONS The CLC012 operates from either +5V or −5.2V single supplies. Refer to Figure 1 when operating the part from +5V. When operating with a −5.2V supply, the VEE pins should be bypassed to ground. The evaluation board and associated literature provide for operation from either supply. Maximum power dissipation occurs at minimum cable length. Under that condition, ICC = 58 mA. Total power dissipated: PT = (58 mA)(5V) = 290 mW Power in the load: PL = (0.7V)(11 mA) + (37.5)(11 mA)2 = 12 mW Maximum power dissipated on the die: PDMAX = PT–PL = 278 mW Junction Temperature = (θJA)(278 mW) + TA = T A + 26˚C DS100145-27 FIGURE 7. Alternative Load Terminated Output Interface Design Guidelines SELECTING THE AUTOMATIC EQUALIZER CAPACITOR The AEC capacitor sets the loop time constant τ for the equalizer’s adaptive loop response time. The following formula is used to set the loop time constant: τ = R • CAEC • 10 −6 R is a conversion factor that is set by internal equalizer parameters and cable length. For Belden 8281 coaxial cable, the R values are (τ = µs, CAEC in pF): Cable Length 100 meters 200 meters 300 meters R Value (Ohms) 15000 20000 32000 Layout and Measurement The printed circuit board layout for the CLC012 requires proper high-speed layout to achieve the performance specifications found in the datasheet. The following list contains a few rules to follow: 1. Use a ground plane. 2. Decouple power pins with 0.1 µF capacitors placed ≤ 0.1” (3mm) from the power pins. 3. Design transmission strip lines from the CLC012’s input and output pins to the board connectors. 4. Route outputs away from inputs. 5. Keep ground plane ≥ 0.025” (0.06mm) away from the input and output pads. For example, a CAEC value of 100 pF results in an adaptive loop time constant of 2 µs at 200 meters of cable. CONNECTION AND OPERATION OF LOS AND MUTE Loss of Signal (LOS) is a CMOS output that indicates the presence of equalized data from the filter. This LOS output can be connected to MUTE to suspend changes in the data outputs DO and DO, if no valid signal exists. This simple configuration prevents random output transitions due to noise. For sparse transition patterns it is recommended that a capacitor be connected to LOS as shown in Figure 1. Add a capacitor to pin 5 to slow the response time of Loss of Signal when LOS is connected to MUTE. The capacitor reduces sensitivity to pathological patterns. Pathological patterns are defined as sparse data sequences with few transitions. Figure 8 shows a block level measurement diagram, while Figure 15 on depicts a detailed schematic. A pseudo-random pattern generator with low output jitter was used to provide a NRZI pattern to create the eye diagrams shown in the Typical Performance Characteristics section. Since most pattern generators have a 50Ω output impedance, a translation can be accomplished using a CLC005 Cable Driver as an impedance transformer. A wide bandwidth oscilloscope is needed to observe the high data rate eye pattern. When monitoring a single output that is terminated at both the equalizer output and the oscilloscope, the effective output load is 37.4Ω. Consequently, the signal swing is half that observed for a single-ended 75Ω termination. www.national.com 10 Layout and Measurement (Continued) DS100145-28 FIGURE 8. Typical Measurement Block Troubleshooting with scope probes can affect the equalization. For high data rates, use a low capacitance probe with less than 2 pF probe capacitance. Evaluation boards and literature are available for quick prototyping and evaluation of the CLC012 Adaptive Cable Equalizer. The CLC012 contains CMOS devices and operators should use grounding straps when handling the parts. Figure 9 shows the CLC012’s internal power supply routing. Bypass VCC (pin 4) by: • Monolithic capacitor of about 0.1 µF placed less than 0.1” (3mm) from the pin The input lines of the CLC012 use a 100Ω series resistors at the input pins. This decreases the inductive effects internal to the part to reduce ringing on fast rise and fall times. Refer to the evaluation board layout for further suggestions on layout for the CLC012 Adaptive Equalizer. EQUALIZATION CURVE The CLC012 Adaptive Cable Equalizer has a maximum equalization response as shown in Figure 10. This response may be obtained by forcing > 0.5V differentially at the AEC pins. • Tantalum capacitor of about 6.8 µF for large current signal swings placed as close as convenient to the CLC012 DS100145-30 FIGURE 10. Maximum Equalization Response DS100145-29 FIGURE 9. Power Package Routing Fixture To minimize ringing at the CLC012’s inputs, place a 100Ω resistor in series with the input. This resistor reduces inductance effects. Several layout techniques can improve high speed performance: • Keep input, output and AEC traces well separated • Use balanced input termination’s • Avoid routing traces close to the CLC012’s input trace • Maintain common return points for components • Use guard traces 11 CABLE EMULATION BOXES Some cable emulation boxes will not mimic cables correctly. When evaluating the CLC012, it is strongly recommended that actual cable be used to determine the various performance parameters. Typical Applications COAXIAL CABLE RECEIVER (Page 1) The CLC012 equalizer application shown on page 1 will equalize a variety of coaxial cables up to lengths that attenuate the signal by 40 dB at 200 MHz. The application shows the proper connection for a single cable driven with a www.national.com Typical Applications (Continued) CLC005 driver. Loss of Signal (LOS) is connected to MUTE to latch outputs DO and DO in the absence of an input signal to the equalizer. Refer to the CLC012’s evaluation board layout for additional suggestions. National can supply most of the major components required to design a transmission line repeater. Figure 11 shows a typical repeater design using the CLC005, CLC012, and the CLC016. The design functions supported by each chip are: CLC005: Cable connection chip Boosts drive for transmission to next repeater or final destinations CLC012: Receive serialized digital data from incoming transmission lines Equalizes the incoming data CLC016: Retimes the equalized data (improving jitter) The CLC016 is a multi-rate data retiming PLL. The circuit (Figure 11) will work at up to 4 different data rates with no additional components or manual tuning. DS100145-31 FIGURE 11. Typical Repeater Design DIGITAL VIDEO (SDV) ROUTERS The CLC012 provides performance that complies with the ITU-T G.703 standard for serial digital data transmission over coaxial cable. One common application is in routers, which provide a switching matrix for connecting source equipment to destination equipment. Figure 12 shows a typical configuration for a router, including equalizers, a crosspoint switch, data retimers, and cable drivers. The CLC012 is used in its standard configuration in this application, and automatically equalizes cable lengths from zero meters to greater than 300 meters at 360 MHz (see plots in Typical Performance Characteristics section). The equalized outputs are connected to the differential inputs of the crosspoint switch. The CLC016 Data Retimer receives the data from the crosspoint and performs the clock and data recovery functions, further reducing jitter. Finally, the retimed data is driven into the coaxial cable by a CLC005 ITU-T G.703 Cable Driver (with two amplitude-adjustable outputs). DS100145-32 FIGURE 12. Data Routing Block Diagram TWISTED PAIR DRIVER A low-cost medium for transmitting data is twisted pair. Category 5 UTP has an attenuation characteristic similar to Belden 8281 coaxial cable but scaled in length: 120 meters of Category 5 UTP is roughly equivalent to 300 meters of Belden 8281 cable. When properly implemented, the CLC012 will equalize data rates up to 625 Mbps over Category 5 UTP. The maximum data rate depends upon the cable length. A plot of Maximum Data Rate vs Cable Length www.national.com 12 Typical Applications (Continued) is found in the Typical Performance Characteristics section for Belden 8281, and can be scaled as stated above to estimate maximum cable lengths and data rates for UTP. Category 5 UTP has a characteristic impedance of approximately 100Ω. The CLC005 in Figure 13 is used to drive the twisted pair AC-coupled with a series 0.1 µF capacitor and a 50Ω resistor in each differential output. The CLC012 Adaptive Equalizer requires 800 mVpp from the transmit side of the cable. A voltage divider is necessary to scale the voltage to the required level at the input of the CLC012. This resistor network also provides the correct impedance match for twisted pair. For Category 5 UTP, the approximate AEC voltage per length is 3.75 mV/m (see Block Description ). The CLC005 provides a trim adjust for fine tuning the output signal with the resistor R. Refer to the CLC005 datasheet for tuning directions. DS100145-33 FIGURE 13. Twisted Pair Equalization DS100145-34 FIGURE 14. Before and After Equalization at 622 Mbps Through 50 Meters of Category 5 UTP DS100145-35 FIGURE 15. Typical Measurement Setup 13 www.national.com Evaluation Board An evaluation board layout and schematic are shown on the following pages. The artwork shows the board solder masks, trace layers, and ground plane. To order an evaluation board contact your local sales representative or National support center and request part number CLC730063. The evaluation board provides an LED and switches to operate the CLC012 in various modes of operation. The power supplies, which must be correctly connected and jumpered for positive or negative voltage operation, are identified on the printed board silk screen. Insert all tantalum capacitors as shown in the schematic or silk screen. A complete bill of materials is given in the accompanying table. DS100145-36 FIGURE 16. Evaluation Board Schematic www.national.com 14 Evaluation Board (Continued) CLC012 Equalizer Evaluation Board Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 U1 D1 Reference Designator Q1 CR1 J1, J2, J3, J4, J5 J6 J7 R6, R7 R8, R9, R10, R11 R13 R3, R4 R1, R2 R14 R12 R5 C2, C3, C9, C12 C4, C7, C8, C10, C11 C1 C5, C6 2N3904 transistor 1N4148 switching diode receptacle vertical BNC PC Amphenol #31-5329-52RFX banana jack, black, EF Johnson #108-0903-001 banana jack, red, EF Johnson #108-0902-001 10 kΩ, 1/8W, 1206, 1% chip resistors 75Ω, 1/8W, 1206, 1% chip resistors 1.33 kΩ, 1/8W, 1206, 1% chip resistors 10Ω, 1/8W, 1206, 1% chip resistors 100Ω, 1/8W, 1206, 1% chip resistors 20 kΩ, 1/8W, 1206, 1% chip resistors 2 kΩ, 1/8W, 1206, 1% chip resistors 49.9Ω, 1/8W, 1206, 1% chip resistors 0.01 µFd, 10% X7R surface mount cap 0.1 µFd, 10% X7R surface mount cap 100 pFd, 5% NPO surface mount cap 10 µFd, 16V tantalum capacitor CLC730063 printed circuit board CLC012AJE LED, GENERAL PURPOSE 4. 5. Description Quantity 1 1 5 1 1 2 4 1 2 2 1 1 1 3 5 1 2 1 1 1 LAYOUT The CLC012 requires proper high-speed layout techniques to obtain best results. A few recommended layout rules to follow for best results when using the CLC012 Adaptive Cable Equalizer are: 1. Use a ground plane. 2. Decouple power pins with 0.01 µF capacitors placed ≤ 0.1” (3mm) from the power pins. 3. Design transmission lines to the inputs and outputs. Route outputs away from inputs. Remove ground plane ≥ 0.025” (0.06mm) from the input and output pads. The solder masks with component locations, trace layer, and ground plane board layer are given below. Note that the CLC012 uses the same Evaluation Board as the CLC014. LOS is labeled CD on the Evaluation Board. 15 www.national.com Evaluation Board (Continued) DS100145-37 www.national.com 16 17 CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin SOIC Order Number CLC012AJE NS Package Number M14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.