CLC407AJ

Comlinear CLC407 Low-Cost, Low-Power, Programmable Gain Buffer with Disable August 1996 N Comlinear CLC407 Low-Cost, Low-Power Programmable Gain Buffer with Disable General Description The Comlinear CLC407 is a low-cost, high-speed (110MHz) buffer which features user-programmable gains of +2, +1, and -1 V/V. This high-performance part has the added versatility of a TTL-compatible disable which quickly switches the buffer off in 18ns and back on in 40ns. The CLC407’s high 60mA output current, coupled with its ultra-low 35mW power consumption makes it the ideal choice for demanding applications that are sensitive to both power and cost. Utilizing Comlinear’s proven architectures, this current feedback amplifier surpasses the performance of alternate solutions with a closed-loop design that produces new standards for buffers in gain accuracy, input impedance, and input bias currents. The CLC407’s internal feedback network provides an excellent gain accuracy of 0.1%. High source impedance applications will benefit from the CLC407’s 6MΩ input impedance along with its exceptionally low 100nA input bias current. With 0.1dB flatness to 30MHz and low differential gain and phase errors, the CLC407 is very useful for professional video processing and distribution. A 110MHz -3dB bandwidth coupled with a 350V/µs slew rate also make the CLC407 a perfect choice in cost-sensitive applications such as video monitors, fax machines, copiers, and CATV systems. Back-terminated video applications will especially appreciate +2 gains which require no external gain components reducing inventory costs and board space. Features s s s s s s s s s Low-cost High output current: 60mA High input impedance: 6MΩ Gains of +1, +2 with no external components Low power: Icc = 3.5mA Ultra-fast enable/disable times Very low input bias currents: 100nA Excellent gain accuracy: 0.1% High speed: 110MHz -3dB BW Desktop video systems Multiplexers Video distribution Flash A/D driver High-speed switch/driver High-source impedance applications Peak detector circuits Professional video processing High resolution monitors Frequency Response (AV = +2V/V) Applications s s s s s s s s s Typical Application 2:1 Mux Cable Driver Pinout DIP & SOIC NOTE: All necessary components are shown. © 1996 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC407 Electrical Characteristics (AV = +2, Vcc = + 5V, RL = 100Ω unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC407AJ TYP +25˚C 110 42 30 0 0.1 0.3 0.03 0.01 0.25 0.08 5 18 3 350 650 -72/-52 -70/-57 5 12 3 1 30 100 3 1 17 2.5 ±0.1% 250 52 50 3.5 0.8 40 18 85 MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C 75 31 15 0.4 0.5 0.6 0.05 0.4 50 27 0.6 0.65 0.7 0.06 0.5 45 26 0.8 0.7 0.7 0.07 0.55 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 1.0Vpp Vout < 5.0Vpp ±0.1dB bandwidth Vout < 1.0Vpp gain flatness Vout < 1.0Vpp peaking DC to 200MHz rolloff 1MHz non-inverting current >1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift output offset voltage amplifier gain error internal feedback resistor (Rf) power supply rejection ratio common-mode rejection ratio supply current disabled SWITCHING PERFORMANCE turn on time turn off time off isolation high input voltage low input voltage -46 -50 6.3 15 3.8 5 900 5 13 ±1.0% ±20% 47 45 4.0 0.9 55 26 80 2 0.8 3 2 1.8 +3.9,-3.2 44 0.2 -45 -47 6.6 16 4 7 50 1600 8 6 40 17 ±1.0% 46 44 4.1 0.95 58 30 80 2 0.8 2.4 2 1.7 +3.8,-3.1 38 0.25 -44 -46 6.7 17 4.2 8 50 2800 11 8 45 19 ±1.0% 45 43 4.4 1 58 32 80 2 0.8 1 2 1.5 +3.7,-2.8 20 0.4 B, C B, C non-inverting inverting A A,3 A B A A DC DC RL= ∞ RL= ∞ to >50dB attn. @ 10MHz 10MHz VIH VIL MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting common mode input range output voltage range RL= ∞ output current output resistance, closed loop 6 1 ±2.2 +4.0,-3.3 60 0.06 Recommended gain range +1, +2 V/V Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage Iout is short circuit protected to ground common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) http://www.national.com Notes ±7V 1) At temps < 0˚C, spec is guaranteed for RL = 500Ω. 2) An 825Ω pull-down resistor is connected between Vo and -Vcc. 3) Source impedance 1kΩ. A) J-level: spec is 100% tested at +25˚C, sample tested at +85˚C. LC/MC-level: spec is 100% wafer probed at +25˚C. B) J-level: spec is sample tested at +25˚C. C) Guaranteed at 10MHz. ±Vcc +175˚C -65˚C to +150˚C +300˚C 2 CLC407 Typical Performance Characteristics (AV = +2, Rf = 250Ω: Vcc = + 5V, RL = 100Ω unless specified) Frequency Response AV+1 Gain RL =1k Gain VO =2Vpp VO =5Vpp VO =1Vpp Frequency Response vs. RL Frequency Response vs. Vout (Av = +2) Magnitude (1dB/div) Magnitude (1dB/div) Gain AV+2 Phase AV -1 Magnitude (1dB/div) Phase (45 o/div) Phase (deg) Phase (deg) RL =50 Phase RL =100 VO =0.2Vpp Phase 0 -45 -90 -135 -180 0 VO =0.2Vpp VO =5Vpp VO =2Vpp VO =1Vpp AV+1 AV+2 AV-1 RL =50 RL =1k RL =100 -45 -90 -135 -180 100 1 10 100 1 10 100 1 10 Frequency (MHz) Frequency Response vs. Vout (Av = +1) VO =0.2Vpp Gain VO =1Vpp Gain Frequency (MHz) Frequency Response vs. Vout (Av = -1) VO =2Vpp Gain VO =0.2Vpp Frequency (MHz) Frequency Response vs. Capacitive Load CL =1kpF Rs=10 CL =100pF Rs= 30 CL =10pF Rs=100 Magnitude (1dB/div) Magnitude (1dB/div) VO =2Vpp Magnitude (1dB/div) Phase (deg) Phase (deg) Phase (deg) VO =4Vpp Phase VO =4Vpp VO =2Vpp VO =0.2Vpp VO =1Vpp VO =4Vpp Phase VO =4Vpp VO =1Vpp VO =2Vpp VO =0.2Vpp VO =1Vpp 0 -45 -90 -135 -180 100 -180 -225 -270 -315 -360 Phase 0 CL =1kpF CL =10pF CL =100pF -45 -90 -135 -180 100 1 10 1 10 100 1 10 Frequency (MHz) Maximum Output Voltage vs. RL Maximum Output Voltage (Vpp) 7.0 Frequency (MHz) Gain Flatness & Linear Phase Deviation 100 Frequency (MHz) Equivalent Input Noise 100 Noise Voltage (nV/√Hz) 6.0 5.0 4.0 3.0 2.0 0 100 200 300 400 500 Magnitude (0.1dB/div) Gain Noise Current (pA/√Hz) LPD (0.5o/div) Phase Inverting Current = 12pA/√Hz 10 Voltage = 5nV/√Hz Non-Inverting Current = 3pA/√Hz 10 1 1 0 15 30 100 1k 10k 100k 1M 10M Load (Ω) 2nd & 3rd Harmonic Distortion -40 -50 -45 Vo = 2Vpp Frequency (MHz) 2nd Harmonic Distortion vs. Pout -45 10dBm = 2Vpp 0dBm = .63Vpp 10MHz 5MHz + - Frequency (Hz) 3rd Harmonic Distortion vs. Pout 50Ω 50Ω Pout 10MHz Distortion (dBc) Distortion (dBc) Distortion (dBc) -55 + -55 5MHz -60 2nd Rl = 100 50Ω 50Ω Pout -65 - -65 1MHz -70 -80 3rd Rl = 100 1MHz -75 500KHz -75 10dBm = 2Vpp 0dBm = .63Vpp 500KHz 2nd Rl = 1k 3rd Rl = 1k -90 0.1 1 10 -85 -10 0 10 -85 -10 0 10 Frequency (MHz) Output Resistance vs. Frequency 50 -20 -40 Output Power (dBm) Forward & Reverse Isolation During Disable 0.20 Output Power (dBm) Differential Gain & Phase 1.00 Output Resistance (20log Zout) Differential Phase (deg) Differential Gain (%) 30 0.15 Phase 0.75 Gain (dB) 10 -10 -30 -50 1 10 100 -60 -80 Reverse 0.10 Gain 0.50 -100 Forward 0.05 0.25 -120 1 10 100 0 1 2 3 4 0 Frequency (MHz) Frequency (MHz) Number of 150Ω Loads 3 http://www.national.com CLC407 Typical Performance Characteristics (AV = +2, Rf = 250Ω: Vcc = + 5V, RL = 100Ω unless specified) Settling Time, Ts(ns) to 0.05% Error Small Signal Pulse Response 0.20 AV+2 Large Signal Pulse Response 2.0 AV+2 Settling Time vs. Capacitive Load 50 + 100 Rs 250Ω CL 1k CLC407 - Output Voltage Output Voltage 0.10 1.0 40 30 20 Ts Vo = 2V step 80 60 40 250Ω Rs (Ω) 0.00 0.0 Rs -0.10 AV-1 -1.0 AV-1 10 0 10 100 20 0 1000 -0.20 -2.0 Time (5ns/div) Time (5ns/div) CL (pF) Short Term Settling Time 0.2 Vout = 2Vstep PSRR and CMRR 60 4.0 PSRR IBI, IBN, VIO vs. Temperature 1.0 IBN Offet Voltage, VIO (mV) Vout (% Final Value) 0.1 PSRR/CMRR (dB) 50 40 30 20 10 CMRR 3.0 2.0 1.0 0 -1.0 VIO IBI 0 IBI, IBN (µA) -1.0 -2.0 -3.0 -4.0 0.0 -0.1 -0.2 0 20 40 60 80 100 10k 100k 1M 10M 100M -60 -20 20 60 100 140 Time (ns) Frequency (Hz) Temperature (oC) CLC407 OPERATION Closed Loop Gain Selection The CLC407 is a current feedback op amp with Rf = Rg = 250Ω on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and -1V/V by connecting pins 2 and 3 as described in the chart below. Gain Acl -1V/V +1V/V +2V/V Input Connections Non-Inverting (pin3) Inverting (pin2) ground input signal input signal input signal NC (open) ground Minimize this capacitive coupling during layout by removing ground plane near pins 1, 2, and 3. This minimization should produce a response similar to the plot labeled “open” in Graph 1. If desired flatness is greater than plot “open” in Graph 1, two options remain to further flatten the frequency response. First, try shorting the inverting input (pin 2) to the non-inverting input (pin 3). This response is labeled “short” in Graph 1. Next, try inserting a 300Ω resistor R between the non-inverting input (pin 2) as shown in Figure 1. This response is labeled “300Ω ” in Graph 1. Notice an “open” produces a response with obvious peaking and maximum bandwidth, a “short” minimizes peaking and bandwidth, and finally 300Ω slightly extends bandwidth with minimal peaking. Frequency Response vs. Unity Gain Configuration Open Magnitude (1dB/div) The gain accuracy of the CLC407 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of ˜ 2000ppm/°C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer . Non-Inverting Unity Gain Considerations (Av = +1V/V) Achieve a gain of +1V/V by removing all resistive and capacitive connections between pin 2 and ground plane. Any capacitive coupling between pin 2 and ground will cause high frequency peaking in the frequency domain response and overshoot in the time domain response. 4 300Ω Short 1 10 100 Frequency (MHz) Graph 1 http://www.national.com 1 2 SMA Input Rin 50Ω R 3 4 8 7 6 Rout 50Ω CLC407 5 SMA Output Input - Bias Current, Impedances, and Source Termination Considerations The CLC407 has: • a 6MΩ non-inverting input impedance. • 100nA non-inverting input bias current. If a large source impedance application is considered, remove all parasitic capacitance around the non-inverting input and source traces. Parasitic capacitances near the input and source act as a low-pass filter and reduce bandwidth. Current feedback op amps have uncorrelated input bias currents. These uncorrelated bias currents prevent source impedance matching on each input from cancelling offsets. Refer to application note OA-07 of the data book to find specific circuits to correct DC offsets. Layout Considerations Whenever questions about layout arise, USE THE EVALUATION BOARD AS A TEMPLATE. Use the 730013 and 730026 evaluation boards for the DIP and SOIC respectively. These board layouts were optimized to produce the typical performance of the CLC407 shown in the data sheet. To reduce parasitic capacitances, the ground plane was removed near pins 2, 3, and 6. To reduce series inductance, trace lengths of components and nodes were minimized. Parasitics on traces degrade performance. Minimize coupling from traces to both power and ground planes. Use low inductance resistors for leaded components . Do not use dip sockets for the CLC407 DIP amplifiers. These sockets can peak the frequency domain response or create overshoot in the time domain response. Use flush-mount socket pins if socketing cannot be avoided. The 730013 circuit board device holes are sized for Cambion P/N 450-2598 socket pins or their functional equivalent. Insert the back matching resistor Rout shown in Figure 3 when driving coaxial cable or a capacitive load. Use the plot in the typical performance section labeled “Settling Time vs. Capacitive Load” to determine the optimum resistor value for Rout for different capacitive loads. This optimal resistance improves settling time for pulse-type applications and increases stability. 1 J1 = 0Ω SMA Input Rin 50Ω 2 3 4 C2 0.1µfd 8 7 6 +5V C1 C3 + 0.1µfd 6.8µfd Rout SMA Output 50Ω -5V C4 6.8µfd + Figure 1 Enable/Disable Operation Using +5V Supplies The CLC407 has a TTL & CMOS logic compatible disable function. Apply a logic low (i.e. < 0.8V) to pin 8, and the CLC407 is guaranteed disabled across its temperature range. Apply a logic high to pin 8, (i.e. > 2.0V) and the CLC407 is guaranteed enabled. Voltage, not current, at pin 8 determines the enable/disable state of the CLC407. Disable the CLC407 and its inputs and output become high impedances. While disabled, the CLC407’s quiescent power drops to 8mW. Use the CLC407’s disable to create analog switches or multiplexers. Implement a single analog switch with one CLC407 positioned between an input and output. Create an analog multiplexer with several CLC407s. Tie the outputs together and put a different signal on each CLC407 input. Operate the CLC407 without connecting pin 8. An internal 20kΩ pull-up resistor guarantees the CLC407 is enabled when pin 8 is floating. Enable/Disable Operation for Single or Unbalanced Supply Operation Pin 7 +Vcc 20kΩ Pull-up Resistor Pin 8 Disable Supply Mid-Point 20kΩ Bias Circuitry Vcc -Vee 2 Q2 20kΩ Q1 I Tail CLC407 NOTE: Pins 4, 7, 8 are external Pin 4 -Vee Figure 2 Figure 2 illustrates the internal enable/disable operation of the CLC407. When pin 8 is left floating or is tied to +Vcc, Q1 is on and pulls tail current through the CLC407 circuitry. When pin 8 is less than 0.8V above the supply mid-point, Q1 stops tail current from flowing in the bias circuitry. The CLC407 is now disabled. Disable Limitations The internal feedback resistor, Rf limits off isolation in inverting gain configurations. Do not apply voltages greater than +Vcc or less than -Vee to pin 8. 5 CLC407 5 Figure 3 http://www.national.com Use power-supply bypassing capacitors when operating this amplifier. Choose quality 0.1µF ceramics for C1 and C2. Choose quality 6.8µF tantalum capacitors for C3 and C4. Place the 0.1µF capacitors within 0.1 inches from the power pins. Place the 6.8µF capacitors within 3/4 inches from the power pins. Special Evaluation Board Considerations for the CLC407 To optimize off-isolation of the CLC407, cut the Rf trace on both the 730013 and the 730027 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 4 shows where to cut both evaluation boards for improved off-isolation. OUT 1 J1 = 0Ω SMA Input Rin 50Ω 2 3 4 8 7 6 +5V C1 C3 + 0.1µfd 6.8µfd Rout SMA Output 50Ω Rpd IEX -5V + CLC407 5 C2 0.1µfd C4 6.8µfd Figure 5 Video Cable Driver The CLC407 was designed to produce exceptional video performance at all three closed-loop gains. At the noninverting gain of 2V/V configuration, back terminate the cable using Rout. A typical cable driving configuration is shown below in Figure 6. 1 8 7 6 C1 0.1µfd Rout 50Ω -5V C2 0.1µfd C4 6.8µfd + C3 6.8µfd +5V + Video Output 50Ω + C3 C4 R2 R8 RF C1 R7 C5 ROUT C6 C2 R6 R3 R1 + C8 R5 R4 RIN C7 A National Semiconductor Company Comlinear (303) 226-0500 J1 = 0Ω SMA Input Rin 50Ω RG 730013 REV C 2 3 4 -Vcc GND +Vcc IN CLC407 Cut trace here Cut trace here 407 Fig 3 (Right) 5 Coax 50Ω Figure 4 Video Performance vs. IEX Improve the video performance of the CLC407 by drawing extra current from the amplifier’s output stage. Using a single external resistor as shown in Figure 5, you can adjust the differential phase. Video performance vs. IEX is illustrated below in Graph 2. This graph represents positive video performance with negative synchronization pulses. Differential Gain & Phase vs. IEX 0.25 0.20 0.15 0.10 0.05 Gain Figure 6 N:1 Mux Cable Driver The CLC407 is capable of multiplexing several signals on a single analog output bus. The front page shows how a 2:1 multiplexer is implemented. An N:1 multiplexer is implemented in an analogous fashion by using an N:1 decoder to enable/disable the appropriate number of CLC407’s. 0.25 Differential Phase (deg) Differential Gain (%) Phase 0.20 0.15 0.10 0.05 0 Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) CerDip qjc 75˚/W 130˚/W 65˚/W qjA 125˚/W 150˚/W 155˚/W Ordering Information 6 8 10 12 14 16 18 0 0 2 4 Model Temperature Range Description 8-pin PDIP 8-pin SOIC 8-pin CerDIP dice 8-pin CerDIP, MIL-STD-883 dice, MIL-STD-883 DESC SMD number. IEX in mA 405 G h1 Graph 2 The value for Rpd in Figure 5 is determined by: Rpd = at +5V supplies. 5 IEX CLC407AJP -40˚C to +85˚C CLC407AJE -40˚C to +85˚C CLC407AIB -40˚C to +85˚C CLC407ALC -40˚C to +85˚C CLC407A8B -55˚C to +125˚C CLC407AMC -55˚C to +125˚C Contact factory for other packages and http://www.national.com 6 This page intentionally left blank. 7 http://www.national.com Comlinear CLC407 Low-Cost, Low-Power, Programmable Gain Buffer with Disable Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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