CLC412

CLC412 Dual Wideband Video Op Amp June 1999 N CLC412 Dual Wideband Video Op Amp General Description The CLC412 combines a high-speed complementary bipolar process with National's current-feedback topology to produce a very highspeed dual op amp. The CLC412 provides a 250MHz small-signal bandwidth at a gain of +2V/V and a 1300V/µs slew rate while consuming only 50mW per amplifier from ±5V supplies. The CLC412 offers exceptional video performance with its 0.02% and 0.02° differential gain and phase errors for NTSC and PAL video signals while driving one back terminated 75Ω load. The CLC412 also offers a flat gain response of 0.1dB to 30MHz and very low channel-to-channel crosstalk of -76dB at 10MHz. Additionally, each amplifier can deliver a 70mA continuous output current. This level of performance makes the CLC412 an ideal dual op amp for highdensity broadcast-quality video systems. The CLC412's two very well-matched amplifiers support a number of applications such as differential line drivers and receivers. In addition, the CLC412 is well suited for Sallen Key active filters in applications such as anti-aliasing filters for high-speed A/D converters. Its small 8-pin SOIC package, low power requirement, low noise and distortion allow the CLC412 to serve portable RF applications such as IQ-channels. The CLC412 is available in the following versions. CLC412AJP CLC412AJE CLC412AIB CLC412A8B CLC412A8L-2A CLC412AMC -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C -55°C to +125°C 8-pin Plastic DIP 8-pin Plastic SOIC 8-pin CERDIP 8-pin CERDIP, MIL-STD-883, Level B 20-pin LCC, MIL-STD-883, Level B dice, MIL-STD-883, Level B Features Wide bandwidth: 330MHz (Av=+1V/V) 250MHz (Av=+2V/V) s 0.1dB gain flatness to 30MHz s Low power: 5mA/channel s Very low diff. gain, phase: 0.02%, 0.02° s -76dB channel-to-channel crosstalk (10MHz) s Fast slew rate: 1300V/µs s Unity-gain stable s Applications s s s s s s HDTV, NTSC & PAL video systems Video switching and distribution IQ amplifiers Wideband active filters Cable drivers DC coupled single-to-differential conversions DESC SMD number: 5962-94719 Typical Application Sallen-Key Low-Pass Filter Pinout Vin + R1 R2 C2 C1 + ½CLC412 DIP & SOIC Rin Ko Vout Vin = R1R 2 C1C 2 ½CLC412 Vout Rf Rg Vout1 Vinv1 Vnon-inv1 -Vcc 1 2 3 4 + + 8 7 6 5 +Vcc Vout2 Vinv2 Vnon-inv2 Rf - 1 1− K 9  1 1 s + s + + +  R1C1 R 2 C 2 R 2 C 2  R1R 2 C1C 2   2 © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC412 Electrical Characteristics (AV = +2; Rf = 634Ω ; VCC = ±5V; RL = 100Ω ) PARAMETERS Ambient Temperature CONDITIONS CLC412 AJ TYP +25°C MIN/MAX RATINGS -40°C +25°C +85°C UNITS SYMBOL FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 0.5Vpp Vout < 4.0Vpp gain flatness Vout < 0.5Vpp peaking DC to 30MHz rolloff DC to 30MHz linear phase deviation DC to 75MHz differential gain 4.43MHz, RL=150Ω differential phase 4.43MHz, RL=150Ω TIME DOMAIN RESPONSE rise and fall time 0.5V step 4V step settling time to 0.05% 2V step overshoot 0.5V step slew rate 2V step DISTORTION AND NOISE RESPONSE 2Vpp, 20MHz 2nd harmonic distortion 2Vpp, 20MHz 3rd harmonic distortion 10MHz 3rd order intermodulation intercept equivalent noise input non-inverting voltage >1MHz inverting current >1MHz non-inverting current >1MHz noise floor >1MHz crosstalk input-referred 10MHz STATIC DC PERFORMANCE *input offset voltage average drift *input bias current average drift *input bias current average drift power supply rejection ratio common mode rejection ratio *supply current 250 105 0.1 0.1 0.5 0.02 0.02 1.4 3.2 12 8 1300 - 46 - 50 43 3.0 12.0 2.0 - 157 - 76 ±2 ± 30 ±5 ± 30 ±3 ± 20 50 50 10.2 1000 1.0 0.04 + 3.8,-3.3 + 3.1,-2.9 ± 2.2 70 150 80 0.1 0.4 1.3 0.04 0.04 2.3 4.4 18 15 1000 - 42 - 46 3.4 13.9 2.6 - 156 - 70 ± 10 ± 60 ± 28 ± 187 ± 34 ± 125 46 45 13.6 175 80 0.1 0.3 1.0 0.04 0.04 2.0 4.4 18 15 1000 - 42 - 46 3.4 13.9 2.6 - 156 - 70 ±6 ____ 135 65 0.2 0.3 1.0 0.08 0.08 2.6 4.8 20 15 800 - 38 - 42 3.8 15.5 3.0 - 155 - 70 ± 12 ± 60 ± 12 ± 90 ± 20 ± 80 44 43 12.8 MHz MHz dB dB deg % deg ns ns ns % V/µs dBc dBc dBm1Hz nV/√Hz pA/√Hz pA/√Hz dBm1Hz dB mV µV/°C µA nA/°C mA nA/°C dB dB mA kΩ pF Ω V V V V mA SSBW LSBW GFP GFR LPD DG DP TRS TRL TSS OS SR HD2 HD3 IMD VN NICN ICN SNF XTLKA VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC RIN CIN ROUT VO VOL VOLC CMIR IO non-inverting inverting DC DC RL= ∞ ± 12 ____ ± 15 ____ 46 45 12.8 MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting output resistance closed loop output voltage range RL= ∞ RL=100Ω RL=100Ω (0° to 70°C) input voltage range common mode output current 300 500 500 2.0 2.0 2.0 0.6 0.3 0.2 + 3.6,-2.9 + 3.7,-3.0 + 3.7,-3.0 + 2.0,-2.5 ± 2.7 ± 2.7 + 2.5,-2.6 ± 1.4 ± 2.0 ± 2.0 25 45 45 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings V cc Iout ±7V short circuit protected to ground, however maximum reliabiliy is obtained if Iout does not exceed... Miscellaneous Ratings Recommended gain range Notes: * AJ : 100% tested at +25°C. ±1 to ±10V/V common-mode input voltage maximum junction temperature operating temperature range: AJ storage temperature range lead temperature (soldering 10 sec) ESD (100V machine test) 125mA ±V cc +150°C -40°C to +85°C -65°C to +150°C +300°C 1000V Package Thermal Resistance Package AJP AJE A8B θ JC 70°C/W 65°C/W 40°C/W θ JA 125°C/W 145°C/W 130°C/W Reliability Information Transistor count 68 http://www.national.com 2 3 http://www.national.com http://www.national.com 4 +Vcc + C3 Rf +Vcc C1 Vin Rin + ½CLC412 + Vout Ro C3 C1 Vin Rg ½CLC412 C2 + C4 Rf Vout Ro + C2 Rb + C4 -Vcc -Vcc Rg Figure 1 Application Introduction Offered in an 8-pin package for reduced space and cost, the wideband CLC412 dual current-feedback op amp provides closely matched DC & AC electrical performance characteristics making the part an ideal choice for wideband signal processing. Applications such as broadcast-quality video systems, IQ amplifiers, filter blocks, high-speed peak detectors, integrators and transimpedance amplifiers will all find superior performance in the CLC412 dual op amp. Feedback Resistor Selection The loop gain and frequency response for a currentfeedback operational amplifier is determined largely by the feedback resistor, Rf. The Electrical Characteristics and Typical Performance plots specify an Rf of 634Ω, a gain of +2V/V and operation with ±5V power supplies (unless otherwise stated). Generally, lowering Rf from its recommended value will peak the frequency response and extend the bandwidth while increasing its value will roll off the response. Reducing the value of Rf too far below its recommended value will cause overshoot, ringing and eventually oscillation. Figure 2 and phase response to the value of the feedback resistor, Rf. For more information see Application Note OA-13 which describes the relationship between Rf and closedloop frequency response. When configuring the CLC412 for other inverting or noninverting gains, it is necessary to adjust the value of the feedback resistor in order to optimize the device’s frequency and phase response. The two plots below provide the means of selecting the recommended feedback-resistor value for both inverting and non- The plot above labeled "Frequency Response vs. Rf" shows the CLC412’s frequency and phase response as Rf is varied while the gain remains constant at +2V/V (RL=100Ω). This plot shows that one particular value of Rf will optimize the frequency and phase response at the specified gain setting, i.e. 634Ω at a gain of +2V/V. Current-feedback op amps, unlike voltage-feedback op amps, have a direct relationship between their frequency 5 inverting gain selections. Both plots show the value of Rf approaching a non-zero minimum (dashed line) at high gains, which is characteristic of current-feedback op amps, while the linear portion of the two (solid) curves (i.e. -5>Av>+6) results from the limitation placed on Rg (i.e. Rg ≥50Ω). This limitation is due to the desire to keep Rg greater in value than that of the inverting input resistance. Therefore, the resulting small-signal http://www.national.com bandwidth curves, labeled "BW", correspond to the two (solid) "Rf" curves. These results may deviate from that produced by the analysis of OA-13 since these plots were produced from an actual board layout that included parasitic capacitances not accounted for by the analysis of OA-13. It should be noted that a non-inverting gain of +1V/V requires an Rf =1kΩ and the output voltage used for both plots is 2Vpp. In order to bandlimit the CLC412 at any particular gain setting, a larger value of Rf (than previously recommended in the plots above) is needed. Following the analysis in OA-13, we find the CLC412’s "optimum feedback transimpedance", Z t *, below.  R ∗ Z t = R f + Rin  1 + f   R  g 634   = 634 + 60 1 +   634  = 754Ω 20LOG (754) = 57.5dB surface mount package. Either of these layouts can assist the designer in obtaining the desired performance. In addition, the boards can serve as an example layout for the final production printed circuit board. Care must also be taken with the CLC412's layout in order to achieve the best circuit performance, particularly channel-to-channel isolation. The decoupling capacitors (both tantalum and ceramic) must be chosen with good high frequency characteristics to decouple the power supplies and the physical placement of the CLC412’s external components is critical. Grouping each amplifier’s external components with their own ground connection and separating them from the external components of the opposing channel with the maximum possible distance is recommended. The input (Rin) and gain-setting resistors (Rg) are the most critical. It is also recommended that the ceramic decoupling capacitor (0.1µF chip or radial-leaded with low ESR) should be placed as closely to the power pins as possible. Package Parasitics In addition to the parasitic capacitances arising from the board layout, each of the CLC412's packages has its own characteristic set of parasitic capacitances and inductances causing frequency response variation from package to package as shown in the plot below labeled "Frequency Response vs. Package Type". Due to its much smaller size, the CLC412AJE (8-pin SOIC) shows the least amount of peaking. The "optimum feedback transimpedance" is unique for each current-feedback op amp and determines the recommended value of Rf for a particular gain setting. Drawing a horizontal line on the “Open-loop Transimpedance, Z(s)” plot from 57.5dB (on the left vertical axis), we find the intersection with the transimpedance magnitude trace occurs at a frequency of 180MHz. This frequency is only an approximation of the CLC412’s small-signal bandwidth. From this intersection, one can see that an increase in Z t will produce a new intersection occurring at a lower frequency. This is the process to follow when bandlimiting. Once the target small-signal bandwidth is determined, the new value of Zt is picked off the graph at the point where the this frequency and the transimpedance magnitude trace intersect. One can then back track to figure the value of the feedback resistor, Rf=Z t-Rin(1+Rf /Rg). This new value of Rf will produce the desired frequency roll-off. Circuit Layout With all high-frequency devices, board layouts with stray capacitances have a strong influence over AC performance. The CLC412 is no exception and its input and output pins are particularly sensitive to the coupling of parasitic capacitances (to ac ground) arising from traces or pads placed too closely (