CLC417AJE

CLC417 Dual Low-Power, Programmable Gain Buffer September 1998 N CLC417 Dual Low-Power, Programmable Gain Buffer General Description The CLC417 is a dual, low-cost, high-speed (120MHz) buffer which features user-programmable gains of +2, +1, and -1V/V. The CLC417’s high 60mA output current, coupled with its ultra-low 39mW per channel power consumption makes it the ideal choice for demanding applications that are sensitive to both power and cost. Utilizing National’s proven architectures, this dual current feedback amplifier surpasses the performance of alternate solutions with a closed-loop design that produces new standards for buffers in gain accuracy, input impedance, and input bias currents. The CLC417’s internal feedback network provides an excellent gain accuracy of 0.1%. High source impedance applications will benefit from the CLC417’s 6MΩ input impedance along with its exceptionally low 100nA input bias current. With exceptional gain flatness and low differential gain and phase errors, the CLC417 is very useful for professional video processing and distribution. A 120MHz -3dB bandwidth coupled with a 400V/µs slew rate also make the CLC417 a perfect choice in cost-sensitive applications such as video monitors, fax machines, copiers, and CATV systems. Back-terminated video applications will be enhanced by a gain of +2 configuration which requires no external gain components reducing costs and board space. Features s s s s s s s s s 0.01%, 0.03° DG, Dφ High output current: 60mA High input impedance: 6MΩ Gains of +1, +2 with no external components Low power Very low input bias currents: 100nA Excellent gain accuracy: 0.1% High speed: 120MHz -3dB BW Low-cost Desktop video systems Video distribution Flash A/D driver High-speed line driver High-source impedance applications Professional video processing High resolution monitors Frequency Response (AV = +2V/V) Applications s s s s s s s Typical Application Differential Input/Differential Output Amplifier -5V Vin2 250Ω 250Ω Pinout DIP & SOIC 0.1µF 6.8µF OUT1 CLC417 Vout2 +IN1 Vin1 6.8µF +5V © 1998 National Semiconductor Corporation Printed in the U.S.A. 250Ω 250Ω 250Ω + - -VCC Vout1 Vout1 – Vout2 = (Vin1 – Vin2) x 2 0.1µF + - -IN1 250Ω 250Ω +VCC OUT2 250Ω -IN2 +IN2 http://www.national.com CLC417 Electrical Characteristics (AV = +2, Vcc = + 5V, RL = 100Ω unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC417AJ TYP +25˚C 120 52 50 0 0.05 0.3 0.01 0.03 4.3 22 3 400 700 -80 -80 -66 -57 5 12 3 72 1 30 100 3 1 17 2.5 ±0.1% 250Ω 52 50 3.9 6 1 ±2.2 +4.0,-3.4 +3.5,-2.9 60 0.06 MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C 85 40 15 0.5 0.5 0.6 0.04 0.08 6.5 30 12 300 65 36 0.6 0.65 0.7 0.04 0.11 7.2 38 12 260 60 35 0.8 0.7 0.7 0.04 0.12 7.4 41 12 250 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 1.0Vpp Vout < 5.0Vpp ±0.1dB bandwidth Vout < 1.0Vpp gain flatness Vout < 1.0Vpp peaking DC to 200MHz rolloff 1MHz non-inverting current >1MHz crosstalk, input referred 2Vpp, 10MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift output offset voltage amplifier gain error internal resistors (Rf, Rg) power supply rejection ratio common-mode rejection ratio supply current per channel MHz MHz MHz dB dB deg % deg ns ns % V/µs V/µs dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz dB mV µV/˚C nA nA/˚C µA nA/˚C mV V/V dB dB mA MΩ pF V V V mA Ω 1 -55 -50 6.3 15 3.8 66 5 900 5 13.3 ±1.5% ±20% 47 45 4.5 3 2 ±1.8 +3.9,-3.3 +3.1,-2.8 44 0.2 -50 -47 6.6 16 4.0 66 7 50 1600 8 6 40 17.6 ±1.5% 47 45 4.6 2.4 2 ±1.7 +3.8,-3.2 +2.9,-2.7 38 0.25 -47 -46 6.7 17 4.2 66 8 50 2800 11 8 45 19.6 ±1.5% 45 43 4.9 1 2 ±1.5 +3.7,-2.8 +2.4,-1.7 20 0.4 A A A A,2 A non-inverting inverting DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting common mode input range output voltage range RL= ∞ output voltage range RL= 100Ω output current output resistance, closed loop Recommended gain range +1, +2 V/V Transistor count = 110 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage Iout is short circuit protected to ground common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) ±7V ±Vcc +175°C 65˚C to +150°C +300°C 2000V Notes 1) At temps < 0°C, spec is guaranteed for RL = 500Ω. 2) Source impedance 1kΩ. A) J-level: spec is 100% tested at +25°C. Ordering Information Model CLC417AJP CLC417AJE Temperature Range -40°C to +85°C -40°C to +85°C Description 8-pin PDIP 8-pin SOIC Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) θJC 80°C/W 95°C/W θJA 95°C/W 115°C/W http://www.national.com 2 CLC417 Typical Performance Characteristics (Vcc = ±5V, Av = +2, RL = 100Ω; Frequency Response Normalized Magnitude (1dB/div) Vout = 1Vpp Av = -1 Av = 2 Av = 1 Av = -1 Av = 1 unless specified) Frequency Response vs. RL Av = +2 Vout = 1Vpp Frequency Response vs. CL Phase (deg) RL = 1k Magnitude (1dB/div) Magnitude (1dB/div) Phase (deg) 0 -90 -180 -270 -360 -450 RL = 100 RL = 50 RL = 1k Rs = 80.6Ω CL = 10pf Rs = 30.1Ω CL = 100pf Rs = 7.7Ω CL = 1000pf 0 RL = 50 RL = 100 -90 -180 -270 -360 -450 Av = 2 1 10 100 1 10 100 1 10 100 Frequency (MHz) Frequency Response vs. Vout (Av = +1) Vo = 0.2Vpp Frequency (MHz) Frequency Response vs. Vout (Av = -1) Frequency (MHz) Frequency Response vs. Vout (Av = +2) Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) Vo = 2Vpp Vo = 2Vpp Vo = 2Vpp Vo = 0.2Vpp Vo = 4Vpp Vo = 4Vpp Vo = 0.2Vpp Vo = 4Vpp 1 10 100 1 10 100 1 10 100 Frequency (MHz) Maximum Output Voltage vs. RL 4 100 Frequency (MHz) Recommended Rs vs. Capacitive Load 100 Frequency (MHz) Equivalent Input Noise 100 Maximum Output Voltage (V) Noise Voltage (nV/√Hz) Noise Current (pA/√Hz) 2 80 60 40 20 0 0 100 200 300 400 500 600 10 100 1000 Rs (Ω) Inverting Current = 12pA/√Hz 0 10 Voltage = 5nV/√Hz Non-Inverting Current = 3pA/√Hz 10 -2 1 -4 1 100 1k 10k 100k 1M 10M Load (Ω) 2nd & 3rd Harmonic Distoration -40 -55 Vo = 2Vpp 3rd, RL = 100Ω 50Ω Po 50Ω CL (pF) 2nd Harmonic Distortion vs. Pout -40 10MHz 50Ω Frequency (Hz) 3rd Harmonic Distortion vs. Pout Po 50Ω Distortion Level (dBc) -50 -60 -60 Distortion (dBc) -65 -70 -75 -80 -85 -90 Distortion (dBc) 348Ω 348Ω -50 5MHz 348Ω 348Ω 10MHz -60 -70 -80 1MHz 5MHz 2nd, RL = 100Ω -70 2nd, RL = 1kΩ 1MHz -80 -90 1 3rd, RL = 1kΩ 500kHz -90 -100 500kHz 10 -10 -5 0 5 10 -10 -5 0 5 10 Frequency (MHz) Small Signal Pulse Response 0.08 0.06 Av = +1 Output Power (dBm) Large Signal Pulse Response 2 Av = +2 Output Power (dBm) Differential Gain & Phase 0.08 0.07 0.40 0.35 0.30 Output Voltage (V) Output Voltage (V) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 Av = -1 1 0.06 Phase (deg) 0 Gain (%) 0.05 0.04 0.03 0.02 0.01 Phase Negative Sync 0.25 0.20 Gain Negative Sync -1 Phase Positive Sync 0.15 0.01 0.05 0 Gain Positive Sync -2 0 Time (5ns/div) Time (5ns/div) 1 2 3 4 Number of 150Ω Loads 3 http://www.national.com CLC417 Typical Performance Characteristics (Vcc = ±5V, Av = +2, RL = 100Ω; PSRR and CMRR 60 PSRR unless specified) Typical DC Errors vs. Temperature 6 1 5 4 -1 3 2 VIO IBI Power Derating Curves 1.0 0.8 Offset Voltage (mV) PSRR/CMRR (dB) 50 40 30 20 10 10k CMRR IBN Bias Current (µA) 0 Power (W) 0.6 0.4 AJP -2 -3 AJE 0.2 0 -50 0 50 100 0 20 40 60 80 100 120 140 160 180 1 100k 1M 10M 100M Frequency (Hz) Temperature (°C) Ambient Temperature (°C) CLC417 OPERATION Description The CLC417 is a dual current feedback buffer with the following features: Gains of +1, -1, and 2 are achievable without external resistors s Differential gain and phase errors of 0.01% and 0.03° into a 150Ω load s Low, 3.9mA, supply current per amplifier s The convenient 8-pin package and internal resistors make common applications, like that seen on the front page, easily feasible in a limited amount of space. The professional video quality differential gain and phase errors and low power capabilities of the CLC417 make this product a good choice for video applications. If gains other than +1, -1, or +2V/V are required, then the CLC416 can be used. The CLC416 is a dual current feedback amplifier with near identical performance, and allows for external feedback and gain resistors. Closed Loop Gain Selection Gains of +1, +2, and -1V/V can be achieved by both of the CLC417’s amplifiers. Implement the gain selection by connecting the inverting (-IN) and non-inverting (+IN) pins as described in the table below. Gain Av -1V/V +1V/V +2V/V Input Connections +IN -IN ground input signal input signal input signal NC (open) ground Non-Inverting Unity Gain Considerations Gains of +1V/V are obtained by removing all resistive and capacitive connections between the inverting pins and ground on the CLC417 amplifiers. Too much capacitive coupling between the inverting pin and ground may cause stability problems. Minimize this capacitive coupling by removing the ground plane near the input and output pins. The response labeled open in Figure 1 is the result of the inverting pin left open and all capacitive coupling removed. A flatter response can be obtained by inserting a resistor between the inverting and non-inverting pins as shown in Figure 2. The two remaining plots in Figure 1 illustrate a 300Ω resistor and a short connected between pins 2 and 3 of the CLC417. Magnitude (1dB/div) Open R = 300Ω Short 1 10 100 Frequency (MHz) Figure 1: Frequency Response vs. Unity Gain Configuration SMA Output1 Rout 50Ω R + Rin 50Ω NOTE: The same technique can also be applied to Channel B. Bypass capacitors not shown. Figure 2: Optional Unity Gain Configuration 4 http://www.national.com + The gain accuracy of the CLC417 is excellent and stable over temperature. The internal feedback and gain setting resistors, Rf and Rg, are diffused silicon resistors. Rf and Rg have a process variation of ±20% and a temperature coefficient of ~ 2000ppm/°C. Although the absolute values of Rf and Rg change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will be impacted by temperature coefficient differences between internal and external resistors. 250Ω 250Ω SMA Input1 250Ω 250Ω Channel Matching Channel matching and crosstalk efficiency are largely dependent on board layout. The layout of National’s dual amplifier evaluation boards are optimized to produce maximum channel matching and isolation. Typical channel matching for the CLC417 is shown in Figure 3. Av = +2 RL = 100Ω Vo = 2Vpp Channel A Channel B 1. Determine the quiescent power PQ = (VCC - VEE) • ICC 2. Determine the RMS power at the output stage PO = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Determine the total RMS power PT = PQ + PO Add the total RMS powers for both channels to determine the power dissipated by the dual. The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utilizing the following equation: P= (175° − Tamb) θ JA Magnitude (0.5dB/div) Channel B Phase (deg) 0 -90 Channel A -180 -270 -360 -450 1 10 100 Frequency (MHz) Figure 3: Channel Matching The CLC417’s channel-to-channel isolation is better than 70dB for input frequencies of 4MHz. Input referred crosstalk vs. frequency is illustrated in Figure 4. -20 -40 where: Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC417 (CLC730038 - DIP, CLC730036 - SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. Supply bypassing is required for best performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. Other layout factors play a major role in high frequency performance. The following are recommended as a basis for high frequency layout: 1. Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. 2. Place the 6.8µF capacitors within 0.75 inches of the power pins. 3. Place the 0.1µF capacitors less than 0.1 inches from the power pins. 4. Remove the ground plane near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. Special Evaluation Board Considerations To optimize off-isolation of the CLC417, cut the Rf trace on both the 730038 and 730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and output. Figure 5 indicates the alterations recommended to improve off-isolation. 5 http://www.national.com Crosstalk (dB) -60 -80 -100 -120 1 10 100 Frequency (MHz) Figure 4: Input Referred Crosstalk vs. Frequency Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC417 will improve stability. The Rs vs. Capacitive Load plot, in the Typical Performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: Quiescent Power Dissipation PQ (No Load Condition) s Total Power Dissipation PT (with Load Condition) s The following steps can be taken to determine the power consumption for each CLC417 amplifier: 730036 Top Applications Circuits +Vcc OUT2 ROUT2 RF2 C3 + C4 + -Vcc C1 C2 ROUT1 GND RG2 IN2 Video Cable Driver The CLC417 was designed to produce exceptional video performance at all three closed-loop gains. A typical cable driving configuration is shown in Figure 6. In this example, the amplifier is configured with a gain of 2. +5V OUT1 RIN2 RG1 RIN1 - 0.1µF NOTE: The same technique can also be applied to Channel A. 250Ω 250Ω 6.8µF Video Output 50Ω Rout J1 50Ω Coax 50Ω SMA Input 6.8µF 0.1µF Cut traces here 730038 Bottom Figure 6: Typical Cable Driver Single to Differential Line Driver The topology in Figure 7 accomplishes a single-ended to differential conversion with no external components. With this configuration, the value of Vin is limited to the common mode input range of the CLC417. +5V 250Ω -5V 6.8µF 0.1µF AV1 = 1V/V AV2 = -1V/V Cut traces here Figure 5: Optional Evaluation Board Alterations SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations s Vout1 = Vin Vout2 = -Vin Figure 7: Single to Differential Line Driver The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. http://www.national.com 6 + - 730038 REV B Vout1 250Ω 250Ω + - + IN1 -5V - Comlinear (970) 226-0500 250Ω + RF1 250Ω 0Ω Rin 50Ω 0.1µF Vout2 6.8µF 250Ω Vin This page intentionally left blank. 7 http://www.national.com CLC417 Dual Low-Power, Programmable Gain Buffer Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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