CLC428AJE

CLC428 Dual Wideband, Low-Noise, Voltage Feedback Op Amp June 1999 N CLC428 Dual Wideband, Low-Noise, Voltage Feedback Op Amp General Description The CLC428 is a very high-speed dual op amp that offers a traditional voltage-feedback topology featuring unity-gain stability and slewenhanced circuitry. The CLC428’s ultra low noise and very low harmonic distortion combine to form a very wide dynamic-range op amp that operates from a single (5 to 12V) or dual (±5V) power supply. Each of the CLC428’s closely matched channels provides a 160MHz unity-gain bandwidth with an ultra low input voltage noise density (2nV/√Hz). Very low 2nd/3rd harmonic distortion (-62/-72dBc) as well as high channel-to-channel isolation (-62dB) make the CLC428 a perfect wide dynamic-range amplifier for matched I/Q channels. With its fast and accurate settling (16ns to 0.1%), the CLC428 is also a excellent choice for wide-dynamic range, anti-aliasing filters to buffer the inputs of hi-resolution analog-to-digital converters. Combining the CLC428’s two tightly-matched amplifiers in a single eight-pin SOIC reduces cost and board space for many composite amplifier applications such as active filters, differential line drivers/ receivers, fast peak detectors and instrumentation amplifiers. To reduce design times and assist in board layout, the CLC428 is supported by an evaluation board and a SPICE simulation model available from National Semiconductor. Features s s s s s s Wide unity-gain bandwidth: 160MHz Ultra-low noise: 2.0nV/√Hz Low distortion: -78dBc 2nd (2MHz) -62/-72dBc (10MHz) Settling time: 16ns to 0.1% Supply voltage range: ±2.5 to ±5 or single supply High output current: ±80mA Applications s s s s s s s General purpose dual op amp Low noise integrators Low noise active filters Diff-in/diff-out instrumentation amp Driver/receiver for transmission systems High-speed detectors I/Q channel amplifiers Typical Application 5-Decade Integrator Pinout DIP & SOIC Vout1 Vinv1 Vnon-inv1 -Vcc 1 2 3 4 + + 8 7 6 5 +Vcc Vout2 Vinv2 Vnon-inv2 © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC428 Electrical Characteristics (V PARAMETERS Ambient Temperature CONDITIONS CLC428 CC = ±5V; AV = +2V/V; Rf =100Ω; Rg =100Ω; RL = 100Ω; unless noted; +25°C MIN/MAX RATINGS 0 to +70°C -40 to +85°C UNITS NOTES TYP +25°C FREQUENCY DOMAIN RESPONSE gain bandwidth product Vout < 0.5Vpp -3dB bandwidth, Av=+1 Vout < 0.5Vpp Av=+2 Vout < 0.5Vpp Vout < 5.0Vpp gain flatness Vout < 0.5Vpp peaking DC to 200MHz rolloff DC to 20MHz linear phase deviation DC to 20MHz TIME DOMAIN RESPONSE rise and fall time 1V step settling time 2V step to 0.1% overshoot 1V step slew rate 5V step DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 1Vpp,10MHz 1Vpp,10MHz 3rd harmonic distortion equivalent input noise voltage 1MHz to 100MHz current 1MHz to 100MHz crosstalk input referred, 10MHz STATIC DC PERFORMANCE open-loop gain input offset voltage average drift input bias current average drift input offset current average drift power supply rejection ratio common-mode rejection ratio supply current 135 160 80 40 0.0 0.05 0.2 5.5 16 1 500 - 62 - 72 2.0 2.0 - 62 60 1.0 5 1.5 150 0.3 5 66 63 11 500 200 2.0 2.0 0.05 ± 3.8 ± 3.5 ± 3.7 ± 70 100 120 50 25 0.6 0.5 1.0 7.5 20 5 300 - 50 - 60 2.5 3.0 - 58 56 2.0 --25 --3 --60 57 12 250 50 3.0 3.0 0.1 ± 3.5 ± 3.2 ± 3.5 ± 50 80 90 40 22 0.8 0.7 1.5 9.0 24 10 275 - 45 - 56 2.8 3.6 - 58 50 3.0 15 40 600 5 25 55 52 13 125 25 3.0 3.0 0.2 ± 3.3 ± 2.6 ± 3.3 ± 40 70 80 35 20 1.0 0.7 1.5 10.0 24 10 250 - 43 - 56 2.8 4.6 - 58 50 3.5 20 65 700 5 50 55 52 15 125 25 3.0 3.0 0.2 ± 3.3 ± 1.3 ± 3.3 ± 20 MHz MHz MHz MHz dB dB ° ns ns % V/µs dBc dBc nV/√Hz pA/√Hz dB dB mV µV/°C µA nA/°C µA nA/°C dB dB mA kΩ kΩ pF pF Ω V V V mA A A per channel, RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance common-mode differential-mode input capacitance common-mode differential-mode output resistance closed loop output voltage range RL= ∞ RL=100 Ω input voltage range common mode output current Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage differential input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) ±7V (note 1) ±Vcc ±10V +150°C -65°C to+150°C +300°C Ordering Information Model Temperature Range -40°C to +85°C -40°C to +85°C -55°C to +125°C 5962-94708 Description 8-pin PDIP 8-pin SOIC 8-pin CerDIP, MIL-STD-883 CLC428AJP CLC428AJE CLC428A8B DESC SMD number: Notes A) J-level: spec is 100% tested at +25°C, sample tested at +85°C. 1) Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA. Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) CerDIP θjc 60°C/W 40°C/W 25°C/W θjA 115°C/W 115°C/W 115°C/W Reliability Information Transistor count 104 http://www.national.com 2 3 http://www.national.com Application Discussion Low Noise Design Ultimate low noise performance from circuit designs using the CLC428 requires the proper selection of external resistors. By selecting appropriate low-valued resistors for Rf and Rg, amplifier circuits using the CLC428 can achieve output noise that is approximately the equivalent voltage input noise of 2.0 nV/√Hz multiplied by the desired gain (Av). Each amplifier in the CLC428 has an equivalent input noise resistance which is optimum for matching source impedances of approximately 1k. Using a transformer, any source can be matched to achieve the lowest noise design. For even lower noise performance than the CLC428, consider the CLC425 or CLC426 at 1.05 and 1.6 nV/√Hz, respectively. DC Bias Currents and Offset Voltages Cancellation of the output offset voltage due to input bias currents is possible with the CLC428. This is done by making the resistance seen from the inverting and noninverting inputs equal. Once done, the residual output offset voltage will be the input offset voltage (Vos) multiplied by the desired gain (Av). Comlinear Application Note OA-7 offers several solutions to further reduce the output offset. Output and Supply Considerations With ±5V supplies, the CLC428 is capable of a typical output swing of ±3.8V under a no-load condition. Additional output swing is possible with slightly higher supply voltages. For loads of less than 50Ω, the output swing will be limited by the CLC428’s output current capability, typically 80mA. Output settling time when driving capacitive loads can be improved by the use of a series output resistor. See the plot labeled "Settling Time vs. Capacitive Load" in the Typical Performance section. Layout Proper power supply bypassing is critical to insure good high frequency performance and low noise. De-coupling capacitors of 0.1µF should be place as close as possible to the power supply pins. The use of surface mounted capacitors is recommended due to their low series inductance. A good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitance from these nodes to ground causes frequency response peaking and possible circuit oscillation. See OA-15 for more information. National suggests the CLC730038 (through-hole) or the CLC730036 (SOIC) dual op amp evaluation board as a guide for high frequency layout and as an aid in device evaluation. http://www.national.com 4 Analog Delay Circuit (All-Pass Network) The circuit in Figure 1 implements an all-pass network using the CLC428. A wide bandwidth buffer (CLC111) drives the circuit and provides a high input impedence for the source. As shown in Figure 2, the circuit provides a Figure 3 A1 (B1) and pass the signals from driver B1 (A1). The output of the receiver amplifier will be: Figure 1 Vout AB ej = 1 2 Vin AB F RI 1 GJ a f G1− R J + 2 V HK f g inB F RI GJ a f G1+ R J HK f A Eq. 3 g Care must be given to layout and component placement to maintain a high frequency common-mode rejection. The plot of Figure 4 shows the simultaneous reception of signals transmitted at 1MHz and 10MHz. Figure 2 13.1ns delay (with R =40.2Ω, C=47pF). Rf and Rg should be of equal and low value for parasitic insensitive operation. The circuit gain is +1 and the delay is determined by the following equations. τ delay = 2 2RC + Td Td = 1 dφ 360 df ; c h Eq. 1 Eq. 2 Figure 4 Five Decade Integrator A composite integrator, as shown in Figure 5, uses the CLC428 dual op amp to increase the circuits' usable frequency range of operation. The transfer function of this circuit is: 1 Vo = Vin dt Eq. 4 RC where Td is the delay of the op amp at AV=+1. The CLC428 provides a typical delay of 2.8ns at its -3dB point. Full Duplex Digital or Analog Transmission Simultaneous transmission and reception of analog or digital signals over a single coaxial cable or twisted-pair line can reduce cabling requirements. The CLC428's wide bandwidth and high common-mode rejection in a differential amplifier configuration allows full duplex transmission of video, telephone, control and audio signals. In the circuit shown in Figure 3, one of the CLC428's amps is used as a "driver" and the other as a difference "receiver" amplifier. The output impedance of the "driver" is essentially zero. The two R's are chosen to match the characteristic impedance of the transmission line. The "driver" op amp gain can be selected for unity or greater. Receiver amplifier A2 (B2) is connected across R and forms differential amplifier for the signals transmitted by driver A1 (B1). If the coax cable is lossless and Rf equals Rg, receiver A2 (B2) will then reject the signals from driver 5 z Figure 5 A resistive divider made from the 143Ω and 60.4Ω resistors was chosen to reduce the loop-gain and stabilize the network. The CLC428 composite integrator provides integration over five decades of operation. R and C set the integrator's gain. Figure 6 shows the frequency and phase response of the circuit in Figure 5 with R = 44.2Ω and C = 360pF. http://www.national.com The maximum speed of detection is limited by the delay of the op amps and the diodes. The use of Schottky diodes will provide faster response. Adjustable or Bandpass Equalizer A "boost" equalizer can be made with the CLC428 by summing a bandpass response with the input signal, as shown in Figure 9. Figure 6 Positive Peak Detector The CLC428's dual amplifiers can be used to implement a unity-gain peak detector circuit as shown in Figure 7. Figure 9 The overall transfer function is shown in Eq. 5. Rb Vout = Vin K Ra + Rb Q1 F GH c I h JK s 2 s2Qω o −1 ω + s o + ω o2 Q Eq. 5 To build a boost circuit, use the design equations Eq. 6 and Eq. 7. R 2C Q 1 = , 2C Ra ||Rb = 2 Qω o ωo c h Eq. 6,7 Figure 7 The acquisition speed of this circuit is limited by the dynamic resistance of the diode when charging Chold. A plot of the of the circuit's performance is shown in Figure 8 with a 1MHz sinusoidal input. Select R2 and C using Eq. 6. Use reasonable values for high frequency circuits - R2 between 10Ω and 5kΩ, C between 10pF and 2000pF. Use Eq. 7 to determine the parallel combination of Ra and Rb. Select Ra and Rb by either the 10Ω to 5kΩ criteria or by other requirements based on the impedance Vin is capable of driving. Finish the design by determining the value of K from Eq. 8. Peak Gain = Vout Vin R cω h = 2KR 2 o −1 a Eq. 8 Figure 10 shows an example of the response of the circuit of Figure 9, where fo is 2.3MHz. The component values are as follows: Ra =2.1kΩ, Rb =68.5Ω, R2 =4.22kΩ, R =500Ω, KR =50Ω, C =120pF. Figure 8 A current source, built around Q1, provides the necessary bias current for the second amplifier and prevents saturation when power is applied. The resistor, R, closes the loop while diode D2 prevents negative saturation when Vin is less than Vc. A MOS-type switch (not shown) can be used to reset the capacitor's voltage. Figure 10 http://www.national.com 6 This page intentionally left blank. 7 http://www.national.com CLC428 Dual Wideband, Low-Noise, Voltage Feedback Op Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 National Semiconductor Europe Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 8