CLC453AJM5

Comlinear CLC453 Single Supply, Low-Power, High Output, Programmable Buffer December 1996 N Comlinear CLC453 Single Supply, Low-Power, High Output, Programmable Buffer General Description The Comlinear CLC453 is a low cost, high speed (110MHz) buffer that features user-programmable gains of +2, +1, and -1V/V. It has a new output stage that delivers high output drive current (100mA), but consumes minimal quiescent supply current (3.0mA) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a programmable range of gains and wide signal levels, and has a linear-phase response up to one half of the -3dB frequency. The CLC453’s internal feedback network provides an excellent gain accuracy of 0.3% The CLC453 offers superior dynamic performance with a 110MHz small-signal bandwidth, 370V/µs slew rate and 4.8ns rise/fall times (2V step). The combination of the small SOT23-5 package, low quiescent power, high output current drive, and high-speed performance make the CLC453 well suited for many batterypowered personal communication/computing systems. The ability to drive low-impedance, highly capacitive loads, makes the CLC453 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC453 will drive a 100Ω load with only -72/-74dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -65/-77dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high-resolution A/D converters, the CLC453 provides excellent -65/-84dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. +5V 6.8µF +5V 1 5kΩ Vin 0.1µF 0.1µF 2 3 5kΩ 4 1kΩ 1kΩ Features s s s s s s s s s 100mA output current 3.0mA supply current 110MHz bandwidth (Av = +2) -65/-84dBc HD2/HD3 (1MHz) 25ns settling to 0.05% 370V/µs slew rate Stable for capacitive loads up to 1000pF Single 5V to ±5V supplies Available in Tiny SOT23-5 package Coaxial cable driver Twisted pair driver Transformer/Coil Driver High capacitive load driver Video line driver Portable/battery-powered applications A/D driver Maximum Output Voltage vs. RL 10 9 Applications s s s s s s s Output Voltage (Vpp) 8 7 6 5 4 3 2 1 10 100 1000 Vs = +5V VCC = ±5V RL (Ω) Response After 10m of Cable Vin = 10MHz, 0.5Vpp 450 Performance Plot Typical Application Single Supply Cable Driver 100mV/div + 8 7 6 0.1µF 75Ω 0.1µF 10m of 75Ω Coaxial Cable Vo 75Ω 20ns/div CLC453 5 Vo VCC 453 Typ. App. Diagram 1kΩ Pinout SOT23-5 VEE Vnon-inv © 1996 National Semiconductor Corporation Printed in the U.S.A. Pinout DIP & SOIC 1kΩ 1kΩ 450 Typ. App. Plot + 1kΩ Vinv VEE http://www.national.com 451 Pinout (SOT) 451 Pinout +5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, R L = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to V cm, unless specified) CONDITIONS CLC453AJ TYP +25°C 110 90 25 0 0.2 0.1 4.8 25 9 370 -72 -65 -65 -74 -84 -60 2.8 7.5 10.5 13 80 5 30 ±0.3 1000 48 51 3.0 0.39 1.5 4.2 0.8 4.0 1.0 4.1 0.9 100 400 MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C 85 75 22 0.5 0.4 2 6.4 – 13 280 -66 -59 -56 -70 -76 -55 3.5 10 14 30 – 18 – ±1.5 ±20% 45 48 3.4 0.28 2.3 4.1 0.9 3.9 1.1 4.0 1.0 80 600 75 72 22 0.9 0.6 3 6.8 – 16 250 -64 -57 -54 -68 -74 -53 3.8 11 15 35 – 22 – ±2.0 ±26% 43 46 3.6 0.25 2.3 4.0 1.0 3.8 1.2 4.0 1.0 65 600 70 70 18 1.0 0.6 3 7.3 – 16 240 -64 -57 -54 -68 -74 -53 3.8 11 15 35 – 24 – ±2.0 ±30% 43 46 3.6 0.25 2.3 4.0 1.0 3.8 1.2 3.9 1.1 40 600 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 0.5Vpp Vo = 2.0Vpp -0.1dB bandwidth Vo = 0.5Vpp gain peaking 1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift gain accuracy internal resistors (Rf, Rg) power supply rejection ratio common-mode rejection ratio supply current B B A A A B A DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC C Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) J-level: spec is 100% tested at +25°C, sample tested at +85°C. B) J-level: spec is sample tested at +25°C. C) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE Absolute Maximum Ratings supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) +14V 140mA VEE to VCC +175°C -65°C to +150°C +300°C 500V Reliability Information Transistor Count MTBF (based on limited test data) 49 31Mhr http://www.national.com 2 ±5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, R L = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC453AJ TYP +25°C 130 70 30 0 0.2 0.1 0.3 0.1 3.8 20 6 460 -82 -69 -65 -73 -90 -60 2.8 7.5 10.5 7 80 3 40 ±0.3 1000 50 53 3.2 0.52 1.2 ±4.2 ±3.8 ±4.0 130 400 GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C 105 55 25 0.5 0.7 0.2 – – 4.8 – 10 340 -74 -63 -59 -69 -80 -56 3.5 10 14 30 – 18 – ±1.5 ±20% 47 50 3.8 0.35 1.8 ±4.1 ±3.6 ±3.8 100 600 95 52 25 0.9 0.8 0.3 – – 5.1 – 13 315 -72 -61 -57 -67 -78 -54 3.8 11 15 35 – 23 – ±2.0 ±26% 45 48 4.0 0.30 1.8 ±4.1 ±3.6 ±3.8 80 600 90 50 20 1.0 0.8 0.3 – – 5.6 – 13 300 -72 -61 -57 -67 -78 -54 3.8 11 15 35 – 25 – ±2.0 ±30% 45 48 4.0 0.30 1.8 ±4.0 ±3.5 ±3.7 50 600 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.0Vpp Vo = 4.0Vpp -0.1dB bandwidth Vo = 1.0Vpp gain peaking 1MHz STATIC DC PERFORMANCE output offset voltage average drift input bias current (non-inverting) average drift gain accuracy internal resistors (Rf, Rg) power supply rejection ratio common-mode rejection ratio supply current DC DC RL= ∞ B MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC C Notes B) J-level: spec is sample tested at +25°C. C) The short circuit current can exceed the maximum safe output current. Model CLC453AJP CLC453AJE CLC453AJM5 CLC453ALC Ordering Information Temperature Range -40°C to +85 °C -40°C to +85 °C -40°C to +85 °C -40°C to +85 °C Description 8-pin PDIP 8-pin SOIC 5-pin SOT dice Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) Surface Mount (AJM5) Dice (ALC) qJC 115°C/W 130°C/W 140°C/W 25°C/W qJA 125°C/W 150°C/W 210°C/W – 3 http://www.national.com +5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 0.5Vpp Av = 1 Av = -1 Av = 2 v = +2, R L = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to V cm, unless specified) Frequency Response vs. RL Vo = 0.5Vpp RL = 1kΩ RL = 100Ω Frequency Response vs. Vo (Av = 2) Phase (deg) Magnitude (1dB/div) Gain Gain RL = 25Ω Magnitude (1dB/div) Phase (deg) Vo = 1Vpp Phase Av = 1 0 -90 Av = 2 Phase 0 RL = 1kΩ RL = 100Ω RL = 25Ω -90 -180 -270 -360 -450 Vo = 0.1Vpp Vo = 2Vpp Vo = 2.5Vpp -180 -270 -360 -450 Av = -1 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo (Av = +453 Plot1 1) Vo = 0.1Vpp Vo = 1Vpp Frequency (Hz) Frequency Response vs. Vo (Av = -1) 453 Plot2 Frequency (Hz) Frequency Response vs. CL Vo = 0.5Vpp 453 Plot3 Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) Vo = 2.5Vpp Vo = 2Vpp Vo = 1Vpp CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 21Ω CL = 1000pF Rs = 7.0Ω + - Vo = 2.5Vpp Vo = 2Vpp Rs 1k CL 1k Vo = 0.1Vpp 1k 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Gain Flatness Vo = 0.5Vpp Frequency (Hz) Frequency (Hz) 453 Plot4 Noise Voltage (nV/√Hz) Equivalent Input Noise 3.2 453 Plot5 12.5 2nd & 3rd Harmonic Distortion -40 Vo = 2Vpp 453 Plot6 Magnitude (0.05dB/div) Inverting Current 10.5pA/√Hz Noise Current (pA/√Hz) Distortion (dBc) 3.1 Non-Inverting Current 7.5pA/√Hz 10 -50 -60 -70 -80 -90 1M 2nd RL = 100Ω 3rd RL = 100Ω 2nd RL = 1kΩ 3 7.5 2.9 Voltage 2.85nV/√Hz 5 3rd RL = 1kΩ 2.8 0 10 20 30 1k 100k 1M 10M 2.5 10M Frequency (MHz) 2nd Harmonic Distortion, RL = 25Ω 453 Plot7 -44 -46 10MHz Frequency (Hz) 3rd Harmonic Distortion, RL = 25Ω 453 Plot8 -35 -40 10MHz Frequency (Hz) 2nd Harmonic Distortion, RL = 100Ω 453 Plot9 -60 10MHz Distortion (dBc) Distortion (dBc) Distortion (dBc) -48 -50 -52 -54 2MHz 5MHz -45 -50 -55 -60 1MHz 5MHz -65 5MHz 2MHz -70 2MHz -56 -58 -60 0 0.5 1 1.5 2 2.5 1MHz -65 -70 -75 0 0.5 1 1.5 2 2.5 -75 1MHz -80 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) -45 -50 Output Amplitude (Vpp) 2nd Harmonic Distortion, RL = 1kΩ 453 Plot11 -60 -60 -65 -65 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 1kΩ453 Plot12 3rd Harmonic Distortion, RL = 100Ω 453 Plot10 10MHz Distortion (dBc) Distortion (dBc) Distortion (dBc) -55 5MHz -70 10MHz -60 -65 -70 -75 -80 0 0.5 1 1.5 2 2.5 2MHz 1MHz -70 10MHz -75 -80 -85 2MHz 5MHz -75 -80 -85 0 5MHz 2MHz -90 1MHz -95 1 1.5 2 2.5 0 0.5 1 1MHz 0.5 1.5 2 2.5 Output Amplitude (Vpp) Output Amplitude (Vpp) Output Amplitude (Vpp) http://www.national.com 453 Plot13 4 453 Plot14 453 Plot15 +5V Typical Performance (A Closed Loop Output Resistance 100 v = +2, R L = 100Ω, Vs = + 5V 1, Vcm = VEE + (Vs/2), RL tied to V cm, unless specified) Recommended Rs vs. CL 50 + Large & Small Signal Pulse Response Output Voltage (0.5V/div) Rs Output Resistance (Ω) 40 10 30 20 10 0 10k 100k 1M 10M 100M 10 100 - 1k 1k CL 1k Large Signal Rs (Ω) Small Signal 1 0.1 0.01 1000 Time (10ns/div) Frequency (Hz) PSRR & CMRR 60 50 40 30 20 10 0 1k 10k 100k 1M 10M 100M PSRR CMRR CL (pF) 453 Plot16 -0.6 IBN, Vos vs. Temperature 453 Plot17 6 5 4 3 2 1 5 4.5 Maximum Output Voltage vs. RL 453 Plot18 Offset Voltage Vos (mV) PSRR & CMRR (dB) IBN Vos Output Voltage (Vpp) -0.7 -0.8 -0.9 -1 -1.1 -100 -50 4 3.5 3 2.5 2 1.5 1 10 100 1000 IBN (µA) 0 50 100 150 Frequency (Hz) Temperature (°C) RL (Ω) 453 Plot19 453 Plot20 453 Plot21 ±5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 1Vpp Gain Av = +1 Phase v = +2, R L = 100Ω, VCC = ± 5V, unless specified) Frequency Response vs. RL Vo = 1Vpp RL = 1kΩ RL = 100Ω Frequency Response vs. Vo (Av = 2) Phase (deg) Magnitude (1dB/div) Gain 0 Av = -1 Phase 0 -90 RL = 25Ω Magnitude (1dB/div) -45 -90 -135 -180 -225 100M Phase (deg) Vo = 5Vpp -180 -270 -360 -450 Vo = 1Vpp Vo = 0.1Vpp Vo = 2Vpp Av = 2 1M 10M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo (Av = +1) Plot22 453 Vo = 0.1Vpp Vo = 1Vpp Frequency (Hz) Frequency Response vs. Vo (Av = -453 Plot23 1) Frequency (Hz) Frequency Response vs. CL Vo = 1Vpp 453 Plot24 Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 21Ω CL = 1000pF Rs = 6.7Ω + - Vo = 2Vpp Vo = 5Vpp Vo = 5Vpp Vo = 2Vpp Vo = 1Vpp Rs 1k CL 1k Vo = 0.1Vpp 1k 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency (Hz) Frequency (Hz) 453 Plot25 453 Plot26 453 Plot27 5 http://www.national.com ±5V Typical Performance (A Gain Flatness Vo = 1Vpp v = +2, R L = 100Ω, VCC = ± 5V, unless specified) Large & Small Signal Pulse Response -40 Vo = 2Vpp 2nd & 3rd Harmonic Distortion Output Voltage (0.5V/div) Magnitude (0.05dB/div) Large Signal -50 Distortion (dBc) Small Signal -60 -70 -80 -90 2nd RL = 100Ω 3rd RL = 100Ω 2nd RL = 1kΩ 3rd RL = 1kΩ 0 5 10 15 20 25 30 Time (10ns/div) 3rd Harmonic Distortion, RL = 25Ω453 Plot29 -30 -40 -55 1M 10M Frequency (MHz) 2nd Harmonic Distortion, RL = 25Ω 453 Plot28 -40 -45 Frequency (Hz) 2nd Harmonic Distortion, RL = 100453 Plot30 Ω 10MHz 10MHz -60 Distortion (dBc) Distortion (dBc) -50 5MHz Distortion (dBc) 10MHz 5MHz -50 -55 -60 -65 0 1 2 3 4 5MHz -65 -70 2MHz -60 -70 -80 -90 1MHz 2MHz 2MHz 1MHz 1MHz -75 -80 5 0 1 2 3 4 5 0 1 2 3 4 5 Output Amplitude (Vpp) -50 -55 Output Amplitude (Vpp) -60 -65 Output Amplitude (Vpp) -60 -65 3rd Harmonic Distortion, RL = 100Ω 453 Plot31 2nd Harmonic Distortion, RL = 1kΩ 453 Plot32 3rd Harmonic Distortion, RL = 1kΩ453 Plot33 10MHz Distortion (dBc) Distortion (dBc) Distortion (dBc) 10MHz -60 5MHz -70 -75 2MHz 5MHz -70 5MHz -65 -70 -75 -80 0 1 2 3 4 5 2MHz 1MHz 2MHz -75 10MHz -80 -85 -90 1MHz -80 -85 0 1MHz -95 1 2 3 4 5 0 1 2 3 4 5 Output Amplitude (Vpp) Recommended Rs vs. CL 50 + Output Amplitude (Vpp) Output Amplitude (Vpp) Differential Gain & Phase 0 f = 3.58MHz Gain Positive Sync Gain Negative Sync 453 Plot34 10 Rs Maximum Output Voltage vs. RL 453 Plot35 9 -0.1 -0.2 453 Plot36 -0.1 -0.15 -0.2 -0.25 -0.3 1k 1k Output Voltage (Vpp) 40 30 20 10 0 10 100 - CL 1k 8 Phase (deg) Gain (%) Rs (Ω) 7 6 5 4 3 2 -0.3 -0.4 Phase Positive Sync -0.5 -0.6 Phase Negative Sync -0.35 -0.4 -0.45 1 2 3 4 -0.7 10 100 1000 1000 CL (pF) IBN, Vos vs. Temperature 1.5 RL (Ω) Number of 150Ω Loads 453 Plot37 12 0.2 Short Term Settling Time 453 Plot38 0.2 Vo = 2Vstep Long Term Settling Time Vo = 2Vstep 453 Plot39 Offset Voltage Vos (mV) 0.15 Vo (% Output Step) Vo (% Output Step) 1 8 0.1 0.1 0.05 0 -0.05 -0.1 -0.15 IBN (µA) 0.5 IBN Vos 4 0 0 0 -0.1 -0.5 -100 -50 0 50 100 150 -4 -0.2 1 10 100 1000 -0.2 1µ 10µ 100µ 1m 10m 100m 1 Temperature (°C) Time (ns) Time (s) http://www.national.com 453 Plot40 6 453 Plot41 453 Plot42 CLC453 Operation The CLC453 is a current feedback buffer built in an advanced complementary bipolar process. The CLC453 operates from a single 5V supply or dual ±5V supplies. Operating from a single 5V supply, the CLC453 has the following features: s s s s Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. Vo = Vin where: s s s Gains of +1, -1, and 2V/V are achievable without external resistors Provides 100mA of output current while consuming only 15mW of power Offers low -65/-84dBc 2nd and 3rd harmonic distortion Provides BW > 80MHz and 1MHz distortion < -70dBc at Vo = 2Vpp Av Rf 1+ Z(jω ) Equation 1 Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC453’s open loop transimpedance gain Z( jω ) is the loop gain Rf The CLC453 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. If gains other than +1, -1, or +2V/V are required, then the CLC452 can be used. The CLC452 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Current Feedback Amplifiers Some of the key features of current feedback technology are: s s s s s s The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: s s s s s Independence of AC bandwidth and voltage gain Inherently stable at unity gain Adjustable frequency response with feedback resistor High slew rate Fast settling Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity CLC453 Design Information Closed Loop Gain Selection The CLC453 is a current feedback op amp with Rf = Rg = 1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and -1V/V by connecting pins 2 and 3 as described in the chart below. Gain Av -1V/V +1V/V +2V/V Input Connections Non-Inverting (pin3) Inverting (pin2) ground input signal input signal input signal NC (open) ground Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC453 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. DC Coupled Single Supply Operation Figures 1, 2, and 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC. The gain accuracy of the CLC453 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of ˜ 2000ppm/°C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. 7 http://www.national.com Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. VCC 6.8µF + 1 Vin Rt Rb Vcm Vcm 2 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + CLC453 5 VCC Vin CC R 1 2 3 1kΩ 1kΩ 8 7 6 Vo 0.1µF Figure 1: DC Coupled, Av = -1V/V Configuration 453 Fig1 Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. R 4 CLC453 5 1 , 2πRinCC R >> R source VCC 6.8µF + Vo = Vin + 2.5 Low frequency cutoff = where Rin = R 2 1 2 Vin Rt Vcm 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm VCC 453 Fig2 Vin CC RC R 6.8µF + Figure 5: AC Coupled, Av = +1V/V Configuration 453 Fig5 VCC 6.8µF + CLC453 5 1 2 3 4 1kΩ 1kΩ 8 7 6 Vo 0.1µF Figure 2: DC Coupled, Av = +1V/V Configuration Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. VCC CLC453 5 1 , 2πRinCC R >> R source 1 Vcm Vin Rt Vcm 2 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm Vo = 2Vin + 2.5 Low frequency cutoff = where Rin = R 2 CLC453 5 453 Fig6 Figure 6: AC Coupled, Av = +2V/V Configuration Figure 3: DC Coupled, Av = +2V/V Configuration 453 Fig3 Dual Supply Operation The CLC453 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 7, 8 and 9. VCC 6.8µF + AC Coupled Single Supply Operation Figures 4, 5, and 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. VCC Vin CC VCC R 3 R 4 6 1 2 1kΩ 1kΩ 1 6.8µF + 8 1kΩ 1kΩ Vin Rt Rb 2 3 4 + 7 6 0.1µF Vo 8 7 Vo 0.1µF CLC453 5 CLC453 6.8µF Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. 5 1 , 2πR gCC Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. 0.1µF VEE 453 Fig7 Figure 4: AC Coupled, Av = -1V/V Configuration 453 Fig4 Figure 7: Dual Supply, Av = -1V/V Configuration 8 http://www.national.com VCC 6.8µF + Figure 10 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications: 1 2 Vin Rt 3 4 + 1kΩ 1kΩ 8 7 6 0.1µF Vo s s s CLC453 5 6.8µF Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: 0.1µF VEE 453 Fig8 Figure 8: Dual Supply, Av = +1V/V Configuration VCC 6.8µF + s s s Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. 1 2 Vin Rt 3 4 + 1kΩ 1kΩ 8 7 6 0.1µF Vo The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. 1 R4 Z0 2 R5 R1 V2 + Z0 R3 R2 3 4 1kΩ 1kΩ 8 7 6 C6 Z0 Vo R7 CLC453 5 6.8µF V1 + - CLC453 R6 5 0.1µF VEE 453 Fig9 Figure 9: Dual Supply, Av = +2V/V Configuration Figure 10: Transmission Line Matching Fig10 453 Power Dissipation Follow these steps to determine the power consumption of the CLC453: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP, SOIC, and SOT packages can dissipate at a given temperature is illustrated in Figure 11. The power derating curve for any CLC453 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA Bandwidth vs. Output Amplitude The bandwidth of the CLC453 is at a maximum for output voltages near 1Vpp. The bandwidth decreases for smaller and larger output amplitudes. Refer to the Frequency Response vs. Vo plots. Load Termination The CLC453 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC453 will improve stability and settling performance. The Frequency Response vs. CL and Recommended Rs vs. C L plots, in the typical performance section, give the recommended series resistance value for optimum flatness at various capacitive loads. Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. where Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) 9 http://www.national.com 1.0 AJP s AJE SOT 0.8 Power (W) s s 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 140 160 180 Rt - Optional resistor for inverting gain configurations (Select Rt to yield desired input impedance = Rg || Rt) C1, C2 - 0.1µF ceramic capacitors C3, C4 - 6.8µF tantalum capacitors C5, C6, C7, C8 R1 thru R8 Components not used: s s Ambient Temperature (°C) 450 Figure 11: Power Derating Curve Fig8 The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC453 To optimize off-isolation of the CLC453, cut the Rf trace on both the CLC730013 and the CLC730027 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 12 shows where to cut both evaluation boards for improved off-isolation. OUT Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC453 (CLC730013-DIP, CLC730027-SOIC, CLC730068-SOT) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: + C3 C4 R2 R8 RF C1 R7 C5 ROUT C6 C2 R6 R3 R1 s s s s s s Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. + C8 R5 C7 RIN A National Semiconductor Company Comlinear (303) 226-0500 730013 REV C -Vcc GND +Vcc IN Cut trace here 407 Fig4 (Left) Cut trace here 407 Fig 3 (Right) Figure 12: Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Comlinear’s monolithic amplifiers that: s s Evaluation Board Information Data sheets are available for the CLC730013/ CLC730027 and CLC730068 evaluation boards. The evaluation board data sheets provide: s s s Evaluation board schematics Evaluation board layouts General information about the boards s Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations The CLC730013/CLC730027 data sheet also contains tables of recommended components to evaluate several of Comlinear’s high speed amplifiers. This table for the CLC453 is illustrated below. Refer to the evaluation board data sheet for schematics and further information. Components Needed to Evaluate the CLC453 on the Evaluation Board: s The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for Comlinear’s Op Amps, contains schematics and a reproduction of the readme file. Application Circuits Single Supply Cable Driver The typical application shown on the front page shows the CLC453 driving 10m of 75Ω coaxial cable. The CLC453 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. 10 Rin, Rout - Typically 50Ω (Refer to the Basic Operation section of the evaluation board data sheet for details) http://www.national.com RG R4 Twisted Pair Driver The high output current and low distortion, of the CLC453, make it well suited for driving transformers. Figure 13 illustrates a typical twisted pair driver utilizing the CLC453 and a transformer. The transformer provides the signal and its inversion for the twisted pair. 1 2 Vin Rt 3 4 + 1kΩ 1kΩ Req = RL n2 8 7 6 V = Av Vin V= Rm 1:n n A v Vin 4 Zo RL UTP Req Av = 2 V= -n A v Vin 4 IL Select the transformer so that it loads the line with a value close to Zo, over the desired frequency range. The output impedance, Ro, of the CLC453 varies with frequency and can also affect the return loss. The return loss, shown below, takes into account an ideal transformer and the value of Ro. Return Loss(dB) ≈ − 20log10 n2 ⋅ Ro Zo CLC453 5 6.8µF + Vo - 0.1µF VEE Vo = 1n A v Vin 2 Figure 13: Twisted Pair Driver 453 Fig13 The load current (IL) and voltage (Vo) are related to the CLC453’s maximum output voltage and current by: Vo ≤ n ⋅ Vmax IL ≤ I max n To match the line’s characteristic impedance (Zo) set: s s RL = Z o Rm = Req Where Req is the transformed value of the load impedance, (RL), and is approximated by: From the above current relationship, it is obvious that an amplifier with high output drive capability is required. 11 http://www.national.com Comlinear CLC453, Single Supply, Low-Power, High Output, Programmable Buffer Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. 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