CLC522ALC

CLC522 Wideband Variable-Gain Amplifier June 1999 N CLC522 Wideband Variable-Gain Amplifier General Description The CLC522 variable gain amplifier (VGA) is a dc-coupled, twoquadrant multiplier with differential voltage inputs and a single-ended voltage output. Two input buffers and an output operational amplifer are integrated with the multiplier core to make the CLC522 a complete VGA system that does not require external buffering. The CLC522 provides the flexibility of externally setting the maximum gain with only two external resistors. Greater than 40dB gain control is easily achieved through a single high impedance voltage input. The CLC522 provides a linear (in Volts per Volt) relationship between the amplifier's gain and the gain-control input voltage. The CLC522's maximum gain may be set anywhere over a nominal range of 2V/V to 100V/V. The gain control input then provides attenuation from the maximum setting. For example, set for a maximum gain of 100V/V, the CLC522 will provide a 100V/V to 1V/V gain control range by sweeping the gain control input voltage from +1 to -0.98V. Set at a maximum gain of 10V/V, the CLC522 provides a 165MHz signal channel bandwidth and a 165MHz gain control bandwidth. Gain nonlinearity over a 40dB gain range is 0.5% and gain accuracy at A Vmax = 10V/V is typically ±0.3%. Features s s s s s s s 330MHz signal bandwidth: Avmax = 2 165MHz gain-control bandwidth 0.3° to 60MHz linear phase deviation 0.04% (-68dB) signal-channel non-linearity >40dB gain-adjustment range Differential or single-end voltage inputs Single-ended voltage output Variable attenuators Pulse amplitude equalizers HF modulators Automatic gain control & leveling loops Video production switching Differential line receivers Voltage controlled filters Gain vs. Gain Control Voltage (V g ) 10 Applications s s s s s s s Gain (V/V) 0 -1.1 Gain Control Voltage, Vg (Volts) 1.1 Typical Application 2nd Order Tuneable Bandpass Filter Pinout DIP & SOIC  1 = −  Vin  n  s 2 + s Vo Rf Rg s 1 CRb k 1 +2 CRb C R y 2 k Rb Ry , ωo = k CR y k = 185 . , Q= © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC522 Electrical Characteristics (V PARAMETERS Ambient Temperature CONDITIONS AJ CC = ±5V; AVmax = +10; Rf =1kΩ ; Rg =182W; RL = 100Ω ; Vg=+1.1V) +25 MIN/MAX RATINGS 0 to +70 -40 to +85 UNITS °C NOTES 1 TYP +25 FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 0.5Vpp Vout < 5.0Vpp gain control bandwidth Vout < 0.5Vpp gain flatness Vout < 0.5Vpp peaking DC to 30MHz rolloff DC to 30MHz linear phase deviation DC to 60MHz feedthrough 30MHz TIME DOMAIN RESPONSE rise and fall time 0.5V step 5.0V step settling time 2.0V step to 0.1% overshoot 0.5V step slew rate 4.0V step DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 2Vpp, 20MHz 3rd harmonic distortion 2Vpp, 20MHz equivalent input noise 1 to 200MHz noise floor 1 to 200MHz GAIN ACCURACY signal channel nonlinearity (SGNL) Vout = ±2Vpp gain control nonlinearity (GCNL) full range gain error (GACCU) AVmax=+10 Vg high low STATIC DC PERFORMANCE Vin voltage range common mode bias current average drift offset current average drift resistance capacitance Vg bias current average drift resistance capacitance output voltage range RL= ∞ current offset voltage AVmax=+10 average drift resistance IRgmax power supply sensitivity output referred common-mode rejection ratio input referred supply current RL= ∞ 165 150 165 0 0.05 0.3 - 62 2.2 3.0 12 2 2000 - 50 - 65 5.8 - 152 0.04 0.5 ± 0.0 + 990 - 975 ± 2.2 9 65 0.2 5 1500 1.0 15 125 100 1.0 ± 4.0 ± 70 25 100 0.1 1.8 10 70 46 120 100 120 0.1 0.25 1.0 - 57 2.9 5.0 18 15 1400 - 44 - 58 6.2 - 150 0.1 2.0 ± 0.5 + 990±60 - 975±80 ± 1.2 21 --2.0 --650 2.0 38 --38 2.0 ± 3.7 ± 47 85 --0.2 1.37 40 59 61 115 95 115 0.1 0.25 1.1 - 57 3.0 5.0 18 15 1400 - 44 - 56 6.5 - 149 0.1 2.2 ± 0.5 + 990±60 - 975±80 ± 1.2 26 175 3.0 30 450 2.0 47 300 30 2.0 ± 3.6 ± 40 95 350 0.3 1.26 40 59 62 110 90 110 0.1 0.4 1.2 -57 3.2 5.0 18 15 1400 -44 -54 6.8 - 149 0.1 3.0 ± 1.0 + 990±60 - 975±80 ± 1.4 45 275 4.0 40 175 2.0 82 600 15 2.0 ± 3.5 ± 25 120 400 0.6 1.15 40 59 63 MHz MHz MHz dB dB ° dB ns ns ns % V/µs dBc dBc nV/√Hz dBm1Hz % % dB mV mV V µA nA/°C µA nA/°C kΩ pF µA nA/°C kΩ pF V mA mV µV/°C Ω mA mV/V dB mA 3 4 2 2 2 2 2 2 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) transistor count ±7V 80mA ±Vcc +150°C -65°C to+150°C +300°C 74 Ordering Information Model CLC522AJP CLC522AJE CLC522ALC CLC522AMC Temperature Range -40°C -40°C -40°C -55°C to to to to +85°C +85°C +85°C +125°C Description 14-pin PDIP 14-pin SOIC dice dice, MIL-STD-883 Notes 1) AJE (SOIC) is tested/guaranteed with Rf=866Ω and Rg= 165Ω. 2) J-level, spec is 100% tested at +25°C. 3) Specified with Vin = 0.2V and Vg < 0.5Vpp. 4) Feedtrough is specified at max. attenuation (i.e Vg =-1.1V) http://www.national.com Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) CerDIP θJC 55°C/W 35°C/W 40°C/W θ JA 100°C/W 105°C/W 95°C/W 2 C LC522 Typical Performance Frequency Response (A V max =2) Phase (45 ° /div) Normalized Magnitude (1dB/div) (T A =+25 ° C, V cc = ± 5V, A v =+10, V g =1.1V, R L =100 Ω ; unless noted) Frequency Response (A V max =10) Phase (45 ° /div) Frequency Response (A V max =100) Phase (45 ° /div) Normalized Magnitude (1dB/div) Gain Normalized Magnitude (1dB/div) Vout = 2Vpp Vout = 500m Vpp Gain Vin = 25mVpp Gain A V =A Vmax (V g =1.0V) Phase A V =A Vmax (V g =1.0V) Phase A V =A Vmax (V g =1.0V) Phase 0 -45 -90 0 -45 -90 0 -45 -90 R g =2k Ω R f = 2.2k Ω 1 A V =1 (V g =0V) Frequency (MHz) -135 -180 -270 500 R g =182 Ω R f = 1k Ω 1 A V =1 (V g =-0.8V) Frequency (MHz) -135 -180 -270 200 R g =10.2 Ω R f = 715 Ω 1 A V =1 (V g =-0.98V) Frequency (MHz) -135 -180 -270 100 PSRR and CMRR (Input Referred) 100 90 80 PSRR/CMRR (dB) Feed-through Isolation 55 40 25 Gain (dB) Gain Flatness & Linear Phase Deviation Vo=2.5Vpp CMRR Gain Magnitude (0.1dB/div) 70 60 50 40 30 20 10 0 10 4 PSRR 10 -5 -20 -35 -50 -65 -80 -95 10 5 10 6 10 7 Frequency (Hz) 10 8 1 10 Frequency (MHz) 10 0 AVmax=+2 Rf=2kΩ AVmax=+10 Rf=1kΩ AVmax=+100 Rf=750Ω A v max + 10 Vo = 2Vpp R f = 1k Vg = 1.1V Deviation from Linear Phase(0.1 °/div) V g =+1.1V V g =-1.1V Phase 0 Frequency (3MHz/div) 30MHz SGNL vs. Vg , Gain 0.20 Full Scale Non-linearity (%) Large Signal Frequency Response 10 Magnitude Magnitude (1dB/div) Large & Small Signal Pulse Response Av max = +10 3 Large signal (Volts) 0.18 0.16 0.14 Gain (V/V) A v max = +2 R f = 2k Ω Vo = 5Vpp V g = 1.1V Phase (deg) 2 1 0 -1 -2 -3 Vg =1.0V R f = 1k Ω V o u t = 5V p p +.75 +.50 Small Signal (Volts) 0.12 0.10 0.08 0.06 0.04 0.02 0.00 SGNL Gain A v max = +10 R f = 1k Ω Phase 0 -45 -90 -135 -180 -225 250 V out = 0.5V pp +.25 0 -.25 -.50 -.75 A v max = +100 R f = 806 Ω 0 0 Frequency (25MHz/div) 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 -0.9 Vg (Volts) A v max = + 10 Ti m e ( 5 n s / d i v ) Gain Control Settling Time & Delay V in = 0.25V DC +1V 0 -1V Gain Control Channel Feedthrough Vin = 0 Vg Input Settling Error (%) Short Term Settling Time .2 .15 0.1 .05 0 -.05 -.1 -.15 -.2 A V max = + 10 2V output step V g = 1.0V 2.5 Vout (0.5V/div.) Vout 100mV/div V g = 1.0V Vg V g = -1.0V Time (5ns/div) Output 0 Time (5ns/div) 0 Time (10ns/div) 100 Long Term Settling Time .20 .15 Settling Error (%) Settling Time vs. Capacitive Load A V max = + 10 2V output step V g = 1.0V Settling Time, TS, (ns), to 0.1% Settling Time vs. Gain 100 90 70 60 50 40 Rs (ohms) Settling Time to 0.1% (ns) 50 Vg=1.0Volt 1kΩ A v max = +10 Rs 1kΩ 50 45 40 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 Attenuation From Maximum Gain (dB) 14 A v max = 20 A v max = 10 A vmax = 5 V o = 1V pp R f = 2k Ω 50Ω .10 .05 0 -.05 -.10 -.15 40 30 20 Ts 10 0 Rs 182Ω CLC522 80 CL 30 20 10 0 1000 -.20 -8 -7 -6 -5 -4 -3 -2 -1 0 9 10 10 10 10 10 10 10 10 10 10 Time (sec) 10 100 Load Capacitance, C L (pF) 3 http://www.national.com CLC522 Typical Performance Differential Gain and Phase .25 .20 Gain Negative Sync Phase Negative Sync 4.43 MHz A v max = +10 V g = 1.0V .25 (T A =+25 ° C, V cc = ± 5V, A v =+10, V g =1.1V, R L =100 Ω ; unless noted) Differential Gain and Phase .10 Phase, V g = 0.0V .08 4.43 MHz Positive Sync A v max = +2 .10 Input Referred Voltage Noise vs A Vmax 100 DifferentialPhase (degrees) DifferentialPhase (degrees) .15 .10 Phase Positive Sync Gain Positive Sync .15 .10 .05 0 .06 Phase, V g = 1.0V Gain, V g = 1.0V .04 .02 Gain, V g = 0.0V 0 .06 .04 .02 0 .05 0 Voltage Noise (nV/ √ Hz) .20 .08 Differential Gain (%) Differential Gain (%) 10 1 2 3 Number of 150Ω Loads 4 1 2 3 Number of 150 Ω Loads Vg 1.1V 4 1 0 10 20 30 40 50 60 70 80 90 100 Maximum Gain Setting, AVmax (V/V) Output Limited R f = 1.4k Ω 2nd Harmonic Distortion vs. P out -35 -40 -45 -50 -55 20MHz -60 -65 -70 -75 -80 -85 -4 -2 -35 -40 3rd Harmonic Distortion vs. P out Rf 1kΩ 50 Ω Po 20 19 18 17 16 15 14 13 12 11 10 -1dB Compression at Maximum Gain 50 Ω 50MHz -1dB Compression (dBm) Distortion Level (dBc) Distortion Level (dBc) 50MHz -45 -50 -55 -60 -65 -70 -75 -80 -85 -4 182 Ω 522 50 Ω 20 Ω 50 Ω 20MHz 10MHz 5MHz 50 Ω 182 Ω Vg 1.1V 522 Rf 10MHz Input Limited R f = 900 Ω Pi Rf Rg 522 1kΩ 50 Ω Po 20 Ω 50 Ω 50 Ω 50 Ω Po 20 Ω 50 Ω 5MHz 50 Ω 50 Ω 0 2 4 6 Output Power (Pout, dBm) 8 10 -2 0 2 4 6 Output Power (Pout, dBm) 8 10 0 Frequency (MHz) 100 Application Discussion Theory of Operation The CLC522 is a linear wideband variable-gain amplifier as illustrated in Fig 1. A voltage input signal may be applied differentially between the two inputs (+Vin, -Vin), or single-endedly by grounding one of the unused inputs. sin ce IR = g Vinput Rg A v = 185∗ . R f  Vg + 1 ∗  Rg  2  Eq. 2 The gain of the CLC522 is therefore a function of three external variables; Rg, Rf and Vg as expressed in Eq. 2. The gain-control voltage (Vg) has a ideal input range of -1V ≤ Vg ≤ +1V. At Vg=+1V, the gain of the CLC522 is at its maximum as expressed in Eq. 3. AV max R = 185 f . Rg Eq. 3 Notice also that Eq. 3 holds for both differential and single-ended operation. Fig. 1 The CLC522 input buffers convert the input voltage to a current (IRg) that is a function of the differential input voltage (Vinput =+Vin - -Vin) and the value of the gainsetting resistor (Rg). This current (IRg) is then mirrored to a gain stage with a current gain of 1.85. The voltagecontrolled two-quadrant multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output amplifier is a current-feedback op amp configured as a transimpedance amplifier. It's transimpedance gain is the feedback resistor (Rf). The input signal, output, and gain control are all voltages. The output voltage can easily be calculated as seen in Eq. 1.  Vg + 1 Vout = IR ∗185∗  .  ∗R f g 2 http://www.national.com Choosing Rf and Rg Rg is calculated from Eq.4. Vinput max is the maximum peak Rg = Vinput IR max gmax Eq. 4 input voltage (Vpk) determined by the application. IRgmax is the maximum allowable current through Rg and is typically 1.8mA. Once A Vmax is determined from the minimum input and desired output voltages, Rf is then determined using Eq. 5. These values of Rf and Rg are Eq. 1 4 ∗R g ∗ A V Eq. 5 max 185 . the minimum possible values that meet the input voltage and maximum gain constraints. Scaling the resistor values will decrease bandwidth and improve stability. Rf = 1 terms are specified in the Electrical Characteristics table and are defined below and illustrated in Fig. 4. : error of A Vmax , expressed as ±dB. GCNL : deviation from theoretical expressed as ±%. Vg high : voltage on Vg producing A Vmax . Vg : voltage on Vg producing A V = 0V/V. low min ∆Vg , ∆Vg : error of Vg , Vg expresed as ±mV. GACCU high low high low AV AVmax ±GACCU ±GCNL Fig. 2 Fig. 2 illustrates the resulting CLC522 bandwidths as a function of the maximum and minimum input voltages when Vout is held constant at 1Vpp. Adjusting Offsets Treating the offsets introduced by the input and output stages of the CLC522 is easily accomplished with a two step process. The offset voltage of the output stage is treated by first applying -1.1Volts on Vg, which effectively ±∆Vglow AVmin ±∆Vghigh Vg Vghigh Vglow Fig. 4 Combining these error terms with Eq. 2 gives the "gain envelope" equation and is expressed in Eq. 7. From the Electrical Characteristics table, the nominal endpoint values of Vg are: Vghigh =+990mV and Vglow = -975mV. ± GACCU     10 20 Vg − Vg ± ∆Vg low low A V = A V max  ± 1 − Vg 2 GCNL V  ± ∆Vg − Vg ± ∆Vg high low low  ghigh    ( ( )( ) ) Eq . 7 Fig. 3 isolates the input stage and multiplier core from the output stage. As illustrated in Fig. 3, the trim pot located at R14 on the CLC522 Evaluation Board should then be adjusted in order to null the offset voltage seen at the CLC522's output (pin 10). Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated. The second step requires the absence of an input signal and matched source impedances on the two input pins in order to cancel the bias current errors. This done then +1.1Volts should be applied to Vg and the trim pot located at R10 adjusted in order to null the offset voltage seen at the CLC522's output. If a more limited gain range is anticipated, the above adjustments should be made at these operating points. Gain Errors The CLC522's gain equation as theoretically expressed in Eq. 2 must include the device's error terms in order to yield the actual gain equation. Each of the gain error Signal-Channel Nonlinearity Signal-channel nonlinearity, SGNL, also known as integral endpoint linearity, measures the non-linearity of an amplifier’s voltage transfer function. The CLC522's SGNL, as it is specified in the Electrical Characteristics table, is measured while the gain is set at its maximum (i.e. Vg=+1.1V). The Typical Performance Characteristics plot labled "SGNL & Gain vs Vg" illustrates the CLC522's SGNL as Vg is swept through its full range. As can be seen in this plot, when the gain as reduced from A Vmax , SGNL improves to < 0.02%(-74dB) at Vg=0 and then degrades somewhat at the lowest gains. Noise Fig. 5 describes the CLC522's input-refered spot noise density as a function of A Vmax . The plot includes all the noise contributing terms. At A Vmax = 10V/V, the CLC522 has a typical input-referred spot noise density (eni) of 5.8nV/√Hz. The input RMS voltage noise can be determined from the following single-pole model: VRMS = ein ∗ 157∗ ( −3dB bandwidth) . Eq. 8 5 Further discussion and plots of noise and the noise model is provided in Application Note OA-23. Comlinear also provides SPICE models that model internal noise and other parameters for a typical part. http://www.national.com 100 Input Referred Voltage Noise vs A Vmax Voltage Noise (nV/ √ Hz) 10 Component parasitics also influence high frequency results, therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. If socketing is necessary, it is recommended to use low impedance flush mount connector jacks such as Cambion (P/N 450-2598). Application Circuits Four-Quadrant Multiplier Applications requiring multiplication, squaring or other non-linear functions can be implemented with four-quadrant multipliers. The CLC522 implements a four-quadrant multiplier as illustrated in figure 8. Rm = 2Rg 1.85 1 0 10 20 30 40 50 60 70 80 Maximum Gain Setting, AVmax (V/V) 90 100 Fig. 5 Circuit Layout Considerations Please refer to the CLC522 Evaluation Board Literature for precise layout guidelines. Good high-frequency operation requires all of the de-coupling capcitors shown in Fig. 6 to be placed as close as possible to the power Rs Vcarrier 50Ω 3 4 Vbaseband RT Rg RT = RmRs Rm-Rs Rf 50Ω 10 2 12 CLC522 9 5 6 Vout 50Ω 25Ω R1 R1 = RT || Rm || Rs Fig. 8 Frequency Shaping Frequency shaping and bandwidth extension of the CLC522 can be accomplished using parallel networks connected across the Rg ports. The network shown in the Fig. 9 schematic will effectively extend the CLC522's bandwidth. Fig. 6 supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate ground plane and lowinductive power returns are also required of the layout. Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9, Fig. 7 10 and 12 as shown in Fig. 7 will assure best high frequency performance. Vref (pin 9) to ground should include a small resistor value of 25 ohms or greater to buffer the internal voltage follower. The parasitic inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or circuit oscillation. This should be treated with a small series resistor between output (pin 10) and CL (see the plot “Settling Time vs. Capacitive Load" for a recommended series resistance). http://www.national.com Fig. 9 2nd Order Tuneable Bandpass Filter The CLC522 Variable-Gain Amplifier placed into feedback loops provide signal processing functions such as 2nd order tuneable bandpass filters. The center frequency of the 2nd order bandpass illustrated on the front page is adjusted through the use of the CLC522's gaincontrol voltage, Vg. The integrators implemented with two CLC420s, provide the coefficients for the transfer function. 6 This page intentionally left blank. 7 http://www.national.com CLC522 Wideband Variable-Gain Amplifier Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. 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