CLC5523IM

CLC5523 Low-Power, Variable Gain Amplifier March 2000 CLC5523 Low-Power, Variable Gain Amplifier General Descriptions The CLC5523 is a low power, wideband, DC-coupled, voltagecontrolled gain amplifier. It provides a voltage-controlled gain block coupled with a current feedback output amplifier. High impedance inputs and minimum dependence of bandwidth on gain make the CLC5523 easy to use in a wide range of applications. This amplifier is suitable as a continuous gain control element in a variety of electronic systems which benefit from a wide bandwidth of 250MHz and high slew rate of 1800V/ms, with only 135mW of power dissipation. Input impedances in the megaohm range on both the signal and gain control inputs simplify driving the CLC5523 in any application. The CLC5523 can be configured to use pin 3 as a low impedance input making it an ideal interface for current inputs. By using the CLC5523’s inverting configuration in which RG is driven directly, inputs which exceed the device’s input voltage range may be used. The gain control input (VG), with a 0 to 2V input range, and a linear-in-dB gain control, simplifies the implementation of AGC circuits. The gain control circuit can adjust the gain as fast as 4dB/ns. Maximum gains from 2 to 100 are accurately and simply set by two external resistors while attenuation of up to 80dB from this gain can be achieved. The extremely high slew rate of 1800V/ms and wide bandwidth provides high speed rise and fall times of 2.0ns, with settling time for a 2 volt step of only 22ns to 0.2%. In time domain applications where linear phase is important with gain adjust, the internal current mode circuitry maintains low deviation of delay over a wide gain adjust range. Features s s s s s s Low power: 135mW 250MHz, -3dB bandwidth Slew rate 1800V/ms Gain flatness 0.2dB @ 75MHz Rise & fall times 2.0ns Low input voltage noise 4nV/ÖHz Automatic gain control Voltage controlled filters Automatic signal leveling for A/D Amplitude modulation Variable gain transimpedance Applications s s s s s Frequency Response with Changes in Vg 30 20 Magnitude (10dB/div) 10 0 -10 -20 -30 -40 -50 1M 10M 100M Frequency (Hz) Typical Application Variable Gain Amplifier Circuit VG +5V 2 3 1 Pinout DIP & SOIC VG +VCC X1 Vin + 4 8 6 7 5 CLC5523 Vo RL VIN Rg GND IVO -VCC + Rg Rf 25W -5V © 2000 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC5523 Electrical Characteristics (VCC = ±5V, Rf = 1k, Rg = 100W, RL = 100W, VG = 2V; unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC5523I TYP +25˚C 250 100 0 0.2 0.6 95 2.0 6.0 22 700 1800 4 -65 -80 -57 -75 5 4 36 50 ±3.8 3.0 3.0 1.0 7.0 7.0 0.04 0.3 0.5 10 1.0 40 57 13.5 ±3.4 ±3.0 0.1 80 146 MIN/MAX RATINGS 25˚C -40 to 85˚C 150 45 0.8 1.0 1.5 70 2.8 15 30 450 1000 125 35 2.0 1.2 3.0 60 3.0 20 60 400 700 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo < 0.5Vpp Vo < 4.0Vpp peaking DC to 200MHz (Vo = 0.5Vpp) rolloff DC to 75MHz (Vo = 0.5Vpp) linear phase deviation DC to 75MHz (Vo = 0.5Vpp) gain control bandwidth Vin = 0.2VDC, Vg = 1VDC TIME DOMAIN RESPONSE rise and fall time overshoot settling time to 0.2% non-inverting slew rate inverting slew rate gain control response rate 0.5V step 0.5V step 2V step 4V step 4V step MHz MHz dB dB deg MHz ns % ns V/ms V/ms dB/nS dBc dBc dBc dBc nV/ÖHz nV/ÖHz pA/ÖHz mV V mA MW pF mA mA % dB mA MW pF mA dB mA V V W mA A A 1 DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 1Vpp, 5MHz 3rd harmonic distortion 1Vpp, 5MHz 2nd harmonic distortion 1Vpp, 10MHz 3rd harmonic distortion 1Vpp, 10MHz input referred total noise Vg = 2V input referred voltage noise Rg referred current noise STATIC DC PERFORMANCE output offset voltage Vin signal input input voltage range Rg open input bias current input resistance input capacitance IRgmax 0° to 70°C IRgmax -40° to 85°C signal ch. non-linearity SGNL Vo = 2Vpp gain accuracy* Vg gain input input bias current input resistance input capacitance ground pin current power supply rejection ratio input-referred supply current RL= ¥ output voltage range no load output voltage range RL = 100W output impedance output current transistor count *maximum gain is defined as Rf/Rg – – -52 -58 6 5.5 50 120 ±3.6 8.0 1.0 1.5 5.0 5.0 0.1 0.5 2.0 2.0 1.5 55 50 15 ±3.0 ±2.5 0.15 65 – – -40 -54 7 5.5 60 150 ±3.3 16 0.8 1.7 4.0 2.5 0.2 0.9 4.0 2.0 1.5 65 46 16 ±2.3 ±2.3 0.15 50 A A Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) I-level: spec is 100% tested at +25˚C. 1) See plot “Gain Control Settling Time”. Model Ordering Information Temp Range Description CLC5523IN -40°C to +85°C 8-pin DIP CLC5523IM -40°C to +85°C 8-pin Small outline CLC5523IMX -40°C to +85°C 8-pin Small outline tape and reel Contact the factory for other packages. Absolute Maximum Ratings supply voltage output current maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) ±7V ±80mA +150˚C -65˚C to +150˚C +300˚C TBD Package Thermal Resistance Package DIP (IN) Small Outline (IM) qJC 65°C/W 55°C/W qJA 115°C/W 135°C/W http://www.national.com 2 CLC5523 Typical Performance (VG = +2V, Rf = 1kW, Rg = 100W, RL = 100W, Vo = 0.5Vpp; Frequency Response (Avmax =10) 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 1 10 100 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 1 10 100 unless specified) Frequency Response (Avmax = 2) 45 40 35 30 25 20 15 10 5 0 -5 -10 Frequency Response (Avmax = 100) Magnitude (5dB/div) Magnitude (5dB/div) Magnitude (5dB/div) 1 10 100 Frequency (MHz) Frequency Response vs. RL 360 Frequency (MHz) Frequency Response vs. Rg Rg = 500W Frequency (MHz) Frequency Response vs. Rf Rf = 689W Magnitude (1dB/div) Magnitude (1dB/div) Magnitude RL = 1k 180 Phase 0 RL = 50W RL = 100W Rg = 10W Rg = 33W Rg = 100W Magnitude (1dB/div) Rf = 1k Phase (deg) -180 -360 -450 Rf = 2k Rf = 5k 1 10 100 1 10 100 1 10 100 Frequency (MHz) PSRR & Rout 60 PSRR Frequency (MHz) Feed-Through Isolation (VG = 0, 2) 100 40 10 20 Avmax = 10 Avmax = 100 Frequency (MHz) Gain Flatness & Linear Phase Deviation Vo = 2Vpp Magnitude (0.1dB/div) Magnitude (dB) 50 Gain Phase (0.5¡C/div) Gain (dB) 0 -20 -40 Rout (W) 40 1.0 Phase 30 Rout 0.1 -60 0.01 0.01 0.10 1 10 100 -80 1 10 100 20 0 15 30 45 60 75 Frequency (MHz) Large Signal Frequency Response 100 Frequency (MHz) Equivalent Input Noise 1000 20 Frequency (MHz) Input Referred Total Noise Input Voltage Noise (nVÖHz) Input Current Noise (pAÖHz) 18 16 14 12 10 8 6 4 2 0 100 200 300 400 500 Inverting Vout = 2Vpp Vout = 4Vpp Non-Inverting Input Voltage Noise (nVÖHz) Vout = 1Vpp Magnitude (1dB/div) 10 Voltage Noise Current Noise 100 Vout = 1Vpp Vout = 2Vpp Vout = 4Vpp 1 10 100 1 0.0001 10 0.001 0.01 0.1 1 10 Frequency (MHz) Gain (V/V) vs. Vg 10 9.0 8.0 7.0 -40¡C Frequency (MHz) Gain (dB) vs. Vg 20 10 85¡C RG (W) Large & Small Signal Pulse Response 2.5 Large 0.5 0.4 0.3 Small Amplitude (0.5V/div) 25¡C 0 1.5 0.5 -0.5 -1.5 -2.5 Amplitude (0.1V/div) Gain (V/V) 6.0 5.0 4.0 3.0 2.0 1.0 0 0 0.4 0.8 1.2 Gain (dB) 85¡C 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -10 -20 -30 25¡C -40¡C -40 -50 -60 1.6 2.0 0 0.4 0.8 1.2 1.6 2.0 Time (5ns/div) Vg Voltage (V) Vg Voltage (V) 3 http://www.national.com CLC5523 Typical Performance 2nd Harmonic Distortion vs. Frequency -30 Vo = 1Vpp (VG = +2V, Rf = 1kW, Rg = 100W, Avmax = 10; unless specified) 3rd Harmonic Distortion vs. Frequency Harmonic Distortion vs. Output Voltage -50 Vo = 1Vpp RL = 100 -40 -50 2nd RL = 100W -40 -60 2nd = 10MHz Distortion (dBc) Distortion (dBc) -50 -60 -70 -80 -90 Distortion (dBc) -60 -70 -80 -90 3rd RL = 100W 3rd RL = 1k -70 -80 -90 2nd = 1MHz 3rd = 10MHz 2nd RL = 1k -100 -110 3rd = 1MHz -100 1 10 -100 1 10 0 0.5 1 1.5 2 2.5 Frequency (MHz) Harmonic Distortion vs. Gain -30 RL = 100 Vo = 100mVpp Frequency (MHz) Input Harmonic Distortion (Av = 2) 60 VG = 1.04V Rg = 250W Output Voltage (Vpp) Differential Gain & Phase (NTSC) 0.05 Phase 0.05 0 Distortion (dBc) Distortion (dBc) -50 50 VG = 0.94V Rg = 100W Phase (deg) Gain (%) 0 Gain -0.05 -0.1 -0.15 -0.2 -70 3rd = 10MHz 2nd = 10MHz 2nd = 1MHz 40 -0.05 30 -90 3rd = 1MHz -110 0.1 1 10 20 0 0.5 1.0 1.5 2.0 -0.1 -1.6 -0.8 0 0.8 1.6 -0.25 Gain (Av) Short Term Settling Time 0.2 Vo = 2Vstep Input Voltage (V) Long Term Settling Time 0.15 Vo = 2Vstep DC Output Voltage Gain Control Settling Time 0.1 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1 100 10000 -0.2 0.001 0 Amplitude (0.5V/div) Vo Vo (% Output Step) Vo (% Output Step) Vg -0.1 0.01 0.1 1.0 10 100 Time (10ns/div) Time (ns) DC Offset vs. Temperature 120 Input Bias Current Time (ms) 2nd Tone, 3rd Order Intermod Intercept 2.5 50 45 Input Bias Current (mA) Output Offset (mV) 100 80 60 40 2.0 1.5 1.0 0.5 Intercept (dBm) 40 35 30 25 20 10 20 30 40 50 60 70 80 Output Offset Voltage 20 -60 -20 20 60 100 140 0 Temperature (¡C) Frequency (MHz) http://www.national.com 4 CLC5523 Operation The key features of the CLC5523 are: s s s s s s Low Power Broad voltage controlled gain and attenuation range Bandwidth independent, resistor programmable gain range Broad signal and gain control bandwidths Frequency response may be adjusted with Rf High Impedance signal and gain control Inputs The CLC5523 combines a closed loop input buffer, a voltage controlled variable gain cell and an output amplifier. The input buffer is a transconductance stage whose gain is set by the gain setting resistor, Rg. The output amplifier is a current feedback op amp and is configured as a transimpedance stage whose gain is set by, and equal to, the feedback resistor, Rf. The maximum gain, Avmax, of the CLC5523 is defined by the ratio; Rf / Rg. As the gain control input (VG) is adjusted over its 0 to 2V range, the gain is adjusted over a range of 80dB relative to the maximum set gain. Setting the CLC5523 Maximum Gain A vmax R =f Rg Using the CLC5523 in AGC Applications In AGC applications, the control loop forces the CLC5523 to have a fixed output amplitude. The input amplitude will vary over a wide range and this can be the issue that limits dynamic range. At high input amplitudes, the distortion due to the input buffer driving Rg may exceed that which is produced by the output amplifier driving the load. In the plot, Harmonic Distortion vs. Gain, second and third harmonic distortion are plotted over a gain range of nearly 40dB for a fixed output amplitude of 100mVpp in the specified configuration, Rf = 1k, Rg = 100W. When the gain is adjusted to 0.1 (i.e. 40dB down from Avmax), the input amplitude would be 1Vpp and we can see the distortion is at its worst at this gain. If the output amplitude of the AGC were to be raised above 100mV, the input amplitudes for gains 40dB down from Avmax would be even higher and the distortion would degrade further. It is for this reason that we recommend lower output amplitudes if wide gain ranges are desired. Using a post-amp like the CLC404 or CLC409 would be the best way to preserve dynamic range and yield output amplitudes much higher than 100mVpp. Another way of addressing distortion performance and its limitations on dynamic range, would be to raise the value of Rg. Just like any other high-speed amplifier, by increasing the load resistance, and therefore decreasing the demanded load current, the distortion performance will be improved in most cases. With an increased Rg, Rf will also have to be increased to keep the same Avmax and this will decrease the overall bandwidth. Gain Partitioning If high levels of gain are needed, gain partitioning should be considered. VG Vin + CLC425 Although the CLC5523 is specified at Avmax = 10, the recommended Avmax varies between 2 and 100. Higher gains are possible but usually impractical due to output offsets, noise and distortion. When varying Avmax several tradeoffs are made: Rg: determines the input voltage range Rf: determines overall bandwidth The amount of current which the input buffer can source into Rg is limited and is specified in the IRgmax spec. This sets the maximum input voltage: Vin (max) = IR gmax × R g The effects of maximum input range on harmonic distortion are illustrated in the Input Harmonic Distortion plot. Variations in Rg will also have an effect on the small signal bandwidth due to its loading of the input buffer and can be seen in Frequency Response vs. Rg. Changes in Rf will have a more dramatic effect on the small signal bandwidth. The output amplifier of the CLC5523 is a current feedback amplifier(CFA) and its bandwidth is determined by Rf. As with any CFA, doubling the feedback resistor will roughly cut the bandwidth of the device in half (refer to the plot Frequency Response vs. Rf). For more information covering CFA’s, there is a basic tutorial, OA-20, Current Feedback Myths Debunked or a more rigorous analysis, OA-13, Current Feedback Amplifier Loop Gain Analysis and Performance Enhancements. 5 25Wž Rc 2 3 1 CLC5523 R2 R1 6 Vo 7 4 Rf Rg 25W Figure 1: Gain Partitioning The maximum gain range for this circuit is given by the following equation: æ R ö æR ö maximum gain = ç1 + 2 ÷ × ç f ÷ R1 ø è R g ø è http://www.national.com The CLC425 is a low noise wideband voltage feedback amplifier. Setting R2 at 909W and R1 at 100W produces a gain of 20dB. Setting Rf at 1000W as recommended and Rg at 50W, produces a gain of 26dB in the CLC5523. The total gain of this circuit is therefore approximately 46dB. It is important to understand that when partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For example, with 46dB of gain, a 20mV signal at the input will drive the output of the CLC425 to 200mV, the output of the CLC5523 to 4V. Accordingly, the designer must carefully consider the contributions of each stage to the overall characteristics. Through gain partitioning the designer is provided with an opportunity to optimize the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved overall performance. CLC5523 Gain Control Range and Minimum Gain Before discussing Gain Control Range, it is important to understand the issues which limit it. The minimum gain of the CLC5523, theoretically, is zero, but in practical circuits is limited by the amount of feedthrough, here defined as the difference in output levels when VG = 2V and when VG = 0V. Capacitive coupling through the board and package as well as coupling through the supplies will determine the amount of feedthrough. Even at DC, the input signal will not be completely rejected. At high frequencies feedthrough will get worse because of its capacitive nature. At low frequencies, the feedthrough will be 80dB below the maximum gain, and therefore it can be said that the CLC5523 has an 80dB Gain Control Range. CLC5523 Gain Control Function In the two plots, Gain vs. VG, we can see the gain as a function of the control voltage. The first plot, sometimes referred to as the S-curve, is the linear (V/V ) gain. This is a hyperbolic tangent relationship. The second gain curve plots the gain in dB and is linear over a wide range of gains. Because of this, the CLC5523 gain control is referred to as “linear-in-dB.” For applications where the CLC5523 will be used at the heart of a closed loop AGC circuit, the S-curve control characteristic provides a broad linear (in dB) control range with soft limiting at the highest gains where large changes in control voltage result in small changes in gain. For applications, requiring a fully linear (in dB) control characteristic, use the CLC5523 at half gain and below (VG ² 1V). Avoiding Overdrive of the CLC5523 Gain Control Input There is an additional requirement for the CLC5523 Gain Control Input (VG): VG must not exceed +2.5V. The gain control circuitry may saturate and the gain may actually be reduced. In applications where VG is being driven from a DAC, this can easily be addressed in the software. If there is a linear loop driving VG, such as an AGC loop, other methods of limiting the input voltage should be implemented. One simple solution is to place a 2:1 resistive divider on the VG input. If the device driving this divider is operating off of ±5V supplies as well, its output will not exceed 5V and through the divider VG can not exceed 2.5V. Improving the CLC5523 Large Signal Performance Figure 2 illustrates an inverting gain scheme for the CLC5523. VG 2 1 CLC5523 25W 6 7 Vo Vin Rg 3 4 Rf 25W Figure 2: Inverting the CLC5523 The input signal is applied through the Rg resistor. The Vin pin should be grounded through a 25W resistor. The maximum gain range of this configuration is given in the following equation: æR ö A vmax = - ç f ÷ è Rg ø The inverting slew rate of the CLC5523 is much higher than that of the non-inverting slew rate. This 2.5X performance improvement comes about because in the non-inverting configuration, the slew rate of the overall amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does not affect slew rate. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 3 shows a typical circuit configuration for matching transmission lines. VG Zo Signal Input + - 2 1 CLC5523 Co 6 7 Rs Zo Ro Output RT Ri Rg 3 4 Rf 25W Figure 3: Transmission Line Matching The resistors Rs, Ri, Ro, and RT are equal to the characteristic impedance, Zo, of the transmission line or cable. Use Co to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp’s output impedance with frequency. http://www.national.com 6 Minimizing Parasitic Effects on Small Signal Bandwidth The best way to minimize parasitic effects is to use the small outline package and surface mount components. For designs utilizing through-hole components, specifically axial resistors, resistor self-capacitance should be considered. Example: the average magnitude of parasitic capacitance of RN55D 1% metal film resistors is about 0.15pF with variations of as much as 0.1pF between lots. Given the CLC5523’s extended bandwidth, these small parasitic reactance variations can cause measurable frequency response variations in the highest octave. We therefore recommend the use of surface mount resistors to minimize these parasitic reactance effects. If an axial component is preferred, we recommend PRP8351 resistors which are available from Precision Resistive Products, Inc., Highway 61 South, Mediapolis, Iowa. Small Signal Response at Low Avmax When the maximum gain, as set by Rg and Rf, is greater than or equal to Avmax = 10, little or no peaking should be observed in the amplifier response. When the gain range is set to less than Avmax = 10, some peaking may be observed at higher frequencies. At gain ranges of 2 ² Avmax ² 10 peaking can be minimized by increasing Rf. At gain ranges of Avmax < 2 peaking reaches approximately 6dB in the upper octave. If peaking is observed with the recommended Rf resistor, and a small increase in the Rf resistor does not solve the problem, then investigate the possible causes and remedies listed below. s s s s Long traces between CLC5523 and 0.1mF bypass capacitors s Keep these traces less than 0.2 inches (5mm) s For the devices in the PDIP package, an additional 1000pF monolithic capacitor should be placed less than 0.1” (3mm) from the pin Extra capacitance between the Rg pin and ground (CG) s See the Printed Circuit Board Layout sub-section below for suggestions on reducing CG s Increase Rf if peaking is still observed after reducing CG Non-inverting input pin connected directly to ground s Place a 50 to 200W resistor between the noninverting pin and ground Adjusting Offsets and DC Level Shifting Offsets can be broken into two parts: an input-referred term and an output-referred term. These errors can be trimmed using the circuit in Figure 4. First set VG to 0V and adjust the trim pot R4 to null the offset voltage at the output. This will eliminate the output stage offsets. Next set VG to 2V and adjust the trim pot R1 to null the offset voltage at the output. This will eliminate the input stage offsets. VG Vin 2 3 1 CLC5523 6 7 Vo +5V R1 10k -5V s s Capacitance across Rf s Do not place a capacitor across Rf s Keep traces connecting Rf separated and as short as possible Capacitive Loads s Place a small resistor (20-50W) between the output and CL Long traces and/or lead lengths between Rf and the CLC5523 s Keep these traces as short as possible R2 10k 0.1mF Rg 4 Rf R3 10k 0.1mF +5V R4 10k -5V 25W Figure 4: Offset Adjust Circuit 7 http://www.national.com Printed Circuit Board Layout High frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: s s s Use a ground plane Bypass each power supply pin with these capacitors: s a high-quality 0.1mF ceramic capacitor placed less than 0.2” (5mm) from the pin s a 6.8mF tantalum capacitor less than 2” (50mm) from the pin s for the plastic DIP package, a high-quality 1000pF ceramic capacitor placed less than 0.1” (3mm) from the pin Minimize or eliminate sources of capacitance between the Rf pin and the output pin. Avoid adjacent feedthrough vias between the Rf and output leads since such a geometry may give rise to a significant source of capacitance. s Minimize trace and lead lengths for components between the inverting and output pins s Remove ground plane 0.1” (3mm) from all input/output pads s For prototyping, use flush-mount printed circuit board pins; never use high profile DIP sockets To minimize high frequency distortion, other layout issues need be addressed: s s Capacitively bypassing power pins to a good ground plane with a minimum of trace length (inductance) is necessary for any high speed device, but it is particularly important for the CLC5523. s s Short, equal length, low impedance power supply return paths from the load to the supplies avoid returning output ground currents near the input stage. Establish wide, low impedance, power supply traces For the plastic DIP package, a 25W resistor should be connected from pin 4 to ground with a minimum length trace Evaluation Boards Evaluation boards are available for both the 8-pin DIP and small outline package types. Evaluation kits that contain an evaluation board and CLC5523 samples can be obtained by calling National Semiconductor’s Customer Service Center at 1-800-272-9959. The 8-pin DIP evaluation kit part number is CLC730065. The 8-pin small outline evaluation kit part number is CLC730066. Input Signal The DIP evaluation kit has been designed to utilize axial lead components. The small outline evaluation kit has been designed to utilize surface mount components. The circuit diagram shown in Figure 5, applies to both the DIP and the small outline evaluation boards. 5V 6.8mF VG Vin X1 Gain Control RX 50W Rin 50W Rg 100W +VCC IVo + - 0.1mF Rf 1kWž Rg GND Ro 50Wž Output -VCC 0.1mF * 25W 6.8mF -5V * 25W series resistor is not required on the small outline device and does not appear on the small outline board Figure 5: Evaluation Board Schematic http://www.national.com 8 Comlinear Layer1 Comlinear Layer2 Figure 6: DIP Evaluation Board (Top Layer) Figure 7: DIP Evaluation Board (Bottom Layer) Comlinear Layer1 Silk Comlinear Layer2 Silk 3255CLC DRAOB LAVE 4C 3C 5J oR DRAOB LAVE 3255CLC Figure 8: Small Outline Evaluation Board (Top Layer) Figure 9: Small Outline Evaluation Board (Bottom Layer) (Not drawn to scale) 9 http://www.national.com CLC5523 Applications Digital Gain Control Digitally variable gain control can be easily realized by driving the CLC5523’s gain control input with a digital-to-analog converter (DAC). Figure 10 illustrates such an application. This circuit employs National Semiconductor’s eight-bit DAC0830, the LM351 JFET input op-amp, and the CLC5523 VGA. With Vref set to 2V, the circuit provides up to 80dB of gain control in 512 steps with up to 0.05% full scale resolution. The maximum gain of this circuit is 20dB. Digital Input Rfb Io1 Vref DAC0830 Io2 LM351 Signal frequencies must not reach the gain control port of the CLC5523, or the output signal will be distorted (modulated by itself). A fast settling AGC needs additional filtering beyond the integrator stage to block signal frequencies. This is provided in Figure 11 by a simple R-C filter (R10 and C3); better distortion performance can be achieved with a more complex filter. These filters should be scaled with the input signal frequency. Loops with slower response time (longer integration time constants) may not need the R10 – C3 filter. Checking the loop stability can be done by monitoring the Vg voltage while applying a step change in input signal amplitude. Changing the input signal amplitude can be easily done with either an arbitrary waveform generator or a fast multiplexer such as the CLC532. + Vin 2 3 1 CLC5523 6 7 Vo RG 100W 4 Rf 1k 25W Figure 10: Digital Gain Control Automatic Gain Control (AGC) #1 Fast Response AGC Loop The AGC circuit shown in Figure 11 will correct a 6dB input amplitude step in 100ns. The circuit includes a two op-amp precision rectifier amplitude detector (U1 and U2), and an integrator (U3) to provide high loop gain at low frequencies. The output amplitude is set by R9. Some notes on building fast AGC loops: Precision rectifiers work best with large output signals. Accuracy is improved by blocking DC offsets, as shown in Figure 11. Includes scope probe capacitance C3 40pF R10 500W C2 680pF Rg 100W R8 500W R9 4.22k -5V Vin 2 3 1 Automatic Gain Control (AGC) #2 Figure 12 on the following page, illustrates an automatic gain control circuit that employs two CLC5523’s. In this circuit, U1 receives the input signal and produces an output signal of constant amplitude. U2 is configured to provide negative feedback. U2 generates a rectified gain control signal that works against an adjustable bias level which may be set by the potentiometer and Rb. Ci integrates the bias and negative feedback. The resultant gain control signal is applied to the U1 gain control input Vg. The bias adjustment allows the U1 output to be set at an arbitrary level less than the maximum output specification of the amplifier. Rectification is accomplished in U2 by driving both the amplifier input and the gain control input with the U1 output signal. The voltage divider that is formed by R1, R2 and the Vg input (pin 1) resistance, sets the rectifier gain. + CLC5523 6 7 4 Rf C1 1.0mF R3 R6 R4 500W R1 20W Output 20MHz, 0.1Vpp U3 CLC426 U2 CLC404 + - R5 25W + 500W 1N5712 Schottky 500W R7 500W U1 CLC404 + R2 25W Figure 11: Automatic Gain Control Circuit #1 http://www.national.com 10 +5V 2k Rb Level Adj. 100W -5V Signal Input Rg1 100W 2 3 1 U1 CLC5523 Rc 100W Ci 100pF 150W R1 100W 2.2mF Output 25W Rg2 100W 2 3 1 U2 CLC5523 6 7 50W 6 7 4 Rf1 1k 4 Rf2 1k Figure 12: Automatic Gain Control Circuit #2 11 http://www.national.com CLC5523 Low-Power, Variable Gain Amplifier LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-25-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12