CLC5903

CLC5903 Dual Digital Tuner / AGC June 2004 N 0 0 Na t i on a l S e m i c o n du c t o r CLC5903 Dual Digital Tuner / AGC General Overview The CLC5903 Dual Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated automatic gain control (AGC). The CLC5903 is a key component in the Enhanced Diversity Receiver Chipset (EDRCS) which includes one CLC5903 Dual Digital Tuner / AGC, two CLC5957 12-bit analog-to-digital converters (ADCs), and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). This system allows direct IF sampling of signals up to 300MHz for enhanced receiver performance and reduced system costs. The CLC5903 is an enhanced replacement for the CLC5902 in the Diversity Receiver Chipset (DRCS). The main improvements relative to the CLC5902 are a 50% increase in maximum sample rate from 52MHz to 78MHz, a 62% reduction in power consumption from 760mW to 290mW, and the added flexibility to independently program filter coefficients in the two channels. A block diagram for a DRCS-based narrowband communications system is shown in Figure 1. The CLC5903 offers high dynamic range digital tuning and filtering based on hard-wired digital signal processing (DSP) technology. Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering is performed by a series of three filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter with a programmable decimation ratio from 8 to 20 48. Next there a re two symmetric FIR filters, a 21-tap and a 63-tap, both with independent programmable coefficients. The first FIR filter decimates the data by 2, the second FIR decimates by either 2 or 4. Channel filter bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz. At 78MSPS, the maximum bandwidth increases to ±975kHz. The CLC5903’s AGC controller monitors the ADC output and controls the ADC input signal level by adjusting the DVGA setting. AGC threshold, deadband+hysteresis, and the loop time constant are user defined. Total dynamic range of greater than 120dB full-scale signal to noise in a 200kHz bandwidth can be achieved with the Diversity Receiver Chipset. Features 78MSPS Operation Low Power, 145mW/channel, 52 MHz, Dec=192 Two Independent Channels with 14-bit inputs Serial Daisy-chain Mode for quad receivers Greater than 100 dB image rejection Greater than 100 dB spurious free dynamic range 0.02 Hz tuning resolution User Programmable AGC with enhanced Power Detector Channel Filters include a Fourth Order CIC followed by 21-tap and 63-tap Symmetric FIRs FIR filters process 21-bit Data with 16-bit Programmable Coefficients Two independent FIR coefficient memories which can be routed to either or both channels. Flexible output formats include 12-bit Floating Point or 8, 16, 24, and 32 bit Fixed Point Serial and Parallel output ports JTAG Boundary Scan 8-bit Microprocessor Interface 128 pin PQFP and 128 pin FBGA packages 100% Software compatible with the CLC5902 Pin compatible with the CLC5902 except for VDD voltage Applications Cellular Basestations Satellite Receivers Wireless Local Loop Receivers Digital Communications CLC5526 LC CLC5957 12 CLC5903 SCK_IN SerialOutA/B SerialOutB SCK SFS RDY ParallelOutput[15..0] ParallelOutputEnable ParallelSelect[2..0] IF A DVGA ADC DAV 8 12 Dual Digital Tuner/AGC IF B CLK DVGA LC ADC DAV Figure 1. Diversity Receiver Chipset Block Diagram ©2004 National Semiconductor Corporation DS200286 www.national.com Revision 1.6 CLC5903 RD WR CE A[7:0] D[7:0] Microprocessor Interface Channel A Controls GAIN_A FREQ_A COEF_SEL_F1A PHASE_A DITH_A COEF_SEL_F2A AGC_IC_A AGC_RB_A AGAIN[2..0] ASTROBE AIN BIN MUX A 14 Channel A Tuning, Channel Filters, and AGC (see Figure 16) Output Formatter Floating Point: 4-bit Exponent and 8-bit Mantissa or Two’s Complement: 32-bit Truncated or 24-bit Rounded or 16-bit Rounded or 8-bit Truncated (see Figure 29) SCK_IN AOUT/BOUT BOUT SCK SFS RDY POUT[15..0] PSEL[2..0] POUT_EN MUX B 14 Channel B Tuning, Channel Filters, and AGC (see Figure 16) TEST_REG Input Source A_SOURCE B_SOURCE CKA CKB SI MR CLK GEN Sync Logic Channel B Controls GAIN_B FREQ_B COEF_SEL_F1B PHASE_B DITH_B COEF_SEL_F2B AGC_IC_B AGC_RB_B Common Channel Controls DEC DEC_BY_4 SCALE EXP_INH EXT_DELAY AGC_HOLD_IC AGC_LOOP_GAIN AGC_TABLE AGC_COMB_ORD PAGE_SEL_F1 F1A_COEFF F1B_COEFF PAGE_SEL_F2 F2A_COEFF F2B_COEFF BSTROBE BGAIN[2..0] Output Controls RATE SOUT_EN SCK_POL SFS_POL RDY_POL MUX_MODE PACKED FORMAT DEBUG_EN DEBUG_TAP SFS_MODE SDC_EN Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations Functional Description The CLC5903 block diagram is shown in Figure 2. The CLC5903 contains two identical digital down-conversion (DDC) circuits. Each DDC accepts an independently clocked 14-bit sample at up to 78MSPS, down converts from a selected carrier frequency to baseband, decimates the signal rate by a programmable factor ranging from 32 to 16384, provides channel filtering, and outputs quadrature symbols. A crossbar switch enables either of the two inputs or a test register to be routed to either DDC channel. Flexible channel filtering is provided by the two programmable decimating FIR filters. The final filter outputs can be converted to a 12-bit floating point format or standard two’s complement format. The output data is available at both serial and parallel ports. T he CLC5903 maintains over 100 dB of spurious free dynamic range and over 100 dB of out-of-band rejection. This allows considerable latitude in channel filter partitioning between the analog and digital domains. The frequencies, phase offsets, and phase dither of the two sine/cosine numerically controlled oscillators (NCOs) can be independently specified. Two sets of coefficient memories and a crossbar switch allow shared or independent filter coefficients and bandwidth for each channel. Both channels share the same decimation ratio and input/output formats. Each channel has its own AGC circuit for use with narrowband radio channels where most of the channel filtering precedes the ADC. The AGC closes the loop around the CLC5526 DVGA, compressing the dynamic range of the signal into the ADC. AGC gain compensation in the CLC5903 removes the DVGA gain steps at the output. The time alignment of this gain compensation circuit can be adjusted to support ADCs with different latencies. The AGC can be configured to operate continuously or set to a fixed gain step. The two AGC circuits operate independently but share the same programmed parameters and control signals. The chip receives configuration and control information over a microprocessor-compatible bus consisting of an 8-bit data I/O port, an 8-bit address port, a chip enable strobe, a read strobe, and a write strobe. The chip’s control registers (8 bits each) are memory mapped into the 8-bit address space of the control port. Page select bits allow access to the overlaid A and B set of FIR coefficients. JTAG boundary scan and on-chip diagnostic circuits are provided to simplify system debug and test. The CLC5903 supports 3.3V I/O even though the core logic voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail so they can be directly connected to 5V TTL inputs if desired. www.national.com 2 CLC5903 Absolute Maximum Ratings Positive IO Supply Voltage (VDDIO) Positive CoreSupply Voltage (VDD) Voltage on Any Input or Output Pin Input Current at Any Pin Package Input Current Package Dissipation at TA=25°C ESD Susceptibility Human Body Model Machine Model Soldering Temperature, Infrared, 10 seconds Storage Temperature -0.3V to 4.2V -0.3V to 2.4V -0.3V to VDDIO+0.5V ±25mA ±50mA 1W 2000V 200V 300°C -65°C to 150°C Operating Ratings Positive IO Supply Voltage (VDDIO) Positive Core Supply Voltage (VDD) Operating Temperature Range 3.3V ±10% 1.8V ±10% -40°C to +85°C Package Thermal Resistance Package 128 pin PQFP 128 pin FBGA θja 39°C/W 30°C/W θjc 20°C/W N/A Reliability Information Transistor Count 1.4 million N OTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Ordering Information Order Code CLC5903VLA CLC5903SM Temperature Range -40°C to +85°C -40°C to +85°C Description 128-pin PQFP (industrial temperature range) 128-pin FBGA (industrial temperature range) CLC5903 Electrical Characteristics (Note 1) DC Characteristics (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Symbol VIL VIH IOZ VOL VOH CIN Voltage input low Voltage input high Input current Voltage output low (IOL = 4mA/16mA, see Note 2) Voltage output high (IOH = -4mA/-16mA, see Note 2) Input capacitance 2.4 5.0 Parameter Min -0.5 2.3 Typ Max 0.7 VDDIO+0.5 20 0.4 Units V V uA V V pF AC Characteristics (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Symbol FCK SFDR SNR Parameter (CL=50pF) Clock (CKA|B) Frequency (Figure 7) Spurious Free Dynamic Range Signal to Noise Ratio Tuning Resolution Phase Resolution Min Typ Max 78 Units MHz dBFS dBFS Hz ° CK periods CK periods -100 -127 0.02 0.005 4 10 tMRA tMRIC MR Active Time (Figure 5) MR Inactive to first Control Port Access (Figure 5) 3 www.national.com CLC5903 AC Characteristics Symbol tMRSU tMRH tSISU tSIH tSIW tCKDC tRF tSU tHD tCKL tSTIW tGSTB tSFSV tOV tRDYW tRDYV tOENV tOENT tSELV tPOV tJPCO tJSCO tJPDZ tJSDZ tJPEN tJSEN tJSSU tJPSU tJSH tJPH tJCH tJCL JTAGFMAX tCSU tCHD (Continued) (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Parameter (CL=50pF) MR Setup Time to CKA|B (Figure 5) MR Hold Time to CKA|B (Figure 5) SI Setup Time to CKA|B (Figure 6) SI Hold Time from CKA|B (Figure 6) SI Pulse Width (Figure 6) CKA|B duty cycle (Figure 7) CKA|B r ise and fall times (VIL to VIH) (Figure 7) Input setup before CKA|B goes high (A|BIN) (Figure 7) Input hold time after CKA|B goes high (A|BIN) (Figure 7) Minimum time low for CK = CKA | CKB (Figure 8) A|BSTROBE Inactive Pulse Width (Figure 9) A|BGAIN setup before A|BSTROBE (Figure 9) SCK to SFS Valid (Note 3) (Figure 10) SCK to A|BOUT Valid (Note 4) (Figure 10) RDY Pulse Width (Figure 10) SCK to RDY valid (Figure 10) POUT_EN Active to POUT[15..0] Valid (Figure 11) POUT_EN Inactive to POUT[15..0] Tri-State (Figure 11) PSEL[2..0] to POUT[15..0] Valid (Figure 12) RDY to POUT[15..0] New Value Valid (Note 5) (Figure 13) Propagation Delay TCK to TDO (Figure 14) Propagation Delay TCK to Data Out (Figure 14) Disable Time TCK to TDO (Figure 14) Disable Time TCK to Data Out (Figure 14) Enable Time TCK to TDO (Figure 14) Enable Time TCK to Data Out (Figure 14) Setup Time Data to TCK (Figure 14) Setup Time TDI, TMS to TCK (Figure 14) Hold Time Data to TCK (Figure 14) Hold Time TCK to TDI, TMS (Figure 14) TCK Pulse Width High (Figure 14) TCK Pulse Width Low (Figure 14) TCK Maximum Frequency (Figure 14) Control Setup before the controlling signal goes low (Figure 15) Control hold after the controlling signal goes high (Figure 15) 5 5 0 0 10 10 45 45 50 40 10 -1 6 -1 -1 2 5 12 10 13 7 25 35 25 35 25 35 5 5 3 1 3.1 2 Min 6 2 6 2 4 40 Typ Max Units ns ns ns ns CK periods 60 2 % ns ns ns ns CK period ns ns ns CK periods ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns www.national.com 4 CLC5903 AC Characteristics Symbol tCSPW tCDLY tCZ IDD IDDIO Note 1: Note 2: Note 3: Note 4: Note 5: (Continued) (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Parameter (CL=50pF) Controlling strobe pulse width (Write) (Figure 15) Control output delay controlling signal low to D (Read) (Figure 15) Control tri-state delay after controlling signal high (Figure 15) Dynamic Supply Current (FCK =78MHz, N=48, SCK=39MHz) Dynamic Supply Current (FCK =78MHz, N=48, SCK=39MHz) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. All output pins provide 16mA output drive except TDO (pin 116) which provides 4mA output drive. tSFSV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1. tOV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1. tRDYV refers to the rising edge of RDY when RDY_POL=0 and the falling edge when RDY_POL=1. Min 30 Typ Max Units ns 30 20 120 65 200 100 ns ns mA mA CLC5903SM Pinout A1 AIN12 B1 AIN10 C1 AIN7 D1 AIN5 E1 AIN2 F1 VSS G1 VDD H1 BIN10 J1 BIN7 K1 BIN4 L1 BIN1 M1 NC A2 VDDIO B2 VSSIO C2 AIN11 D2 AIN8 E2 AIN1 F2 CKA G2 BIN13 H2 BIN11 J2 BIN8 K2 BIN2 L2 VSS M2 VDDIO A3 AGAIN1 B3 NC C3 NC D3 AIN13 E3 AIN6 F3 AIN3 G3 BIN12 H3 BIN9 J3 BIN6 K3 BIN0 L3 NC M3 BGAIN0 A4 SCAN_EN B4 TRST C4 ASTROB D4 AGAIN2 E4 AIN9 F4 AIN4 G4 AIN0 H4 BIN5 J4 BIN3 K4 CKB L4 BGAIN1 M4 MR A5 TCK B5 TMS C5 VSS D5 A6 VDD B6 TDO C6 TDI D6 A7 POUT_SEL1 B7 A8 VSSIO B8 A9 VDDIO B9 POUT4 C9 NC D9 POUT7 E9 POUT9 F9 SFS G9 RDY H9 D[2] A10 POUT3 B10 NC C10 VSSIO D10 VDDIO E10 VSSIO F10 POUT14 G10 BOUT H10 D[0] J10 VSSIO K10 NC L10 D[6] M10 VSSIO A11 NC B11 SCK_IN C11 POUT6 D11 POUT11 E11 POUT13 F11 VDD G11 VSSIO H11 SCK J11 D[1] K11 D[4] L11 NC M11 VDDIO A12 NC B12 POUT5 C12 POUT8 D12 POUT10 E12 POUT12 F12 POUT15 G12 AOUT H12 VDDIO J12 VSS K12 VDD L12 D[3] M12 D[5] POUT_SEL0 POUT_EN C7 POUT0 D7 POUT1 C8 POUT2 D8 VSS AGAIN0 POUT_SEL2 J5 BGAIN2 K5 BSTROB L5 NC M5 A[7] J6 SI K6 VSSIO L6 A[6] M6 VDD J7 NC K7 A[4] L7 A[5] M7 VSS J8 CE K8 A[1] L8 A[3] M8 A[2] J9 D[7] K9 RD L9 A[0] M9 WR Top View Figure 3. CLC5903SM FBGA Pinout 5 www.national.com CLC5903 CLC5903VLA Pinout CKB NC BIN[0] BIN[1] BIN[2] BIN[3] BIN[4] BIN[5] BIN[6] VSSIO BIN[7] BIN[8] BIN[9] BIN[10] BIN[11] BIN[12] (MSB) BIN[13] VDD CKA VSS AIN[0] AIN[1] AIN[2] AIN[3] AIN[4] AIN[5] AIN[6] VDDIO AIN[7] AIN[8] AIN[9] AIN[10] AIN[11] AIN[12] (MSB) AIN[13] VSSIO NC NC VDDIO BGAIN[2] BGAIN[1] BGAIN[0] BSTROBE NC MR SI VSSIO A[7] VDD A[6] VSS A[5] A[4] A[3] A[2] A[1] A[0] WR RD CE VSSIO D[7] D[6] VDDIO 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 CLC5903VLA Dual Digital Tuner / AGC (Top View) Pin Descriptions Signal MR AIN[13:0], BIN[13:0] www.national.com NC NC NC VSSIO D[5] D[4] D[3] D[2] D[1] VDD D[0] VSS RDY BOUT VDDIO SCK SFS AOUT VSSIO POUT[15] VDD POUT[14] POUT[13] POUT[12] VSSIO POUT[11] POUT[10] VDDIO POUT[9] POUT[8] POUT[7] POUT[6] POUT[5] VSSIO SCK_IN NC NC NC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 VDDIO AGAIN[2] AGAIN[1] AGAIN[0] ASTROBE NC SCAN_EN TRST VSS TCK TMS TDI TDO VDD POUT_SEL[0] POUT_SEL[1] POUT_SEL[2] POUT_EN VSSIO POUT[0] POUT[1] VDDIO POUT[2] POUT[3] POUT[4] VSS Figure 4. CLC5903VLA PQFP Pinout PQFP Pin 45 FBGA Pin M4 D3,A1,C2, B1,E4,D2, C1,E3,D1, F4,F3,E1, E2,G4; G2,G3,H2, H1,H3,J2, J1,J3,H4, K1,J4,K2, L1,K3 Description MASTER RESET, Active low Resets all registers within the chip. ASTROBE and BSTROBE are asserted during MR . 4:10,12:18, 22:28, 30:36 INPUT DATA, Active high 2’s complement input data. AIN[13] and BIN[13] are the MSBs. The data is clocked into the chip on the rising edge of the corresponding clock (CKA, CKB). The CLC595X connects directly to these input pins with no additional logic. Tie unused input bits low. 6 CLC5903 Pin Descriptions Signal (Continued) PQFP Pin FBGA Pin Description SERIAL OUTPUT DATA, Active high The 2’s complement serial output data is transmitted on these pins, MSB first. The output bits change on the rising edge of SCK (falling edge if SCK_POL=1) and should be captured on the falling edge of SCK (rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode AOUT=DEBUG[1], BOUT=DEBUG[0]. OUTPUT DATA TO DVGA, Active high 3 bit bus that sets the gain of the DVGA determined by the AGC circuit. DVGA STROBE, Active low Strobes the data into the DVGA. See Figure 9 and Figure 35 timing diagrams. SERIAL DATA CLOCK, Active high or low The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode outputs an appropriate clock for the debug data. If RATE=0 the input CK duty cycle will be reflected to SCK. SERIAL DATA CLOCK INPUT, Active high or low Data bits from a serial daisy-chain slave are clocked into a serial daisy-chain master on the falling edge of SCK_IN (rising if SCK_POL=1 on the slave). Tie low if not used. SERIAL FRAME STROBE, Active high or low The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a pulse at the beginning of each serial word (PACKED=0) or each serial word I/Q pair (PACKED=1). The polarity of this signal is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode SFS=DEBUG[2]. AOUT BOUT 82 78 G12 G10 AGAIN[2:0], BGAIN[2:0] ASTROBE, BSTROBE 125:127 40:42 124 43 D4,A3,D5 J5,L4,M3 C4 K5 SCK 80 H11 SCK_IN 99 B11 SFS 81 F9 POUT[15:0] 84,86:88, 90,91, 93:97,104: 106, 108,109 F12,F10, E11,E12, D11,D12, E9,C12,D9, C11,B12, B9,A10,C8, D7,C7 PARALLEL OUTPUT DATA, Active high The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0] pins select one of eight 16-bit output words. The POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug Mode POUT[15..0]=DEBUG[19..4]. POUT_SEL[2:0] 112:114 D6,A7,B7 PARALLEL OUTPUT DATA SELECT, Active high The 16-bit output word is selected with these 3 pins according to Table 2. Not used in Debug Mode. For a serial daisy-chain master, POUT_SEL[2:0] become inputs from the slave: POUT_SEL[2]=SFSSLAVE, POUT_SEL[1]=BOUTSLAVE, and POUT_SEL[0]=AOUTSLAVE. Tie low if not used. PARALLEL OUTPUT ENABLE. Active low This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debug Mode. Tie high if not used. READY FLAG, Active high or low The chip asserts this signal to identify the beginning of an output sample period (OSP). The polarity of this signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode RDY=DEBUG[3]. INPUT CLOCK. Active high The clock inputs to the chip. The corresponding AIN and BIN signals are clocked into the chip on the rising edge of this signal. CKA and CKB are OR’d together on chip to create the CK signal. SI is clocked into the chip on the rising edge of CK. Tie low if not used. SYNC IN. Active low The sync input to the chip. The decimation counters, dither, and NCO phase can be synchronized by SI. This sync is clocked into the chip on the rising edge of CK (CK = CKA + CKB). Tie this pin high if external sync is not required. All sample data is flushed by SI. To properly initialize the DVGA ASTROBE and BSTROBE are asserted during SI. POUT_EN 111 B8 RDY 77 G9 CKA, CKB 20, 38 F2 K4 SI 46 J6 7 www.national.com CLC5903 Pin Descriptions Signal (Continued) PQFP Pin 62,63, 69:73,75 FBGA Pin J9,L10, M12,K11, L12,H9, J11,H10 M5,L6,L7, K7,L8,M8, K8,L9 Description DATA BUS. Active high This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these pins. The chip will only drive output data on these pins when CE is low, RD is low, and WR is high. ADDRESS BUS. Active high These pins are used to address the control registers within the chip. Each of the control registers within the chip are assigned a unique address in a flat address space. A control register can be written to or read from by setting A[7:0] to the register’s address. READ ENABLE. Active low This pin enables the chip to output the contents of the selected register on the D[7:0] pins when CE is also low. WRITE ENABLE. Active low This pin enables the chip to write the value on the D[7:0] pins into the selected register when CE is also low. This pin can also function as RD/WR if RD is held low. CHIP ENABLE. Active low This control strobe enables the read or write operation. The contents of the register selected by A[7:0] will be output on D[7:0] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be loaded with the contents of D[7:0]. TEST DATA OUT. Active high TEST DATA IN. Active high with pull-up TEST MODE SELECT. Active high with pull-up TEST CLOCK. Active high. Tie low if JTAG is not used. TEST RESET. Active low with pull-up Asynchronous reset for TAP controller. Tie low or to MR if JTAG is not used. SCAN ENABLE. Active low with pull-up Enables access to internal scan registers. Tie high. Used for manufacturing test only! Core Ground. Quantity 5 in PQFP (6 in FBGA). Core Power, 1.8V. Quantity 5. D[7:0] A[7:0] 48,50, 52:57 RD 59 K9 WR 58 M9 CE 60 J8 TDO TDI TMS TCK TRST SCAN_EN VSS VDD 116 117 118 119 121 122 19,51,76, 103,120 21,49,74, 85,115 3,29,47,61, 68,83,89, 98,110 11,39,64, 79,92,107, 128 1,2,37,44, 65,66,67, 100,101, 102,123 B6 C6 B5 A5 B4 A4 C5,D8,F1, J12,L2,M7 A6,F11,G1, K12,M6 A8,B2,C10, E10,G11, J10,K6,M10 A2,A9,D10, H12,M2, M11 A11,A12, B3,B10,C3, C9,J7,K10, L11,L5,L3, M1 VSSIO I/O Ground. Quantity 9 (8 in FBGA). VDDIO I/O Power, 3.3V. Quantity 7 (6 in FBGA). NC No Connect. These pins should be left floating. Quantity 11 (12 in FBGA). www.national.com 8 CLC5903 Timing Diagrams CK tMRH tMRSU tMRA MR tMRIC RD or WR Figure 5. CLC5903 Master Reset Timing CK tSIH tSISU tSIW SI Figure 6. CLC5903 Synchronization Input (SI) Timing 1/FCK tCKDC CKA|B tHD tSU A|BIN Note: AIN relative to CKA, BIN relative to CKB tCKDC VIL tRF VIH Figure 7. CLC5903 ADC Input and Clock Timing tCKL CKA CKB CK Note: CK = CKA | CKB Figure 8. CLC5903 CKA vs. CKB Timing tSTIW A|BSTROBE tGSTB A|BGAIN[2..0] Figure 9. CLC5903 DVGA Interface Timing 9 www.national.com CLC5903 Timing Diagrams (Continued) SCK SCK_POL=0 SCK=CK/2 SCK SCK_POL=1 tSFSV tSFSV SFS SFS_POL=0 SFS SFS_POL=1 tOV A|BOUT lsb or undef Previous Q Output Word RDY RDY_POL=0 RDY RDY_POL=1 tRDYW tRDYV msb msb-1 I Output Word msb-2 tOV msb-3 Figure 10. CLC5903 Serial Port Timing POUT_EN tOENV POUT[15..0] tOENT Figure 11. CLC5903 Parallel Output Enable Timing POUT_SEL[2..0] tSELV POUT[15..0] n n+1 tSELV n+2 output (n) output (n+1) output (n+2) Figure 12. CLC5903 Parallel Output Select Timing RDY RDY_POL=0 RDY RDY_POL=1 POUT[15..0] tPOV old output new output Figure 13. CLC5903 Parallel Output Data Ready Timing www.national.com 10 CLC5903 TCK tJPCO tJPEN TDO tJCL TCK tJPSU TDI, TDS tJPH tJCH tJPDZ TCK tJSCO tJSEN D tJSDZ TCK tJSSU D tJSH Figure 14. CLC5903 JTAG Port Timing CE WR RD A[7:0] D[7:0] READ CYCLE; NORMAL MODE CE WR RD A[7:0] tCHD D[7:0] WRITE CYCLE; NORMAL MODE CE WR A[7:0] D[7:0] READ CYCLE; RD HELD LOW CE WR A[7:0] D[7:0] WRITE CYCLE; RD HELD LOW tCSU tCHD tCSPW tCSU tCDLY tCZ tCHD tCSU tCSPW tCHD tCSU tCDLY tCZ Figure 15. CLC5903 Control I/O Timing 11 www.national.com CLC5903 Detailed Description (Continued) Detailed Description Control Interface The CLC5903 is configured by writing control information into 148 control registers within the chip. The contents of these control registers and how to use them are described under Control Register Addresses and Defaults on page 21. The registers are written to or read from using the D[7:0], A[7:0] , C E , R D and W R pins (see Table for pin descriptions). This interface is designed to allow the CLC5903 to appear to an external processor as a memory mapped peripheral. See Figure 15 for details. The control interface is asynchronous with respect to the system clock, CK (CK = CKA + CKB). This allows the registers to be written or read at any time. In some cases this might cause an invalid operation since the interface is not internally synchronized. In order to assure correct operation, SI must be asserted after the control registers are written. The D [7:0] , A [7:0] , W R , R D a nd C E p ins should not be driven above the positive supply voltage. Master Reset A master reset pin, MR, is provided to initialize the CLC5903 to a known condition and should be strobed after power up. This signal will clear all sample data and all user programmed data (filter coefficients and AGC settings). All outputs will be disabled (tri-stated). ASTROBE and BSTROBE will be asserted to initialize the DVGA values. Control Register Addresses and Defaults on page 21 describes the control register default values. Synchronizing Multiple CLC5903 Chips A system containing two or more CLC5903 chips will need to be synchronized if coherent operation is desired. To synchronize multiple CLC5903 chips, connect all of the sync input pins together so they can be driven by a common sync strobe. Synchronization occurs on the rising edge of CKA|B when S I goes back high. When S I i s asserted all sample data will be flushed immediately, the numerically controlled oscillator (NCO) phase offset will be initialized, the NCO dither generators will be reset, and the CIC decimation ratio will be initialized. Only the configuration data loaded into the microprocessor interface remains unaffected. SI may be held low as long as desired after a minimum of 4 CK periods. Input Source The input crossbar switch allows either AIN , B IN, or a test register to be routed to the channel A or channel B AGC/ DDC. The AGC outputs, A GAIN a nd B GAIN , are not switched. If AIN and BIN are exchanged the AGC loop will be open and the AGCs will not function properly. AIN and BIN should meet the timing requirements shown in Figure 7. Selecting the test register as the input source allows the AGC or DDC operation to be verified with a known input. See the test and diagnostics section for further discussion. Down Converters A detailed block diagram of each DDC channel is shown in Figure 16. Each down converter uses a complex NCO and mixer to quadrature downconvert a signal to baseband. The “FLOAT TO FIXED CONVERTER” treats the 15-bit mixer output as a mantissa and the AGC output, EXP, as a 3-bit exponent. It performs a bit shift on the data based on the value of EXP. This bit shifting is used to expand the compressed dynamic range resulting from the DVGA operation. The DVGA gain is adjusted in 6dB steps which are equivalent to each digital bit shift. Digitally compensating for the DVGA gain steps in the CLC5903 causes the DDC output to be linear with respect to the DVGA input. The AGC operation will be completely transparent at the CLC5903 output. The exponent (EXP) can be forced to its maximum value by setting the EXP_INH bit. If x in ( n ) is the DDC input, the signal after the “FLOAT TO FIXED CONVERTER” is x 3 ( n ) = x in ( n ) • cos ( ω n ) • 2 EXP (1) for the I component. Changing the ‘cos’ to ‘sin’ in this equation will provide the Q component. The “FLOAT TO FIXED CONVERTER” circuit expands the dynamic range compression performed by the DVGA. Signals from this point onward extend across the full dynamic range of the signals applied to the DVGA input. This allows the AGC to operate continuously through a burst without producing artifacts in the signal due to the settling response of the decimation filters after a 6dB DVGA gain adjustment. For example, if the DVGA input signal were to increase causing the ADC output level to cross the AGC threshold level, the gain of the DVGA would change by -6dB. The 6dB step is allowed to propagate through the ADC and mixers and is compensated out just before the filtering. The accuracy of EXP_INH SCALE 3 EXP F1 FILTER DECIMATE BY 2 CIC FILTER DECIMATE BY 8 TO 2K SAT & ROUND SAT & ROUND F2 FILTER DECIMATE BY 2 OR 4 EXPONENT FLOAT TO FIXED CONVERTER SHIFT UP SHIFT UP x in ( n ) ROUND MUXA 14 DEC EXP (from AGC) F2_COEF DEC_BY_4 F1_COEF GAIN_A 15 22 21 21 I TO OUTPUT CIRCUIT Data @ FCK = FS (FSAMPLE) 17 17 COS 15 22 21 21 FREQ_A PHASE_A SIN x3 ( n ) Data @ FCK/N Data @ FCK/N*2 Data @ FCK/N*2*F2_DEC = OFS (Output FSAMPLE) NCO N = DEC + 1 Figure 16. CLC5903 Down Converter, Channel A (Channel B is identical) www.national.com 12 SAT Q CLC5903 Detailed Description (Continued) the compensation is dependent on timing and the accuracy of the DVGA gain step. The CLC5903 allows the timing of the gain compensation to be adjusted in the EXT_DELAY register. This operating mode requires 21 bits (14-bit ADC output + 7-bit shift) to represent the full linear dynamic range of the signal. The output word must be set to either 24-bit or 32-bit to take advantage of the entire dynamic range available. The CLC5903 can also be configured to output a floating point format with up to 138dB of numerical resolution using only 12 output bits. The “SHIFT UP” circuit will be discussed in the Four Stage CIC filter section on page 14. A 4-stage cascaded-integrator-comb (CIC) filter and a two-stage decimate by 4 or 8 finite impulse response (FIR) filter are used to lowpass filter and isolate the desired signal. The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 2048 (decimation ratio). The CIC outputs are followed by a gain stage and then followed by a two-stage decimate by 4 or 8 filter. The gain circuit allows the user to boost the gain of weak signals by up to 42 dB in 6 dB steps. It also rounds the signal to 21 bits and saturates at plus or minus full scale. The first stage of the two stage filter is a 21-tap, symmetric decimate by 2 FIR filter (F1) with programmable 16 bit tap weights. The coefficients of the first 11 taps are downloaded to the chip as 16 bit words. Since the filter is a symmetric configuration only the first 11 coefficients must be loaded. The F1 section on page 15 provides a generic set of coefficients that compensate for the rolloff of the CIC filter and provide a passband flat to 0.01dB with 70 dB of out of band rejection. A second coefficient set is provided that has a narrower output passband and greater out-of-band rejection. The second set of coefficients is ideal for systems such as GSM where far-image rejection is more important than adjacent channel rejection. The second stage is a 63 tap decimate by 2 or 4 programmable FIR filter (F2) also with 16 bit tap weights. Filter coeffi- cients for a flat response from -0.4FS to +0.4FS of the output sample rate with 80dB of out of band rejection are provided in the F2 section. A second set of F2 coefficients is also provided to enhance performance for GSM systems. The user can also design and download their own final filter to customize the channel’s spectral response. Typical uses of programmable filter F2 include matched (root-raised cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63 tap symmetrical filter is downloaded into the chip as 32 words, 16 bits each. Saturation to plus or minus full scale is performed at the output of F1 and F2 to clip the signal rather than allow it to roll over. The CLC5903 provides two sets of coefficient memory for both F1 and F2. These coefficient memories can be independently routed to channel A, channel B, or both channel A and B with a crossbar switch. The coefficients can be switched on the fly but some time will be required before valid output data is available. The Numerically Controlled Oscillator The tuning frequency of each down converter is specified as a 32 bit word (.02Hz resolution at CK=52MHz) and the phase offset is specified as a 16 bit word (.005°). These two parameters are applied to the Numerically Controlled Oscillator (NCO) circuit to generate sine and cosine signals used by the digital mixer. The NCOs can be synchronized with NCOs on other chips via the sync pin SI. This allows multiple down converter outputs to be coherently combined, each with a unique phase and amplitude. The tuning frequency is set by loading the FREQ register according to the formula FREQ = 232F/FCK, where F is the desired tuning frequency and F CK i s the chip’s clock rate. FREQ is a 2’s complement word. The range for F is from -FCK/2 to +FCK(1-2-31)/2. In some cases the sampling process causes the order of the I and Q components to be reversed. Should this occur simply invert the polarity of the tuning frequency F. Complex NCO Output Complex NCO Output 0 0 -20 -20 -40 -40 Magnitude (dB) -60 Magnitude (dB) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -60 -80 -80 -100 -100 -120 -120 -140 -140 -160 -0.5 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Frequency Normalized to FS Frequency Normalized to FS (a) Before Phase Dithering (b) After Phase Dithering Figure 17. Example of NCO spurs due to phase truncation 13 www.national.com CLC5903 Detailed Description (Continued) The 2’s complement format represents full-scale negative as 10000000 and full-scale positive as 01111111 for an 8-bit example. The 16 bit phase offset is set by loading the PHASE register according to the formula PHASE = 2 16P/2π, where P is the desired phase in radians ranging between 0 and 2π. PHASE is an unsigned 16-bit number. P ranges from 0 to 2π(1-2-16). Phase dithering can be enabled to reduce the spurious signals created by the NCO due to phase truncation. This truncation is unavoidable since the frequency resolution is much finer than the phase resolution. With dither enabled, spurs due to phase truncation are below -100 dBc for all frequencies and phase offsets. Each NCO has its own dither source and the initial state of one is maximally offset with respect to the other so that they are effectively uncorrelated. The phase dither sources are on by default. They are independently controlled by the DITH_A and DITH_B bits. The amplitude resolution of the ROM creates a worst-case spur amplitude of -101dBc rendering amplitude dither unnecessary. The spectrum plots in Figure 17 show the effectiveness of phase dither in reducing NCO spurs due to phase truncation for a worst-case example (just below F S/8). With dither off, the spur is at -86.4dBFS. With dither on, the spur is below -125dBFS, disappearing into the noise floor. This spur is spread into the noise floor which results in an SNR of -83.6dBFS. The channel filter’s processing gain will further improve the SNR. Figure 18 shows the spur levels as the tuning frequency is scanned over a narrow portion of the frequency range. The spurs are again a result of phase quantization but their locations move about as the frequency scan progresses. As before, the peak spur level drops when dithering is enabled. When dither is enabled and the fundamental frequency is exactly at FS/8, the worst-case spur due to amplitude quantization can be observed at -101dBc in Figure 19. Four Stage CIC Filter The mixer outputs are decimated by a factor of N in a four stage CIC filter. N is programmable to any integer between 8 and 2048. Decimation is programmed in the DEC register where DEC = N - 1. The programmable decimation allows the chip’s usable output bandwidth to range from about 2.6kHz to 1.3MHz when the input data rate (which is equal to the chip’s clock rate, FCK) is 52 MHz. For the maximum sample rate of 78MHz, the CLC5903’s output bandwidth will range from about 4.76kHz to 1.95MHz. A block diagram of the CIC filter is shown in Figure 20. The CIC filter is primarily used to decimate the high-rate incoming data while providing a rough lowpass characteristic. The lowpass filter will have a sin(x)/x response (similar to the AGC’s CIC shown in Figure 36 on page 24) where the first null is at FS/N. SCALE 0 Complex NCO Output Phase Dither Disabled N C O f r e q u e n c y sw e p t -20 -40 Magnitude (dB) -60 -80 -100 -120 -140 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Frequency Normalized to FS Figure 18. NCO Spurs due to Phase Quantization Complex NCO Output Phase Dither Enabled 0 -20 -40 Magnitude (dB) -60 -80 -100 -120 -140 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Frequency Normalized to FS Figure 19. Worst Case Amplitude Spur, NCO at FS/8 The CIC filter has a gain equal to N 4 ( filter decimation^4) which must be compensated for in the “SHIFT UP” circuit shown in Figure 20 as well as Figure 16. This circuit has a gain equal to 2(SCALE-44), where SCALE ranges from 0 to 40. This circuit divides the input signal by 2 44 providing maxi- DATA IN DECIMATE BY FACTOR OF N SHIFT UP 22 66 DATA OUT Data @ FCK/N Data @ FCK = FS (FSAMPLE) 22-bit input to SHIFT_UP is aligned at the bottom of the 66-bit path when SCALE=0. N = DEC + 1 Figure 20. Four-stage decimate by N CIC filter www.national.com 14 CLC5903 Detailed Description (Continued) mum headroom through the CIC filter. For optimal noise performance the SCALE value is set to increase this level until the CIC filter is just below the point of distortion. A value is normally calculated and loaded for SCALE such that GAIN SHIFTUP ⋅ GAIN CIC ≤ 1 . The actual gain of the CIC filter will only be unity for power-of-two decimation values. In other cases the gain will be somewhat less than unity. Channel Gain The gain of each channel can be boosted up to 42 dB by shifting the output of the CIC filter up by 0 to 7 bits prior to rounding it to 21 bits. For channel A, the gain of this stage is: , where GAIN_A ranges from 0 to 7. OverGAIN = 2 flow due to the GAIN circuit is saturated (clipped) at plus or minus full scale. Each channel can be given its own GAIN setting. First Programmable FIR Filter (F1) The CIC/GAIN outputs are followed by two stages of filtering. The first stage is a 21 tap decimate-by-2 symmetric FIR filter with programmable coefficients. Typically, this filter compensates for a slight droop induced by the CIC filter while removing undesired alias images above Nyquist. In addition, it often provides stopband assistance to F2 when deep stop bands are required. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 21 coefficients is equal to 216. If the sum is not 216, then F1 will introduce a gain equal to (sum of coefficients)/216. The 21 coefficients are identified as coefficients h 1 ( n ), n = 0, …, 20 where h 1 ( 10 ) is the center tap. The coefficients are symmetric, so only the first 11 are loaded into the chip. Two example sets of coefficients are provided here. The first set of coefficients, referred to as the standard set (STD), compensates for the droop of the CIC filter providing a passband which is flat (0.01 dB ripple) over 95% of the final output bandwidth with 70dB of out-of-band rejection (see Figure 21). The filter has a gain of 0.999 and is symmetric with the following 11 unique taps (1|21, 2|20, ..., 10|12, 11): 29, -85, -308, -56, 1068, 1405, -2056, -6009, 1303, 21121, 32703 Frequency Response of F1 Using STD Set 0 −10 −20 −30 Magnitude (dB) The second set of coefficients (GSM set) are intended for applications that need deeper stop bands or need oversampled outputs. These requirements are common in cellular systems where out of band rejection requirements can exceed 100dB (see Figure 22). They are useful for wideband radio architectures where the channelization is done after the ADC. These filter coefficients introduce a gain of 0.984 and are: -49, -340, -1008, -1617, -1269, 425, 3027, 6030, 9115, 11620, 12606 Frequency Response of F1 Using GSM Set 0 GAIN_A −20 Magnitude (dB) −40 −60 −80 −100 −120 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 Figure 22. F1 GSM frequency response Second Programmable FIR Filter (F2) The second stage decimate by two or four filter also uses externally downloaded filter coefficients. F2 determines the final channel filter response. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 63 coefficients is equal to 216. If the sum is not 216, then the F2 will introduce a gain equal to (sum of coefficients)/216. The 63 coefficients are identified as h 2 ( n ) , n = 0 ,… ,62 where h 2 ( 31 ) is the center tap. The coefficients are symmetric, so only the first 32 are loaded into the chip. An example filter (STD F2 coefficients, see Figure 23) with 80dB out-of-band rejection, gain of 1.00, and 0.03 dB peak to peak passband ripple is created by this set of 32 unique coefficients: -14, -20, 19, 73, 43, -70, -82, 84, 171, -49, -269, -34, 374, 192, -449, -430, 460,751, -357, -1144, 81, 1581, 443, -2026, -1337, 2437, 2886, -2770, -6127, 2987, 20544, 29647 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 A second set of F2 coefficients (GSM set, see Figure 24) suitable for meeting the stringent wideband GSM requirements with a gain of 0.999 are: -536, -986, 42, 962, 869, 225, 141, 93, -280, -708, -774, -579, -384, -79, 536, 1056, 1152, 1067, 789, 32, -935, -1668, -2104, -2137, -1444, 71, 2130, 4450, 6884, 9053, 10413, 10832 Figure 21. F1 STD frequency response The filter coefficients of both filters can be used to tailor the spectral response to the user’s needs. For example, the first can be loaded with the standard set to provide a flat 15 www.national.com CLC5903 Detailed Description (Continued) 0 Frequency Response of F2 Using STD Set 0 −10 −20 −30 Magnitude (dB) Magnitude (dB) Combined Frequency Response of CIC/F1/F2 Using STD Set FCK = 52MHz Decimation = 192 OFS = 270.83kHz −50 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 −100 −150 0 500 1000 1500 2000 Frequency (KHz) 2500 3000 Figure 25. CIC, F1, & F2 STD frequency response Combined Frequency Response of CIC/F1/F2 Using STD Set 0.1 Figure 23. F2 STD frequency response Frequency Response of F2 Using GSM Set 5 0 −5 Magnitude (dB) 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −10 Magnitude (dB) −15 −20 −25 −30 −35 −40 −0.1 −45 −50 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 0 50 100 150 Frequency (KHz) 200 250 Figure 26. CIC, F1, & F2 STD Passband Flatness Combined Frequency Response of CIC/F1/F2 Using GSM Set 0 Figure 24. F2 GSM frequency response response through to the second filter. The latter can then be programmed as a Nyquist (typically a root-raised-cosine) filter for matched filtering of digital data. The complete channel filter response for standard coefficients is shown in Figure 25. Passband flatness is shown in Figure 26. The complete filter response for GSM coefficients is shown in Figure 27. GSM Passband flatness is shown in Figure 28. The mask shown in Figure 27 is derived from the ETSI GSM 5.05 specifications for a normal Basestation Transceiver (BTS). For interferers, 9dB was added to the carrier to interference (C/I) ratios. For blockers, 9dB was added to the difference between the blocker level and 3dB above the reference sensitivity level. Channel Bandwidth vs. Sample Rate When the CLC5903 is used for GSM systems, a bandwidth of about 200kHz is desired. With a sample rate of 52MHz, the total decimation of 192 provides the desired 270.833kHz output sample rate. This output sample rate in combination with the FIR filter coefficients create the desired channel bandwidth. If the sample rate is increased to 65MHz, the decimation must also be increased to 65MHz/270.833kHz or 240. This new decimation rate will maintain the same output −20 FCK = 52MHz Decimation = 192 OFS = 270.83kHz Magnitude (dB) −40 −60 −80 −100 0 500 1000 1500 2000 Frequency (KHz) 2500 3000 Figure 27. CIC, F1, & F2 GSM frequency response bandwidth. At 78MHz, the decimation must increase again to 78MHz/270.833kHz or 288. The output bandwidth may only be changed in relation to the output sample rate by creating a new set of FIR filter coefficients. As the filter bandwidth www.national.com 16 CLC5903 Output Modes (Continued) Combined Frequency Response of CIC/F1/F2 Using GSM Set 1 6dB conversion loss in the mixer. For full-scale square wave 1 inputs the -- should be set to 1 to prevent signal distortion. 2 Data Latency and Group Delay The CLC5903 latency calculation assumes that the FIR filter latency will be equal to the time required for data to propagate through one half of the taps. The CIC filter provides 4N equivalent taps where N is the CIC decimation ratio. F1 and F2 provide 21 and 63 taps respectively. When these filters are reflected back to the input rate, the effective taps are increased by decimation. This results in a total of 298N taps when the F2 decimation is 2 and 550N taps when the F2 decimation is 4. The latency is then 149N CK periods when the F2 decimation is 2 and 275N CK periods when the F2 decimation is 4. 0.5 0 Magnitude (dB) −0.5 −1 −1.5 −2 0 20 40 60 Frequency (KHz) 80 100 The CLC5903 filters are linear phase filters so the group delay remains constant. Figure 28. CIC, F1, & F2 GSM Passband Flatness decreases relative to the output sample rate, the CIC droop compensation performed by F1 may no longer be required. Overall Channel Gain The overall gain of the chip is a function of the amount of decimation (N), the settings of the “SHIFT UP” circuit (SCALE), the GAIN setting, the sum of the F1 coefficients, and the sum of the F2 coefficients. The overall gain is shown below in Equation 2. 4 1 G DDC = -- ( DEC + 1 ) 2 Output Modes After processing by the DDC, the data is then formatted for output. All output data is two’s complement. The serial outputs power up in a tri-state condition and must be enabled when the chip is configured. Parallel outputs are enabled by the POUT_EN pin. Output formats include truncation to 8 or 32 bits, rounding to 16 or 24 bits, and a 12-bit floating point format (4-bit exponent, 8-bit mantissa, 138dB numeric range). This function is performed in the OUTPUT CIRCUIT shown in Figure 29. (2) POLARITY INVERT RDY_POL, SCK_POL, SFS_POL CK DIVIDE BY RATE RDY SCK SFS ⋅2 ⋅2 [ SCALE – 44 – AGAIN ⋅ ( 1 – EXP _ INH ) ] GAIN Where: 21 NUMBER FORMAT CONTROL SERIALIZER AND TDM FORMATTER CH B ⋅ G F 1 ⋅ GF 2 AOUT CH A ∑ h1 ( i ) =1 G F 1 = i---------------------16 2 BOUT SCK_IN (3) FORMAT 63 ∑ h2 ( i ) =1 G F 2 = i---------------------16 2 (4) MUX 16 MUX_MODE PACKED SFS_MODE and: POUT[15..0] It is assumed that the DDC output words are treated as fractional 2’s complement words. The numerators of G F 1 and G F 2 equal the sums of the impulse response coefficients of F1 and F2, respectively. For the STD and GSM sets, G F 1 and G F 2 are nearly equal to unity. Observe that the AGAIN term in (2) is cancelled by the DVGA operation so that the entire gain of the DRCS is independent of the DVGA setting 1 when EXP_INH=0. The -- appearing in (2) is the result of the 2 3 POUT_SEL[2..0] POUT_EN Figure 29. CLC5903 output circuit The channel outputs are accessible through serial output pins and a 16-bit parallel output port. The R DY pin is provided to notify the user that a new output sample period (OSP) has begun. OSP refers to the interval between output samples at the decimated output rate. For example, if the input rate (and clock rate) is 52 MHz and the overall decimation factor is 192 (N=48, F2 decimation=2) the OSP will be 3.69 microseconds which corresponds to an output sample 17 www.national.com CLC5903 Output Modes (Continued) clock stops and data is zero after transfers are complete SCK SFS AOUT I15 I14 I1 I0 Q15 Q14 Q1 Q0 (a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD clock stops and data is zero after transfers are complete SCK SFS AOUT I15 I14 I1 I0 Q15 Q14 Q1 Q0 (b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER RDY SFS A|BOUT SFS AOUT SFS AOUT leading edge of RDY aligns with leading edge of SFS Output Sample Period (OSP) RDY is 2 CK periods wide IA QA MUX_MODE=0, SFS_MODE=0|1 IA QA IA QA IB QB MUX_MODE=1, SFS_MODE=0 IA QA IB QB IA QA IB QB MUX_MODE=1, SFS_MODE=1 IA QA IB QB (c) ONE OR TWO CHANNEL MUX AND SFS MODES (PACKED MODE IS ON) clock stops and data is zero after transfers are complete SCK SFS AOUT mI7 mI6 mI0 eI3 eI2 eI0 eQ3 eQ0 mQ7 mQ0 (d) FLOATING POINT FORMAT Figure 30. Serial output formats. Refer to Figure 10 for detailed timing information rate of 270.833kHz. An OSP starts when a sample is ready and stops when the next one is ready. Serial Outputs The CLC5903 provides a serial clock (SCK), a frame strobe (SFS) and two data lines (AOUT and BOUT) to output serial data. The MUX_MODE control register specifies whether the two channel outputs are transmitted on two separate serial pins, or multiplexed onto one pin in a time division multiplexed (TDM) format. Separate output pins are not provided for the I and Q halves of complex data. The I and Q outputs are always multiplexed onto the same serial pin. The I-component is output first, followed by the Q-component. By setting the PACKED mode bit to ‘1’ a complex pair may be treated as a single double-wide word. The R DY s ignal is used to identify the first word of a complex pair of the TDM formatted output when the SFS_MODE bit is set to ‘0’. Setting SFS_MODE to ‘1’ causes the CLC5903 to output a single SFS pulse for each output period. This SFS pulse will be coincident with RDY and only a single SCK period wide. The TDM modes are summarized in Table 1. SERIAL OUTPUTS SFS_MODE MUX_MODE AOUT 0 0 1 0 1 1 OUTA, OUTB LOW OUTA, OUTB OUTA LOW OUTB OUTA BOUT OUTB Table 1. TDM Modes The serial outputs use the format shown in Figure 30. Figure 30(a) shows the standard output mode (the PACKED mode bit is low). The chip clocks the frame and data out of the chip on the rising edge of SCK (or falling edge if the SCK_POL bit in the input control register is set high). Data should be captured on the falling edge of SCK (rising if SCK_POL=1). The www.national.com 18 CLC5903 AGC (Continued) AOUT BOUT SFS SCK POUT_SEL[0] POUT_SEL[1] POUT_SEL[2] SCK_IN AOUT SCK To DSP SFS RDY ParallelOutput[15..0] ParallelOutputEnable ParallelSelect[2..0] Slave CLC5903 SDC_EN=0 MUX_MODE=0 PACKED=1 12 12 Master CLC5903 SDC_EN=1 MUX_MODE=0 12 SCKMASTER=2*SCKSLAVE ADCs and DVGAs ADCs and DVGAs Figure 31. Serial Daisy-Chain Mode chip sends the I data first by setting S FS h igh (or low if SFS_POL in the input control register is set high) for one clock cycle, and then transmitting the data, MSB first, on as many SCK cycles as are necessary. Without a pause, the Q data is transferred next as shown in Figure 30(a). If the PACKED control bit is high, then the I and Q components are sent as a double length word with only one S FS strobe as shown in Figure 30(b). If both channels are multiplexed out the same serial pin, then the subsequent I/Q channel words will be transmitted immediately following the first I/Q pair as shown in Figure 30(c). Figure 30(c) also shows how SFS_MODE=1 allows the SFS signal to be used to identify the I and Q channels in the TDM serial transmission. The serial output rate is programmed by the RATE register to CK divided by 1, 2, 4, 8, 16, or 32. The serial interface will not work properly if the programmed rate of SCK is insufficient to clock out all the bits in one OSP. Serial Port Daisy-Chain Mode Two CLC5903s can be connected in series so that a single DSP serial port can receive four DDC output channels. This mode is enabled by setting the SDC_EN bit to ‘1’ on the serial daisy-chan (SDC) master. The SDC master is the CLC5903 which is connected to the DSP while the SDC slave’s serial output drives the master. The SDC master’s RATE register must be set so that its SCK rate is twice that of the SDC slave, the SDC master must have MUX_MODE=1, the SDC slave must have MUX_MODE=0 and PACKED=1, and both chips must come out of a MR or SI event within four CK periods of each other. In this configuration, the master’s serial output data is shifted out to the DSP then the slave’s serial data is shifted out. All the serial output data will be muxed onto the master’s AOUT pin as shown in Figure 31. Serial Port Output Number Formats Several numeric formats are selectable using the FORMAT control register. The I/Q samples can be rounded to 16 or 24 bits, or truncated to 8 bits. The packed mode works as described above for these fixed point formats. A floating point format with 138dB of dynamic range in 12 bits is also provided. The mantissa (m) is 8 bits and the exponent (e) is 4 bits. The MSB of each segment is transmitted first. When this mode is selected, the I/Q samples are packed regardless of the state of MUX_MODE, and the data is sent as mI/eI/eQ/ mQ which allows the two exponents to form an 8-bit word. This is shown in Figure 30(d). For all formats, once the defined length of the word is complete, SCK stops toggling. Parallel Outputs Output data from the channels can also be taken from a 16-bit pa ra llel por t. A 3-bit wo rd a pplie d to th e POUT_SEL[2:0] pins determines which 16-bit segment is multiplexed to the parallel port. Table 2 defines this mapping. To allow for bussing of multiple chips, the parallel port is tri-stated unless POUT_EN is low. The RDY signal indicates the start of an OSP and that new data is ready at the parallel output. The user has one OSP to cycle through whichever registers are needed. The RATE register must be set so that each OSP is at least 5 SCK periods. Parallel Port Output Numeric Formats The I/Q samples can be rounded to 16 or 24 bits or the full 32 bit word can be read. By setting the word size to 32 bits it is possible to read out the top 16 bits and only observe the top 8 bits if desired. Additionally, the output samples can be formatted as floating point numbers with an 8-bit mantissa and a 4 bit exponent. For the fixed-point formats, the valid bits are justified into the MSBs of the registers of Table 2 and POUT_SEL 0 1 2 3 4 5 6 7 Normal Register Contents IA upper 16 bits IA lower 16 bits QA upper 16 bits QA lower 16 bits IB upper 16 bits IB lower 16 bits QB upper 16 bits QB lower 16 bits 12 4 4 Floating Point Register Contents 0000/eIA/mIA 0x0000 0000/eQA/mQA 0x0000 0000/eIB/mIB 0x0000 0000/eQB/mQB 0x0000 Table 2. Register Selection for Parallel Output all other bits are set to zero. For the floating point format, the valid bits are placed in the upper 16 bits of the appropriate channel register using the format 0000/eI/mI for the I samples. AGC The CLC5903 AGC processor monitors the output level of the ADC and servos it to the desired setpoint. The ADC input is controlled by the DVGA to maintain the proper setpoint 19 www.national.com CLC5903 Test and Diagnostics (Continued) level. DVGA operation results in a compression of the signal through the ADC. The DVGA signal compression is reversed in the CLC5903 to provide > 120dB of linear dynamic range. This is illustrated in Figure 32. after programming the desired gain in the AGC_IC_A and AGC_IC_B registers. Allowing the AGC to free run should be appropriate for most applications. Programming the AGC_COMB_ORD register allows the AGC power detector bandwidth to be reduced if desired. This will tend to improve the power detector’s ability to reject the signal carrier frequency and reduce overall AGC activity. Figure 36 on page 24 shows the power detector response. Diversity Receiver Chipset Full Scale C O pu ut t Power Management The CLC5903 can be placed in a low power (static) state by stopping the input clock. To prevent this from placing the CLC5903 into unexpected states, the SI pin of the CLC5903 should be asserted prior to disabling the input clock and held asserted until the input clock has returned to a stable condition. Output Power A O GC ve O rT p hi era s te Rs an ge D D ADC Full Scale AGC Threshold Test and Diagnostics The CLC5903 supports IEEE 1149.1 compliant JTAG Boundary Scan for the I/O's. The following pins are used: TRST TMS TDI TDO TCK Instruction BYPASS EXTEST IDCODE SAMPLE/PRELOAD HIGHZ (test reset) (test mode select) (test data in) (test data out) (test clock) Description Connects TDI directly to TDO Drives the ‘extest’ TAP controller output Connects the 32-bit ID register to TDO Drives the ‘samp_load’ TAP controller output Tri-states the outputs ADC Output Deadband+Hysteresis Input Power Figure 32. Output Gain Scaling vs. Input Signal In order to use the AGC, the DRCS Control Panel software may be used to calculate the programmable parameters. To generate these parameters, only the desired setpoint, deadband+hysteresis, and loop time constant need to be supplied. All subsequent calculations are performed by the software. Complete details of the AGC operation are provided in an appendix but are not required reading. The following JTAG instructions are supported: 6dB DVGA Output Power Deadband The JTAG Boundary Scan can be used to verify printed circuit board continuity at the system level. The user is able to program a value into TEST_REG and substitute this for the normal channel inputs from the A IN/ BIN pins by selecting it with the crossbar. With the NCO frequency set to zero this allows the DDCs and the output interface of the chip to be verified. Also, the AGC loop can be opened by setting AGC_HOLD_IC high and setting the gain of the DVGA by programming the appropriate value into the AGC_IC_A/B register. Real-time access to the following signals is provided by configuring the control interface debug register: • • • • NCO sine and cosine outputs data after round following mixers data before F1 and F2 data after the CIC filter within the AGC Reference Setpoint 6dB Hysteresis=Deadband-6dB DVGA Input Power Figure 33. AGC Setup. AGC setpoint and deadband+hysteresis are illustrated in Figure 33. The loop time constant is a measure of how fast the loop will track a changing signal. Values down to approximately 1.0 microsecond will be stable with the second order LC noise filter. Since the DVGA operates with 6dB steps the deadband should always be greater than 6dB to prevent oscillation. An increased deadband value will reduce the amount of AGC operation. A decreased deadband value will increase the amount of AGC operation but will hold the ADC output closer to the setpoint. The threshold should be set so that transients do not cause sustained overrange at the ADC inputs. The threshold setting can also be used to set the ADC input near its optimal performance level. The AGC will free run when AGC_HOLD_IC is set to ‘0’. It may be set to a fixed gain by setting AGC_HOLD_IC to ‘1’ The access points are multiplexed to a 20-bit parallel output port which is created from signal pins POUT[15:0], AOUT, BOUT, SFS, and RDY according to the table below: Normal Mode Pin POUT[15:0] RDY SFS AOUT BOUT Debug Mode Pin DEBUG[19..4] DEBUG[3] DEBUG[2] DEBUG[1] DEBUG[0] www.national.com 20 CLC5903 SCK will be set to the proper strobe rate for each debug tap point. POUT_EN and P SEL[2..0] have no effect in Debug Mode. The outputs are turned on when the Debug Mode bit is set. Normal serial outputs are also disabled. writing using the control bus pins (CE, RD, WR, A[7:0], and D[7:0]) described in the Control Interface section. The two sets of FIR coefficients are overlaid at the same memory address. Use the PAGE_SEL registers to access the second set of coefficients. The register names and descriptions are listed below under Control Register Addresses and Defaults o n page 21. A quick reference table is provided in the Condensed CLC5903 Address Map on page 22. Control Registers The chip is configured and controlled through the use of 8-bit control registers. These registers are accessed for reading or Control Register Addresses and Defaults Register Name DEC Width 11b Type R/W Defaulta 7 Addr 0(LSBs) 1(MSBs) 1 Bit 7:0 2:0 4 Description CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned integer. This affects both channels. Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both channels. CIC SCALE parameter. Format is an unsigned integer representing the number of left bit shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects both channels. Value of left bit shift prior to F1 for channel A. Value of left bit shift prior to F1 for channel B. Determines rate of serial output clock. The output rate is FCK/(RATE+1). Unsigned integer values of 0, 1, 3, 7, 15, and 31 are allowed. Enables the serial output pins AOUT, BOUT, SCK, and SFS. 0=Tristate. 1=Enabled. Determines polarity of the SCK output. 0=AOUT, BOUT, and SFS change on the rising edge of SCK (capture on falling edge). 1=They change on the falling edge of SCK. Determines polarity of the SFS output. 0=Active High. 1=Active Low. Determines polarity of the RDY output. 0=Active High. 1=Active Low. Determines the mode of the serial outputs. 0=Each channel is output on its respective pin, 1=Both channels are multiplexed and output on AOUT. See also Table 1. Controls when SFS goes active. 0=SFS pulses prior to the start of the I and the Q words. 1=SFS pulses only once prior to the start of each I/Q sample pair (i.e. the pair is treated as a double-sized word) The I word precedes the Q word. See Figure 30. Determines output number format. 0=Truncate serial output to 8 bits. Parallel output is truncated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0. 2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating point. 8-bit mantissa, 4-bit exponent. All other bits are set to 0. Frequency word for channel A. Format is a 32-bit, 2’s complement number spread across 4 registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_A/ 232. Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2 registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/ 2^16. Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4 registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_B/ 232. Phase word for channel B. Format is a 16-bit, unsigned magnitude number spread across 2 registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_B/ 2^16. 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel input source. 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel input source. 0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC channel to a 7 (maximum digital gain). This affects both channels. AGC_FORCE on the CLC5902. Do not use. AGC_RESET_EN on the CLC5902. Do not use. 0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both channels. Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels. AGC_COUNT on the CLC5902. Do not use. AGC fixed gain for channel A. Format is an 8-bit, unsigned magnitude number. The channel A DVGA gain will be set to the inverted three MSBs. DEC_BY_4 1b R/W 0 SCALE 6b R/W 0 2 5:0 GAIN_A GAIN_B RATE 3b 3b 1B R/W R/W R/W 0 0 1 3 4 5 2:0 2:0 7:0 SOUT_EN SCK_POL 1b 1b R/W R/W 0 0 6 6 0 1 SFS_POL RDY_POL MUX_MODE 1b 1b 1b R/W R/W R/W 0 0 0 6 6 6 2 3 4 PACKED 1b R/W 0 6 5 FORMAT 2b R/W 0 6 7:6 FREQ_A 4B R/W 0 7-10 7:0 PHASE_A 2B R/W 0 11-12 7:0 FREQ_B 4B R/W 0 13-16 7:0 PHASE_B 2B R/W 0 17-18 7:0 A_SOURCE 2 R/W 0 19 1:0 B_SOURCE 2 R/W 1 19 3:2 EXP_INH 1b R/W 0 20 0 Reserved Reserved AGC_HOLD_IC 1b 1b 1b R/W R/W R/W 1 0 0 20 20 20 1 2 3 AGC_LOOP_GAIN Reserved AGC_IC_A 2b 2B 1B R/W R/W R/W 0 0 0 20 21-22 23 4:5: 7:0 7:0 21 www.national.com CLC5903 Control Register Addresses and Defaults Register Name AGC_IC_B (Continued) Description Width 1B Type R/W Defaulta 0 Addr 24 Bit 7:0 AGC fixed gain for channel B. Format is an 8-bit, unsigned magnitude number. The channel B DVGA gain will be set to the inverted three MSBs. AGC integrator readback value for channel A. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel A integrator from this register. AGC integrator readback value for channel B. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel B integrator from this register. Test input source. Instead of processing values from the A|BIN pins, the value from this location is used instead. Format is 14-bit 2s complement number spread across 2 registers. For future use. For future use. 0=Normal. 1=Enables access to the internal probe points. Selects internal node tap for debug. 0 selects F1 output for BI, 20 bits 1 selects F1 output for BQ, 20 bits 2 selects F1 output for AQ, 20 bits 3 selects F1 output for AI, 20 bits 4 selects F1 input for BI, 20 bits 5 selects F1 input for BQ, 20 bits 6 selects F1 input for AI, 20 bits 7 selects F1 input for AQ, 20 bits 8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0. 9 selects NCO A, sine output, 17 bits, 3 LSBs are 0. 10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0. 11 selects NCO B, sine output, 17 bits, 3 LSBs are 0. 12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0. 13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0. 14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0. 15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0. 16-31 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits from ch B, 2 LSBs are 0. 0=Disable NCO dither source for channel A. 1=Enable. 0=Disable NCO dither source for channel B. 1=Enable. RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s complement numbers. This is common to both channels. Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one spread across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is in address 163. PAGE_SEL_F1=1 maps these addresses to coefficient memory B. Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one spread across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is in address 185. PAGE_SEL_F2=1 maps these addresses to coefficient memory B. Channel A F1 coefficient select register. 0=memory A, 1=memory B. Channel B F1 coefficient select register. 0=memory A, 1=memory B. F1 coefficient page select register. 0=memory A, 1=memory B. Channel A F2 coefficient select register. 0=memory A, 1=memory B. Channel B F2 coefficient select register. 0=memory A, 1=memory B. F2 coefficient page select register. 0=memory A, 1=memory B. 0=SFS asserted at the start of each output word when PACKED=1 or each I/Q pair when PACKED=0, 1=SFS asserted at the start of each output sample period. 0=normal serial mode, 1=serial daisy-chain master mode. Enable reduced bandwidth AGC power detector. 0=2nd-order decimate-by-eight CIC, 1=1-tap comb added to CIC, 2=4-tap comb added to CIC. Number of CK period delays in excess of 4 needed to align the DVGA gain step with the digital gain compensation step. Use the default of zero for the CLC5957 ADC. AGC_RB_A 1B R 0 25 7:0 AGC_RB_B 1B R 0 26 7:0 TEST_REG 14b R/W 0 27(LSBs) 28(MSBs) 7:0 5:0 Reserved Reserved DEBUG_EN DEBUG_TAP 1B 1B 1b 5b R/W R/W 0 0 29 30 31 31 7:0 7:0 0 5:1 DITH_A DITH_B AGC_TABLE 1b 1b 32B R/W R/W R/W 1 1 0 31 31 128-159 6 7 7:0 F1_COEFF 22B R/W 0 160-181 7:0 F2_COEFF 64B R/W 0 182-245 7:0 COEF_SEL_F1A COEF_SEL_F1B PAGE_SEL_F1 COEF_SEL_F2A COEF_SEL_F2B PAGE_SEL_F2 SFS_MODE 1b 1b 1b 1b 1b 1b 1b R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 246 246 246 247 247 247 248 0 1 2 0 1 2 0 SDC_EN AGC_COMB_ORD 1b 2b R/W R/W 0 0 248 249 1 1:0 EXT_DELAY 5b R/W 0 249 6:2 a. These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values. Condensed CLC5903 Address Map Register Name DEC Addr 0 Addr Hex 0x00 Bit7 Dec7 Bit6 Dec6 Bit5 Dec5 Bit4 Dec4 Bit3 Dec3 Bit2 Dec2 Bit1 Dec1 Bit0 Dec0 www.national.com 22 CLC5903 Condensed CLC5903 Address Map Register Name DEC_BY_4 SCALE GAIN_A GAIN_B RATE SERIAL_CTRL FREQ_A (Continued) Bit5 Bit4 DecBy4 Sc5 Sc4 Sc3 Addr 1 2 3 4 5 6 7 8 9 10 Addr Hex 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1F 0x80 0x9F 0xA0 0xB5 0xB6 0xF5 0xF6 0xF7 0xF8 0xF9 Bit7 Bit6 Bit3 Bit2 Dec10 Sc2 GA2 GB2 Bit1 Dec9 Sc1 GA1 GB1 Rate1 SCK_POL FA1 FA9 FA17 FA25 PA1 PA9 FB1 FB9 FB17 FB25 PB1 PB9 AS1 Reserved Reserved Reserved AgcIcA1 AgcIcB1 AgcRbA1 AgcRbB1 Test1 Test9 TapSel0 Bit0 Dec8 Sc0 GA0 GB0 Rate0 SOUT_EN FA0 FA8 FA16 FA24 PA0 PA8 FB0 FB8 FB16 FB24 PB0 PB8 AS0 ExpInh Reserved Reserved AgcIcA0 AgcIcB0 AgcRbA0 AgcRbB0 Test0 Test8 DebugEnable Rate7 FMT1 FA7 FA15 FA23 FA31 PA7 PA15 FB7 FB15 FB23 FB31 PB7 PB15 Rate6 FMT0 FA6 FA14 FA22 FA30 PA6 PA14 FB6 FB14 FB22 FB30 PB6 PB14 Rate5 Packed FA5 FA13 FA21 FA29 PA5 PA13 FB5 FB13 FB21 FB29 PB5 PB13 Rate4 MuxMode FA4 FA12 FA20 FA28 PA4 PA12 FB4 FB12 FB20 FB28 PB4 PB12 Rate3 RDY_POL FA3 FA11 FA19 FA27 PA3 PA11 FB3 FB11 FB19 FB27 PB3 PB11 BS1 Rate2 SFS_POL FA2 FA10 FA18 FA26 PA2 PA10 FB2 FB10 FB18 FB26 PB2 PB10 BS0 Reserved Reserved Reserved AgcIcA2 AgcIcB2 AgcRbA2 AgcRbB2 Test2 Test10 TapSel1 PHASE_A 11 12 FREQ_B 13 14 15 16 PHASE_B 17 18 SOURCE AGC_CTRL AGC_COUNT 19 20 21 22 AgcLG1 Reserved Reserved AgcIcA7 AgcIcB7 AgcRbA7 AgcRbB7 Test7 Reserved Reserved AgcIcA6 AgcIcB6 AgcRbA6 AgcRbB6 Test6 Reserved Reserved AgcIcA5 AgcIcB5 AgcRbA5 AgcRbB5 Test5 Test13 DITH_B DITH_A TapSel4 AgcLG0 Reserved Reserved AgcIcA4 AgcIcB4 AgcRbA4 AgcRbB4 Test4 Test12 TapSel3 AgcHldIC Reserved Reserved AgcIcA3 AgcIcB3 AgcRbA3 AgcRbB3 Test3 Test11 TapSel2 AGC_IC_A AGC_IC_B AGC_RB_A AGC_RB_A TEST_REG 23 24 25 26 27 28 DEBUG AGC_TABLE 31 128 159 The AGC Table loads from the low address to the high address in this order: “1st location, 2nd location…” F1_COEFF 160 181 The FIR Coefficients load from the low address to the high address in this order: “1st location low byte, 1st location high byte, 2nd location…” The Page Select bits determine which set of coefficient memory is written. PgSelF1 PgSelF2 CfSelF1B CfSelF2B SdcEn ExtDelay4 ExtDelay3 ExtDelay2 ExtDelay1 ExtDelay0 CombOrd1 CfSelF1A CfSelF2A SfsMode CombOrd0 F2_COEFF 182 245 F1_CTRL F2_CTRL SERIAL_CTRL2 AGC_CTRL2 246 247 248 249 23 www.national.com CLC5903 AGC Theory of Operation (Continued) AGC Theory of Operation A block diagram of the AGC is shown in Figure 34. The DVGA interface comprises four pins for each of the channels. The first three pins of this interface are a 3-bit binary word that controls the DVGA gain in 6dB steps (AGAIN). The final pin is ASTROBE which allows the AGAIN bits to be latched into the DVGA’s register. A key feature of the A STROBE , illustrated Figure 35, is that it toggles only if the data on AGAIN has changed from the previous cycle. Not shown is that ASTROBE and BSTROBE are independent. For example, A STROBE o nly toggles when AGAIN h as changed. BSTROBE w ill not toggle because AGAIN has changed. This is done to minimize unnecessary digital noise on the sensitive analog path through the DVGA. A STROBE a nd BSTROBE are asserted during MR and SI to properly initialize the DVGAs. The absolute value circuit and the 2-stage, decimate-by-8 CIC filter comprise the power detection part of the AGC. The power detector bandwidth is set by the CIC filter to F CK/8. The absolute value circuit doubles the effective input frequency. This has the effect of reducing the power detector bandwidth from FCK/8 to FCK/16. For a full-scale sinusoidal input, the absolute value circuit output is a dc value of 511 ⋅ ( 2 ⁄ π ) . Because the absolute value circuit also generates undesired even harmonic terms, the CIC filter (response shown in Figure 36), is required to, remove these harmonics. The first response null occurs at FCK/8, where FCK is the clock frequency, and the response magnitude is at least 25dB below the dc value from FCK/10 to 9FCK/10. Because the 2nd harmonic from the absolute value 10 0 AGC Power Detection Filter: Amplitude Response CIC CIC + 1−tap Comb CIC + 4−tap Comb AGC_COMB_ORD=2 −10 AGC_COMB_ORD=0 −20 AGC_COMB_ORD=1 −30 Magnitude/dB −40 −50 −60 −70 −80 −90 −100 0 5 10 15 20 25 30 Frequency/MHz 35 40 45 50 Figure 36. Power detector filter response, 52MHz circuit is about 10dB below the dc this means that the ripple in the detected level is about 0.7dB or less for input frequencies between FCK/20 to 19FCK/20. Setting the AGC_COMB_ORD register to either 1 or 2 will narrow the power detector’s bandwidth as shown in Figure 36. The “FIXED TO FLOAT CONVERTER” takes the fixed point 9-bit output from the CIC filter and converts it to a “floating point” number. This conversion is done so that the 32 values in the RAM can be uniformly assigned (dB scale) to detected power levels (54 dB range). This provides a resolution of 1.7dB between detected power levels. The truth table for this converter is given in Table 3. The upper three bits of the output represent the exponent (e) and the lower 2 are the mantissa (m). The exponent is determined by the position of the AGC_TABLE AGC_LOOP_GAIN EXP 2 STAGE DECIMATE BY 8 CIC FILTER POST CIC COMB FILTER SHIFT DOWN FIXED TO FLOAT CONVERTER AIN[13:4] (from MUXA) 32X8 RAM POUT 9 SHIFT DOWN ABSOLUTE VALUE 12 10 16 9 5 8 AGAIN 12 3 MUX AGC_IC_A FUNCTION PROGRAMMED INTO RAM LOG AGC_HOLD_IC -REF Figure 34. CLC5903 AGC circuit, Channel A ASTROBE does not pulse because AGAIN[2:0] does not change CK CK/8 ASTROBE AGAIN[2:0] Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information. www.national.com 24 CLC5903 AGC Theory of Operation (Continued) leading ‘1’ out of the CIC filter. An output of ‘001XX’ corresponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent increases by one each time the leading ‘1’ advances in bit position. The mantissa bits are the two bits that follow the leading ‘1’. If we define E as the decimal value of the exponent bits and M as the decimal value of the mantissa bits, the output of the CIC filter, P OUT, corresponding to a given “FIXED TO FLOAT CONVERTER” output is, P OUT = [ 4 ⋅ min ( E, 1 ) + M ] ⋅ 2 ( max ( E, 1 ) – 1 ) The reference subtraction is constructed by subtracting the desired loop servo point (in dB) from the table values computed in the previous paragraph. For example, if it is desired that the DVGA servo the ADC input level (sinusoidal signal) to -6dBFS, the number to subtract from the data is 511 2 -20 log  --------- ⋅ --  = 44 dB .  2 π (8) (5) , E ≥ 1. The max() and min() operators account for row 1 of Table 3 which is a special case because M=POUT. Equation 5 associates each address of the RAM with a CIC filter output. INPUT 0-3 4-7 8-15 16-31 32-63 64-127 128-255 256-511 The table data will then cross through zero at the address corresponding to this reference level. A deadband wider than 6dB should then be constructed symmetrically about this point. This prevents the loop from hunting due to the 6dB gain steps of the DVGA. Any deadband in excess of 6dB appears as hysteresis in the servo point of the loop as illustrated in Figure 33. The deadband is constructed by loading zeros into those addresses on either side of the one which corresponds to the reference level. The last function of the RAM table is that of error amplification. All the operations preceding this one gave a table slope S RAM = 1 . This must now be adjusted in order to control the time constant of the loop given by, 8 1 1 τ = ----------  ------ + --  . -F CK  G L 2 The term GL in this equation is the loop gain, G L = – 6.02 ⋅ S RAM ⋅ 2 ( AGC_LOOP_GAIN – 8 ) OUTPUT (eeemm) 000XX 001XX 010XX 011XX 100XX 101XX 110XX 111XX (9) . (10) The design equations are obtained by solving Equation 9 for GL and Equation 10 for S RAM . AGC_LOOP_GAIN is a control register value that determines the number of bits to shift the output of the RAM down by. This allows some of the loop gain to be moved out of the RAM so that the full output range of the table is utilized but not exceeded. The valid range for AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 1 to 4 bit shift left. An example set of numbers to implement a loop having a reference of 6dB below full scale, a deadband of 8dB, and a loop gain of 0.108 is: -102 -102 -88 -80 -75 -70 -66 -63 -61 -56 -53 -50 -47 -42 -39 -36 -33 -29 -25 -22 -19 -15 -11 0 0 0 0 0 0 13 17 20 Table 3. Fixed to Float Converter Truth Table As shown in Figure 34, the 32X8 RAM look-up table implements the functions of log converter, reference subtraction, error amplifier, and deadband. The user must build each of these functions by constructing a set of 8-bit, 2’s complement numbers to be loaded into the RAM. Each of these functions and how to construct them are discussed in the following paragraphs. A log conversion is done in order to keep the loop gain independent of operating point. To see why this is beneficial, the control gain of the DVGA computed without log conversion is, ′ K DVGA ( G – Go ) ∂ = (v ⋅ 2 ), ∂G i = – v i ⋅ ln ( 2 ) ⋅ 2 ( G – Go ) (6) , These values are shown plotted in Figure 37 with respect to the table addresses in (a), and the CIC filter output POUT in (b). For a 52MHz clock rate and AGC_LOOP_GAIN=2, these values result in a loop time constant of 1.5 µ s . The error signal from the loop gain “SHIFT DOWN” circuit is gated into the loop integrator. The gate is controlled by a timing and control circuit discussed in the next paragraph. A MUX within the integrator feedback allows the integrator to be initialized to the value loaded into AGC_IC_A (channel B can be set independently). The conditions under which it is initialized are configured in the registers associated with the timing and control circuit. The top eight bits of the integrator output can also be read back over the microprocessor interface from the AGC_RB_A (or AGC_RB_B) register. The top 3 bits below the sign become AGAIN and are output along with ASTROBE signal on the DVGA interface pins. The valid range of AGAIN is from 0 to 7 which corresponds to a valid range of 0 to 210-1 for the 11-bit, 2’s complement integrator output from which AGAIN is derived. This is illustrated in Fig- where G is the decimal equivalent of GAIN and Go accounts for the DVGA gain in excess of unity. This equation assumes that the DVGA gain control polarity is positive as is the case for the CLC5526. The gain around the entire loop must be negative. Observe in Equation 6 that the control gain is dependent on operating point G. If we instead compute the control gain with log conversion, K DVGA = ( G – Go ) ∂ [ 20 ⋅ log ( v i ⋅ 2 )], ∂G (7) = – 6.02, which is no longer operating-point dependent. The log function is constructed by computing the CIC filter output associated with each address (Equation 5) and converting these to dB. Full scale (dc signal) is 20 log ( 511 ) = 54 dB . 25 www.national.com CLC5903 20 20 AGC RAM CONTENTS AGC RAM CONTENTS 0 0 -20 -20 -40 -40 -60 -60 -80 -80 -100 -100 -120 0 5 10 15 20 25 30 -120 0 10 20 30 40 50 60 ADDRESS POUT (dB) (a) (b) Figure 37. Example of programmed RAM contents AGAINa 000 = -12dB 001 = -6dB 010 = +0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB EXPb 111 = +0dB 110 = -6dB 101 = -12dB 100 = -18dB 011 = -24dB 010 = -30dB 001 = -36dB 000 = -42dB Inputc -12dB -12dB -12dB -12dB -12dB -12dB -12dB -12dB 21 14 14 14 14 14 14 14 14 20 13 14 14 14 14 14 14 14 19 12 13 14 14 14 14 14 14 18 11 12 13 14 14 14 14 14 17 10 11 12 13 14 14 14 14 16 9 10 11 12 13 14 14 14 15 8 9 10 11 12 13 14 14 14 7 8 9 10 11 12 13 14 ... ... ... ... ... ... ... ... ... 8 1 2 3 4 5 6 7 8 7 0 1 2 3 4 5 6 7 6 L 0 1 2 3 4 5 6 5 L L 0 1 2 3 4 5 4 L L L 0 1 2 3 4 3 L L L L 0 1 2 3 2 L L L L L 0 1 2 1 L L L L L L 0 1 0 L L L L L L L 0 Table 4. 15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP.d a. AGAIN sets the DVGA or analog gain value. b. EXP sets the “FIXED TO FLOAT CONVERTER” or digital gain value. c. 22-bit input to SHIFT-UP block in Figure 16 horizontally, linearized SHIFT-UP value vertically. d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low. ure 38. The integrator saturates at these limits to prevent overshoots as the integrator attempts to enter the valid range. The AGAIN value is inverted ( EXP ) and used to adjust the gain of the incoming signal to provide a linear output dynamic range. The relationship between the DVGA analog gain (AGAIN) and the “FIXED TO FLOAT CONVERTER” digital gain (EXP) is shown in Table 4. The DVGA’s compression of the incoming signal in the analog domain vs. the subsequent expansion in the digital domain is shown in Figure 32. The AG C m ay be forc ed t o fr ee r un by se tt ing AG C _ H O L D _ I C l o w. W r i t i n g a n i n i t i a l c o n d i t i o n t o AGC_IC_A|B and then setting AGC_HOLD_IC high will force the AGC to a fixed gain. The three MSBs of the value written to AGC_IC_A|B are inverted and output to drive the DVGA. Allowing the AGC to free run should be appropriate for most applications. If the INH_EXP bit is not set, the DVGA gain word ( EXP ) is routed to the “FLOAT TO FIXED CONVERTER” in the DDCs prior to the programmable decimation filter. The EXP signals are delayed to account for the propagation delay of the DVGA interface and the CLC5957 ADC. 7 For this range to be the same size as all others, the max integrator output must be limited to 8x27-1=210-1 6 5 AGAIN 4 3 2 1 The min integrator output must be limited to 0 so that the sign of AGAIN is positive 0 1x27 2x27 3x27 4x27 5x27 6x27 7x27 8x27 0 Integrator Output Figure 38. AGC integrator output limits www.national.com 26 CLC5903 Evaluation Hardware Evaluation boards are available to facilitate designs based on the CLC5903: CLC-EDRCS-PCASM The Enhanced Diversity Receiver Chipset evaluation board providing a complete narrowband receiver from IF to digital symbols. CLC-CAPT-PCASM A simple method for capturing output data from CLC ADCs and the CLC5903. SOFTWARE Control panel software for the CLC5903 supports complete device configuration on both evaluation boards. Capture software manages the capture of data and its storage in a file on a PC. Matlab script files support data analysis: FFT, DNL, and INL plotting. This software and additional application information is available on the CLC Evaluation Kit CDROM. 27 www.national.com CLC5903 Physical Dimensions inches (millimeters) unless otherwise noted. CLC5903SM Figure 39. CLC5903SM FBGA Package Dimensions www.national.com 28 CLC5903 Dual Digital Tuner / AGC Physical Dimensions inches (millimeters) unless otherwise noted CLC5903VLA D ETAIL A Dimension are in millimeters Figure 40. CLC5903VLA PQFP Package Dimensions LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com Fax: +49 (0) 180-530 85 86 E-mail: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.